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author Vas Crabb <vas@vastheman.com>2016-06-22 11:10:42 +1000
committer Vas Crabb <vas@vastheman.com>2016-06-22 11:11:01 +1000
commit5b9e7bcccf52458e365b8759c8a0c4b5e51d166e (patch)
treea60f2b1709298c4afb02ae16a99d6ee8d0c21f4a /src/devices/cpu/sparc/sparc.h
parent496fb0609b80538623441578199373eb460d6e31 (diff)
SPARC disassembler improvements: [Vas Crabb]
* Fix addcc/andcc in SPARCv7 mode and simplify integer op tables * Allow ASI descriptions to be supplied with MCFG macro sun4: add SPARC ASI descriptions [Vas Crabb]
Diffstat (limited to 'src/devices/cpu/sparc/sparc.h')
-rw-r--r--src/devices/cpu/sparc/sparc.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/devices/cpu/sparc/sparc.h b/src/devices/cpu/sparc/sparc.h
index a646a80040c..a5e31751ed2 100644
--- a/src/devices/cpu/sparc/sparc.h
+++ b/src/devices/cpu/sparc/sparc.h
@@ -40,6 +40,10 @@
#define SPARC_INT15 31
#define SPARC_TRAP_INSTRUCTION 128
+// TODO: when there are more SPARC CPUs, move setter to a base class
+#define MCFG_SPARC_ADD_ASI_DESC(desc) \
+ mb86901_device::add_asi_desc(*device, desc);
+
class mb86901_device : public cpu_device
{
public:
@@ -76,7 +80,11 @@ public:
void hold_bus() { m_hold_bus = true; }
void release_bus() { m_hold_bus = false; }
+ template<typename T> static void add_asi_desc(device_t &device, const T &desc) { return downcast<mb86901_device &>(device).add_asi_desc(desc); }
+
protected:
+ template<typename T> void add_asi_desc(const T &desc) { m_dasm.add_asi_desc(desc); }
+
bool invoke_queued_traps();
bool check_main_traps(UINT32 op, bool privileged, UINT32 alignment, UINT8 registeralign, bool noimmediate);