diff options
author | 2020-01-06 23:20:24 -0500 | |
---|---|---|
committer | 2020-01-06 23:20:28 -0500 | |
commit | 2645475b752919e2c6891ee35f0a4c4493336f36 (patch) | |
tree | 6d6de24fa094627b91ebd179a38d059d1eee133e /src/devices/cpu/rx01 | |
parent | 0d06ae9f4d3541a6a9c26a5f600c34914c2d9b4e (diff) |
rx01_cpu: Start executing some instructions (nw)
Diffstat (limited to 'src/devices/cpu/rx01')
-rw-r--r-- | src/devices/cpu/rx01/rx01.cpp | 143 | ||||
-rw-r--r-- | src/devices/cpu/rx01/rx01.h | 16 |
2 files changed, 149 insertions, 10 deletions
diff --git a/src/devices/cpu/rx01/rx01.cpp b/src/devices/cpu/rx01/rx01.cpp index 149c43e30f2..db6fe74848c 100644 --- a/src/devices/cpu/rx01/rx01.cpp +++ b/src/devices/cpu/rx01/rx01.cpp @@ -10,24 +10,33 @@ #include "rx01.h" #include "rx01dasm.h" +//#define VERBOSE 1 +#include "logmacro.h" + // device type definition DEFINE_DEVICE_TYPE(RX01_CPU, rx01_cpu_device, "rx01_cpu", "DEC RX01 CPU") rx01_cpu_device::rx01_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) : cpu_device(mconfig, RX01_CPU, tag, owner, clock) - , m_rom_config("program", ENDIANNESS_LITTLE, 8, 12, 0) + , m_inst_config("program", ENDIANNESS_LITTLE, 8, 12, 0) , m_sp_config("scratchpad", ENDIANNESS_LITTLE, 8, 4, 0, address_map_constructor(FUNC(rx01_cpu_device::scratchpad_map), this)) - , m_rom_cache(nullptr) + , m_inst_cache(nullptr) , m_sp_cache(nullptr) , m_pc(0) + , m_ppc(0) + , m_mb(0) + , m_br_condition(false) + , m_inst_disable(false) + , m_inst_repeat(false) , m_cntr(0) , m_sr(0) , m_spar(0) , m_bar(0) , m_crc(0) + , m_flag(false) , m_icount(0) { - m_rom_config.m_is_octal = true; + m_inst_config.m_is_octal = true; m_sp_config.m_is_octal = true; } @@ -44,14 +53,14 @@ void rx01_cpu_device::scratchpad_map(address_map &map) device_memory_interface::space_config_vector rx01_cpu_device::memory_space_config() const { return space_config_vector { - std::make_pair(AS_PROGRAM, &m_rom_config), + std::make_pair(AS_PROGRAM, &m_inst_config), std::make_pair(AS_DATA, &m_sp_config) }; } void rx01_cpu_device::device_start() { - m_rom_cache = space(AS_PROGRAM).cache<0, 0, ENDIANNESS_LITTLE>(); + m_inst_cache = space(AS_PROGRAM).cache<0, 0, ENDIANNESS_LITTLE>(); m_sp_cache = space(AS_DATA).cache<0, 0, ENDIANNESS_LITTLE>(); set_icountptr(m_icount); @@ -71,28 +80,146 @@ void rx01_cpu_device::device_start() // Save state registration save_item(NAME(m_pc)); + save_item(NAME(m_ppc)); + save_item(NAME(m_mb)); + save_item(NAME(m_br_condition)); + save_item(NAME(m_inst_disable)); + save_item(NAME(m_inst_repeat)); save_item(NAME(m_cntr)); save_item(NAME(m_sr)); save_item(NAME(m_spar)); save_item(NAME(m_bar)); save_item(NAME(m_crc)); + save_item(NAME(m_flag)); } void rx01_cpu_device::device_reset() { // Clear address registers, counters and flags m_pc = 0; + m_mb = 0; + m_inst_disable = false; + m_inst_repeat = false; m_bar = 0; m_cntr = 0; m_sr = 0; m_spar = 0; + m_flag = false; +} + +u8 rx01_cpu_device::mux_out() +{ + return BIT(m_mb, 0) ? m_sp_cache->read_byte(m_spar) : m_inst_cache->read_byte(m_pc); +} + +bool rx01_cpu_device::test_condition() +{ + switch (m_mb & 074) + { + case 020: + return BIT(m_sr, 7); + + case 024: + return m_cntr == 0377; + + case 030: + return BIT(m_crc, 0); + + case 074: + return m_flag; + + default: + LOG("%04o: Unhandled branch condition %d\n", m_ppc, (m_mb & 074) >> 2); + return true; + } } void rx01_cpu_device::execute_run() { - // TODO - debugger_instruction_hook(m_pc); - m_icount = 0; + while (m_icount > 0) + { + if (m_inst_disable) + { + if ((m_mb & 0302) == 0202) + m_pc = u16(m_mb & 074) << 6 | mux_out(); + else if (BIT(m_mb, 6) && m_br_condition) + m_pc = ((m_pc + 1) & 07400) | mux_out(); + else + m_pc = (m_pc + 1) & 07777; + + m_inst_disable = false; + m_inst_repeat = false; + } + else + { + if (!m_inst_repeat) + { + m_ppc = m_pc; + debugger_instruction_hook(m_pc); + + m_mb = m_inst_cache->read_byte(m_pc); + m_pc = (m_pc + 1) & 03777; + } + + if (BIT(m_mb, 6)) + { + m_br_condition = test_condition() == BIT(m_mb, 1); + if (BIT(m_mb, 7)) + { + m_inst_disable = m_cntr == 0377 || m_br_condition; + m_inst_repeat = m_cntr != 0377 && !m_br_condition; + m_cntr++; + } + else + m_inst_disable = true; + } + else if (BIT(m_mb, 7)) + { + if (BIT(m_mb, 1)) + m_inst_disable = true; + else + m_spar = (m_mb & 074) >> 2; + } + else switch (m_mb & 074) + { + case 044: + if (BIT(m_mb, 1)) + m_bar = (m_bar + 1) & 07777; + else + m_bar = BIT(m_mb, 0) ? 0 : 06000; + break; + + case 060: + m_flag = (!BIT(m_mb, 0) && m_flag) || (BIT(m_mb, 1) && !m_flag); + break; + + case 064: + m_sp_cache->write_byte(m_spar, m_sr); + break; + + case 070: + if (BIT(m_mb, 1)) + m_cntr++; + else + m_cntr = mux_out(); + m_inst_disable = !BIT(m_mb, 0); + break; + + case 074: + if ((m_mb & 3) == 1) + m_sr = m_cntr; + else + m_sr = (m_sr << 1) | (BIT(m_mb, 0) ? 0 /*sep_data()*/ : BIT(m_mb, 1)); + break; + + default: + LOG("%04o: Unimplemented instruction %03o\n", m_ppc, m_mb); + break; + } + } + + m_icount--; + } } void rx01_cpu_device::state_string_export(const device_state_entry &entry, std::string &str) const diff --git a/src/devices/cpu/rx01/rx01.h b/src/devices/cpu/rx01/rx01.h index f491c8ba56a..ab1cbc123c8 100644 --- a/src/devices/cpu/rx01/rx01.h +++ b/src/devices/cpu/rx01/rx01.h @@ -27,6 +27,8 @@ protected: virtual void device_reset() override; // device_execute_interface overrides + virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 4 - 1) / 4; } + virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 4); } virtual void execute_run() override; // device_disasm_interface overrides @@ -41,19 +43,29 @@ protected: private: void scratchpad_map(address_map &map); + // internal helpers + u8 mux_out(); + bool test_condition(); + // address spaces - address_space_config m_rom_config; + address_space_config m_inst_config; address_space_config m_sp_config; - memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_rom_cache; + memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_inst_cache; memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_sp_cache; // internal state u16 m_pc; + u16 m_ppc; + u8 m_mb; + bool m_br_condition; + bool m_inst_disable; + bool m_inst_repeat; u8 m_cntr; u8 m_sr; u8 m_spar; u16 m_bar; u16 m_crc; + bool m_flag; s32 m_icount; }; |