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author AJR <ajrhacker@users.noreply.github.com>2017-11-18 19:37:43 -0500
committer AJR <ajrhacker@users.noreply.github.com>2017-11-18 19:38:48 -0500
commit0f1d2011fe284045627647fdb201107dd5d6bce0 (patch)
tree1e959445132d3cc0d5095e8ba3f61a6ca6bb61e1 /src/devices/cpu/powerpc/ppcdrc.cpp
parent764c6de06012555d627d1f09c066868c31ca8a7f (diff)
Attempt at fixing PPC DRC scheduling bug (MT #6615)
N.B. My development machine lacks the computing power to test this rigorously (it at least seems to work for scud).
Diffstat (limited to 'src/devices/cpu/powerpc/ppcdrc.cpp')
-rw-r--r--src/devices/cpu/powerpc/ppcdrc.cpp10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/devices/cpu/powerpc/ppcdrc.cpp b/src/devices/cpu/powerpc/ppcdrc.cpp
index 741e75f9cc2..2d2a8f0dcee 100644
--- a/src/devices/cpu/powerpc/ppcdrc.cpp
+++ b/src/devices/cpu/powerpc/ppcdrc.cpp
@@ -3316,7 +3316,7 @@ bool ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *co
UML_MOV(block, R32(G_RD(op)), m_flavor); // mov rd,flavor
else
{
- generate_update_cycles(block, compiler, desc->pc, true); // <update cycles>
+ generate_update_cycles(block, compiler, desc->pc, false); // <update cycles>
UML_MOV(block, mem(&m_core->param0), spr); // mov [param0],spr
UML_CALLC(block, (c_function)cfunc_ppccom_execute_mfspr, this); // callc ppccom_execute_mfspr,ppc
UML_MOV(block, R32(G_RD(op)), mem(&m_core->param1)); // mov rd,[param1]
@@ -3338,7 +3338,7 @@ bool ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *co
uint32_t tbr = compute_spr(G_SPR(op));
if (tbr != SPRVEA_TBL_R && tbr != SPRVEA_TBU_R)
return false;
- generate_update_cycles(block, compiler, desc->pc, true); // <update cycles>
+ generate_update_cycles(block, compiler, desc->pc, false); // <update cycles>
UML_MOV(block, mem(&m_core->param0), tbr); // mov [param0],tbr
UML_CALLC(block, (c_function)cfunc_ppccom_execute_mftb, this); // callc ppccom_execute_mftb,ppc
UML_MOV(block, R32(G_RD(op)), mem(&m_core->param1)); // mov rd,[param1]
@@ -3383,7 +3383,7 @@ bool ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *co
; // read only
else
{
- generate_update_cycles(block, compiler, desc->pc, true); // <update cycles>
+ generate_update_cycles(block, compiler, desc->pc, false); // <update cycles>
UML_MOV(block, mem(&m_core->param0), spr); // mov [param0],spr
UML_MOV(block, mem(&m_core->param1), R32(G_RS(op))); // mov [param1],rs
UML_CALLC(block, (c_function)cfunc_ppccom_execute_mtspr, this); // callc ppccom_execute_mtspr,ppc
@@ -3429,7 +3429,7 @@ bool ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *co
{
uint32_t spr = compute_spr(G_SPR(op));
assert(m_cap & PPCCAP_4XX);
- generate_update_cycles(block, compiler, desc->pc, true); // <update cycles>
+ generate_update_cycles(block, compiler, desc->pc, false); // <update cycles>
UML_MOV(block, mem(&m_core->param0), spr); // mov [param0],spr
UML_CALLC(block, (c_function)cfunc_ppccom_execute_mfdcr, this); // callc ppccom_execute_mfdcr,ppc
UML_MOV(block, R32(G_RD(op)), mem(&m_core->param1)); // mov rd,[param1]
@@ -3440,7 +3440,7 @@ bool ppc_device::generate_instruction_1f(drcuml_block *block, compiler_state *co
{
uint32_t spr = compute_spr(G_SPR(op));
assert(m_cap & PPCCAP_4XX);
- generate_update_cycles(block, compiler, desc->pc, true); // <update cycles>
+ generate_update_cycles(block, compiler, desc->pc, false); // <update cycles>
UML_MOV(block, mem(&m_core->param0), spr); // mov [param0],spr
UML_MOV(block, mem(&m_core->param1), R32(G_RS(op))); // mov [param1],rs
UML_CALLC(block, (c_function)cfunc_ppccom_execute_mtdcr, this); // callc ppccom_execute_mtdcr,ppc