diff options
| author |   Patrick Mackinlay <pmackinlay@hotmail.com> | 2023-06-07 09:02:34 +0700 |
|---|---|---|
| committer | Patrick Mackinlay <pmackinlay@hotmail.com> | 2023-06-07 09:02:34 +0700 |
| commit | f3f10eef0f754f13b93787faa405f2180dff897a (patch) | |
| tree | a5aa20899bf9f912119a96d3b7d28076fe9ea444 /src/devices/cpu/mips | |
| parent | eed6108b151582384b522d6c7dacf772e80559d3 (diff) | |
mips3: fix tlb modify exception registers
Diffstat (limited to 'src/devices/cpu/mips')
| -rw-r--r-- | src/devices/cpu/mips/mips3com.cpp | 2 | ||||
| -rw-r--r-- | src/devices/cpu/mips/mips3drc.cpp | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/devices/cpu/mips/mips3com.cpp b/src/devices/cpu/mips/mips3com.cpp index cf8e65cd5af..2a9a933ef87 100644 --- a/src/devices/cpu/mips/mips3com.cpp +++ b/src/devices/cpu/mips/mips3com.cpp @@ -143,7 +143,7 @@ generate_tlb_index - generate a random tlb index uint32_t mips3_device::generate_tlb_index() { // Actual hardware uses a free running counter to generate the index. - // This impementation uses a linear congruential generator so that DRC and non-DRC code sequences match. + // This implementation uses a linear congruential generator so that DRC and non-DRC code sequences match. m_tlb_seed = 214013 * m_tlb_seed + 2531011; return (m_tlb_seed >> 16) & 0x3f; } diff --git a/src/devices/cpu/mips/mips3drc.cpp b/src/devices/cpu/mips/mips3drc.cpp index 1b1683b8d65..b2b4cf22a35 100644 --- a/src/devices/cpu/mips/mips3drc.cpp +++ b/src/devices/cpu/mips/mips3drc.cpp @@ -756,7 +756,7 @@ void mips3_device::static_generate_exception(uint8_t exception, int recover, con UML_MOV(block, CPR032(COP0_BadVAddr), I0); // mov [BadVAddr],i0 } - if (exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE) + if (exception == EXCEPTION_TLBMOD || exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE) { /* set the upper bits of EntryHi and the lower bits of Context to the fault page */ UML_ROLINS(block, CPR032(COP0_EntryHi), I0, 0, 0xffffe000); // rolins [EntryHi],i0,0,0xffffe000 @@ -2610,7 +2610,7 @@ bool mips3_device::generate_set_cop0_reg(drcuml_block &block, compiler_state &co { case COP0_Cause: UML_ROLINS(block, CPR032(COP0_Cause), I0, 0, ~0xfc00); // rolins [Cause],i0,0,~0xfc00 - compiler.checksoftints = true; + compiler.checkints = true; if (!in_delay_slot) generate_update_cycles(block, compiler, desc->pc + 4, true); return true; |