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author | 2019-03-25 23:13:40 +0100 | |
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committer | 2019-03-25 23:13:40 +0100 | |
commit | b380514764cf857469bae61c11143a19f79a74c5 (patch) | |
tree | 63c8012e262618f08a332da31dd714281aa2c5ed /src/devices/cpu/mips/mips3.h | |
parent | c24473ddff715ecec2e258a6eb38960cf8c8e98e (diff) |
Revert "conflict resolution (nw)"
This reverts commit c24473ddff715ecec2e258a6eb38960cf8c8e98e, reversing
changes made to 009cba4fb8102102168ef32870892438327f3705.
Diffstat (limited to 'src/devices/cpu/mips/mips3.h')
-rw-r--r-- | src/devices/cpu/mips/mips3.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/devices/cpu/mips/mips3.h b/src/devices/cpu/mips/mips3.h index 0afa4ef610b..8d16c6cbd84 100644 --- a/src/devices/cpu/mips/mips3.h +++ b/src/devices/cpu/mips/mips3.h @@ -297,7 +297,6 @@ public: void set_icache_size(size_t icache_size) { c_icache_size = icache_size; } void set_dcache_size(size_t dcache_size) { c_dcache_size = dcache_size; } - void set_secondary_cache_line_size(uint8_t secondary_cache_line_size) { c_secondary_cache_line_size = secondary_cache_line_size; } void set_system_clock(uint32_t system_clock) { c_system_clock = system_clock; } TIMER_CALLBACK_MEMBER(compare_int_callback); @@ -437,13 +436,11 @@ protected: bool m_bigendian; uint32_t m_byte_xor; uint32_t m_word_xor; - uint32_t m_dword_xor; data_accessors m_memory; /* cache memory */ size_t c_icache_size; size_t c_dcache_size; - uint8_t c_secondary_cache_line_size; /* MMU */ mips3_tlb_entry m_tlb[MIPS3_MAX_TLB_ENTRIES]; |