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author Olivier Galibert <galibert@pobox.com>2020-05-25 16:42:42 +0200
committer Olivier Galibert <galibert@pobox.com>2020-05-25 16:42:57 +0200
commit22513fb6fe281f5ccb75aaddb6417a12a66c313d (patch)
tree3cf84032cc6482d685a8dbb57e015bd17c7f7fdc /src/devices/cpu/mcs48/mcs48.h
parente42c2d2874cf9c1092c01ab5ce9ef997d465ce25 (diff)
emumem: A little more speedup. cache and specific change syntax, and are not pointers anymore [O. Galibert]
The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
Diffstat (limited to 'src/devices/cpu/mcs48/mcs48.h')
-rw-r--r--src/devices/cpu/mcs48/mcs48.h17
1 files changed, 8 insertions, 9 deletions
diff --git a/src/devices/cpu/mcs48/mcs48.h b/src/devices/cpu/mcs48/mcs48.h
index 8041d11a89d..572c09b6bec 100644
--- a/src/devices/cpu/mcs48/mcs48.h
+++ b/src/devices/cpu/mcs48/mcs48.h
@@ -216,10 +216,9 @@ protected:
int m_icount;
/* Memory spaces */
- address_space *m_program;
- memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_cache;
- address_space *m_data;
- address_space *m_io;
+ memory_access<12, 0, 0, ENDIANNESS_LITTLE>::cache m_program;
+ memory_access<8, 0, 0, ENDIANNESS_LITTLE>::specific m_data;
+ memory_access<8, 0, 0, ENDIANNESS_LITTLE>::specific m_io;
required_shared_ptr<uint8_t> m_dataptr;
@@ -235,15 +234,15 @@ protected:
const mcs48_ophandler *const m_opcode_table;
/* ROM is mapped to AS_PROGRAM */
- uint8_t program_r(offs_t a) { return m_program->read_byte(a); }
+ uint8_t program_r(offs_t a) { return m_program.read_byte(a); }
/* RAM is mapped to AS_DATA */
- uint8_t ram_r(offs_t a) { return m_data->read_byte(a); }
- void ram_w(offs_t a, uint8_t v) { m_data->write_byte(a, v); }
+ uint8_t ram_r(offs_t a) { return m_data.read_byte(a); }
+ void ram_w(offs_t a, uint8_t v) { m_data.write_byte(a, v); }
/* ports are mapped to AS_IO and callbacks */
- uint8_t ext_r(offs_t a) { return m_io->read_byte(a); }
- void ext_w(offs_t a, uint8_t v) { m_io->write_byte(a, v); }
+ uint8_t ext_r(offs_t a) { return m_io.read_byte(a); }
+ void ext_w(offs_t a, uint8_t v) { m_io.write_byte(a, v); }
uint8_t port_r(offs_t a) { return m_port_in_cb[a - 1](); }
void port_w(offs_t a, uint8_t v) { m_port_out_cb[a - 1](v); }
int test_r(offs_t a) { return m_test_in_cb[a](); }