summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/cpu/m68000/m68000.h
diff options
context:
space:
mode:
author Vas Crabb <vas@vastheman.com>2018-11-25 11:49:51 +1100
committer Vas Crabb <vas@vastheman.com>2018-11-25 11:49:51 +1100
commitf99c502820eac58590f99f840bdf4b90196066aa (patch)
tree033834459f68a24609126c4b201db21b308b563b /src/devices/cpu/m68000/m68000.h
parent5babaee6238c5d5b8298daf2f3fe3c7b48457756 (diff)
srcclean and fixup (nw)
Diffstat (limited to 'src/devices/cpu/m68000/m68000.h')
-rw-r--r--src/devices/cpu/m68000/m68000.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/devices/cpu/m68000/m68000.h b/src/devices/cpu/m68000/m68000.h
index 2edbfa8bdf8..0596dd07976 100644
--- a/src/devices/cpu/m68000/m68000.h
+++ b/src/devices/cpu/m68000/m68000.h
@@ -292,7 +292,7 @@ protected:
uint16_t m_mmu_tmp_buserror_rw; /* temporary hack: (first) bus error rw */
uint16_t m_mmu_tmp_buserror_sz; /* temporary hack: (first) bus error size` */
- bool m_mmu_tablewalk; /* set when MMU walks page tables */
+ bool m_mmu_tablewalk; /* set when MMU walks page tables */
uint32_t m_mmu_last_logical_addr;
uint32_t m_ic_address[M68K_IC_SIZE]; /* instruction cache address data */
uint32_t m_ic_data[M68K_IC_SIZE]; /* instruction cache content data */