diff options
author | 2017-07-05 11:44:49 +0200 | |
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committer | 2017-11-26 17:41:27 +0100 | |
commit | 6caef2579a1490f05d28bcede731cbdd45fc5c65 (patch) | |
tree | 8055384e183be3cb27e7d0894ac53dc96c09e6fa /src/devices/cpu/lh5801/5801dasm.h | |
parent | 34b222062c89adbeed822f56be6130421777e11f (diff) |
dvdisasm: Overhaul [O. Galibert]
Disassemblers are now independant classes. Not only the code is
cleaner, but unidasm has access to all the cpu cores again. The
interface to the disassembly method has changed from byte buffers to
objects that give a result to read methods. This also adds support
for lfsr and/or paged PCs.
Diffstat (limited to 'src/devices/cpu/lh5801/5801dasm.h')
-rw-r--r-- | src/devices/cpu/lh5801/5801dasm.h | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/src/devices/cpu/lh5801/5801dasm.h b/src/devices/cpu/lh5801/5801dasm.h new file mode 100644 index 00000000000..9a6b66b0c5b --- /dev/null +++ b/src/devices/cpu/lh5801/5801dasm.h @@ -0,0 +1,110 @@ +// license:BSD-3-Clause +// copyright-holders:Peter Trauner +/***************************************************************************** + * + * disasm.c + * portable lh5801 emulator interface + * + * + *****************************************************************************/ + +#ifndef MAME_CPU_LH5801_5801DASM_H +#define MAME_CPU_LH5801_5801DASM_H + +#pragma once + +class lh5801_disassembler : public util::disasm_interface +{ +public: + lh5801_disassembler() = default; + virtual ~lh5801_disassembler() = default; + + virtual u32 opcode_alignment() const override; + virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) override; + +private: + enum Ins + { + ILL, ILL2, PREFD, NOP, + + LDA, STA, LDI, LDX, STX, + LDE, SDE, LIN, SIN, + TIN, // (x++)->(y++) + ADC, ADI, ADR, SBC, SBI, + DCA, DCS, // bcd add and sub + CPA, CPI, CIN, // A compared with (x++) + AND, ANI, ORA, ORI, EOR, EAI, BIT, BII, + INC, DEC, + DRL, DRR, // digit rotates + ROL, ROR, + SHL, SHR, + AEX, // A nibble swap + + BCR, BCS, BHR, BHS, BZR, BZS, BVR, BVS, + BCH, LOP, // loop with ul + JMP, SJP, RTN, RTI, HLT, + VCR, VCS, VHR, VHS, VVS, VZR, VZS, + VMJ, VEJ, + PSH, POP, ATT, TTA, + REC, SEC, RIE, SIE, + + AM0, AM1, // load timer reg + ITA, // reads input port + ATP, // akku send to data bus + CDV, // clears internal divider + OFF, // clears bf flip flop + RDP, SDP,// reset display flip flop + RPU, SPU,// flip flop pu off + RPV, SPV // flip flop pv off + }; + + enum Adr + { + Imp, + Reg, + Vec, // imm byte (vector at 0xffxx) + Vej, + Imm, + RegImm, + Imm16, + RegImm16, + ME0, + ME0Imm, + Abs, + AbsImm, + ME1, + ME1Imm, + ME1Abs, + ME1AbsImm, + RelP, + RelM + }; + + enum Regs + { + RegNone, + A, + XL, XH, X, + YL, YH, Y, + UL, UH, U, + P, S + }; + + struct Entry { + Ins ins; + Adr adr; + Regs reg; + + const char *ins_name() const { return ins_names[ins]; } + const char *reg_name() const { return reg_names[reg]; } + Entry(Ins i, Adr a = Imp, Regs r = RegNone) : ins(i), adr(a), reg(r) { } + }; + + static const char *const ins_names[]; + static const char *const reg_names[]; + + static const Entry table[0x100]; + static const Entry table_fd[0x100]; +}; + +#endif |