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author Olivier Galibert <galibert@pobox.com>2020-05-25 16:42:42 +0200
committer Olivier Galibert <galibert@pobox.com>2020-05-25 16:42:57 +0200
commit22513fb6fe281f5ccb75aaddb6417a12a66c313d (patch)
tree3cf84032cc6482d685a8dbb57e015bd17c7f7fdc /src/devices/cpu/lc8670/lc8670.h
parente42c2d2874cf9c1092c01ab5ce9ef997d465ce25 (diff)
emumem: A little more speedup. cache and specific change syntax, and are not pointers anymore [O. Galibert]
The last(?) two changes are: - Add a template parameter to everything (theoretically the address space width, in practice a level derived from it to keep as much compatibility between widths as possible) so that the shift size becomes a constant. - Change the syntax of declaring and initializing the caches and specifics so that they're embedded in the owner device. Solves lifetime issues and also removes one indirection (looking up the base dispatch pointer through the cache/specific pointer).
Diffstat (limited to 'src/devices/cpu/lc8670/lc8670.h')
-rw-r--r--src/devices/cpu/lc8670/lc8670.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/devices/cpu/lc8670/lc8670.h b/src/devices/cpu/lc8670/lc8670.h
index 8293ed66f26..890472d689f 100644
--- a/src/devices/cpu/lc8670/lc8670.h
+++ b/src/devices/cpu/lc8670/lc8670.h
@@ -189,10 +189,10 @@ private:
address_space_config m_data_config;
address_space_config m_io_config;
- address_space * m_program; // program space (ROM or flash)
- address_space * m_data; // internal RAM/register
- address_space * m_io; // I/O ports
- memory_access_cache<0, 0, ENDIANNESS_BIG> *m_cache;
+ memory_access<16, 0, 0, ENDIANNESS_BIG>::cache m_cache;
+ memory_access<16, 0, 0, ENDIANNESS_BIG>::specific m_program; // program space (ROM or flash)
+ memory_access< 9, 0, 0, ENDIANNESS_BIG>::specific m_data; // internal RAM/register
+ memory_access< 8, 0, 0, ENDIANNESS_BIG>::specific m_io; // I/O ports
// timers
static const device_timer_id BASE_TIMER = 1;