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author yz70s <yz70s@users.noreply.github.com>2019-04-07 18:45:50 +0200
committer yz70s <yz70s@users.noreply.github.com>2019-04-07 23:14:00 +0200
commit03e88d66960cf303d2cbb8704593346ada9f99ea (patch)
treef2f376b618a13a1ff33301334ad3ccd408f7fe63 /src/devices/cpu/i386/i386.h
parent702b45b1bc3ee8690d88914a2cfabab1f0de4bbd (diff)
i386.cpp: athlon xp updates to memory access (nw)
Now athlon xp supports WrMem and RdMem bits in fixed range MTRRs Accesses to the first megabyte can be directed to system memory (ram) or memory-mapped-io (mmio) (the pci bus) Above 1mb accesses below the top_mem MSR address ram the others mmio At reset everyting is directed to mmio Addresss spaces work in the following way AS_PROGRAM is used for ram AS_DATA is used for mmio AS_OPCODES is used by the debugger disassembler and in memory views to look at the memory contents from the point of view of the microprocessor, including the cache Also some class members have been added to the save state
Diffstat (limited to 'src/devices/cpu/i386/i386.h')
-rw-r--r--src/devices/cpu/i386/i386.h15
1 files changed, 14 insertions, 1 deletions
diff --git a/src/devices/cpu/i386/i386.h b/src/devices/cpu/i386/i386.h
index 6fd0dc04266..e3182fcfb81 100644
--- a/src/devices/cpu/i386/i386.h
+++ b/src/devices/cpu/i386/i386.h
@@ -1655,15 +1655,28 @@ protected:
virtual void mem_pwd16(offs_t address, u16 data) override { program_write_cache<u16, NATIVE_ENDIAN_VALUE_LE_BE(0, 2)>(address, data); }
virtual void mem_pwd32(offs_t address, u32 data) override { program_write_cache<u32, 0>(address, data); }
+ // device_memory_interface override
+ virtual space_config_vector memory_space_config() const override;
+
private:
void parse_mtrrfix(u64 mtrr, offs_t base, int kblock);
- int check_cacheable(offs_t address);
+ inline int check_cacheable(offs_t address);
+ template <int wr> int address_mode(offs_t address);
template <class dt, offs_t xorle> dt opcode_read_cache(offs_t address);
template <class dt, offs_t xorle> dt program_read_cache(offs_t address);
template <class dt, offs_t xorle> void program_write_cache(offs_t address, dt data);
+ DECLARE_READ32_MEMBER(debug_read_memory);
+
+ address_space_config m_data_config;
+ address_space *m_data;
+ address_space_config m_opcodes_config;
+ address_space *m_opcodes;
+ memory_access_cache<2, 0, ENDIANNESS_LITTLE> *mmacache32;
uint8_t m_processor_name_string[48];
+ offs_t m_msr_top_mem;
+ uint64_t m_msr_sys_cfg;
uint64_t m_msr_mtrrfix[11];
uint8_t m_memory_ranges_1m[1024 / 4];
cpucache<17, 9, Cache2Way, CacheLineBytes64> cache; // 512 sets, 2 ways (cachelines per set), 64 bytes per cacheline