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author Vas Crabb <vas@vastheman.com>2025-03-20 15:00:40 +1100
committer Vas Crabb <vas@vastheman.com>2025-03-20 15:00:40 +1100
commit3ad89ebbc79370f7885ca41243f52790c1a825a7 (patch)
tree325313d14b7f94c93c165104ec33757ba938e2cc /src/devices/cpu/e132xs
parent3fed48aedd73020b7af86e02d46708570bb5adb6 (diff)
Some relatively simple recompiler optimisations:
cpu/drcbex64.cpp: Avoid a lot of unnecessary flag manipulation on shift/rotate operations. Don't calculate flags when not requested. Don't preserve carry in for operations that don't use it as an input. cpu/drcbex64.cpp: Avoid loading CL when ECX can be used. Loading CL doesn't clear the upper bits, so it depends on the previous value of RCX, causing pipeline dependencies. Loading ECX can grab a fresh rename register. cpu/drcbearm64.cpp: Attempt more optimisation on one more load immediate operation. cpu/e132xs: Get rid of a redundant TEST - ROLAND can set the Z flag.
Diffstat (limited to 'src/devices/cpu/e132xs')
-rw-r--r--src/devices/cpu/e132xs/e132xsdrc_ops.hxx3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/devices/cpu/e132xs/e132xsdrc_ops.hxx b/src/devices/cpu/e132xs/e132xsdrc_ops.hxx
index 6ba9ca26b49..f8fc201828a 100644
--- a/src/devices/cpu/e132xs/e132xsdrc_ops.hxx
+++ b/src/devices/cpu/e132xs/e132xsdrc_ops.hxx
@@ -245,7 +245,6 @@ void hyperstone_device::generate_trap_exception_or_int(drcuml_block &block)
UML_ROLAND(block, I1, DRC_SR, 7, 0x7f);
UML_ROLAND(block, I2, DRC_SR, 11, 0xf);
- UML_TEST(block, I2, 0xf);
UML_MOVc(block, uml::COND_Z, I2, 16);
UML_ADD(block, I3, I1, I2);
@@ -256,7 +255,7 @@ void hyperstone_device::generate_trap_exception_or_int(drcuml_block &block)
UML_ROLINS(block, DRC_SR, I3, 25, 0xfe000000);
UML_AND(block, I1, I3, 0x3f);
- UML_AND(block, I2, DRC_PC, ~1);
+ UML_AND(block, I2, DRC_PC, ~uint32_t(1));
UML_ROLINS(block, I2, DRC_SR, 32-S_SHIFT, 1);
UML_STORE(block, (void *)m_core->local_regs, I1, I2, SIZE_DWORD, SCALE_x4);
UML_ADD(block, I2, I1, 1);