diff options
author | 2022-06-08 19:26:49 +0200 | |
---|---|---|
committer | 2022-06-09 03:26:49 +1000 | |
commit | c046ba26c0322d5fe96f8f8ba675d64bf7039063 (patch) | |
tree | 38b8a709581fd398971522806d753b9f1d820885 /src/devices/cpu/dsp56156 | |
parent | 4fdaa5733afb5fe3ed49fb8d1a454f393d1cdea8 (diff) |
cpu/dps56156, plygonet.cpp: DSP56156 fixes and plygonet.cpp cleanup: (#9894) [Ryan Holtz]
* cpu/dsp56156: Fixed ANDI, fixed BFCLR errata, fixed DEC24 not affecting flags.
* cpu/dsp56156: Added proper devcb_write16 for Port C output.
* plygonet.cpp: Fixed banking and tightened up VRAM access.
* plygonet.cpp: Account for endianness in tilemap accesses.
* plygonet.cpp: Switched to logmacro, merged into one file, and general code cleanup.
Diffstat (limited to 'src/devices/cpu/dsp56156')
-rw-r--r-- | src/devices/cpu/dsp56156/dsp56156.cpp | 4 | ||||
-rw-r--r-- | src/devices/cpu/dsp56156/dsp56156.h | 21 | ||||
-rw-r--r-- | src/devices/cpu/dsp56156/dsp56mem.cpp | 19 | ||||
-rw-r--r-- | src/devices/cpu/dsp56156/dsp56ops.hxx | 24 |
4 files changed, 40 insertions, 28 deletions
diff --git a/src/devices/cpu/dsp56156/dsp56156.cpp b/src/devices/cpu/dsp56156/dsp56156.cpp index 1b93948adf5..f8685d080ae 100644 --- a/src/devices/cpu/dsp56156/dsp56156.cpp +++ b/src/devices/cpu/dsp56156/dsp56156.cpp @@ -127,6 +127,7 @@ dsp56156_device::dsp56156_device(const machine_config &mconfig, const char *tag, , m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56156_device::dsp56156_program_map), this)) , m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56156_device::dsp56156_x_data_map), this)) , m_program_ram(*this, "dsk56156_program_ram") + , portC_cb(*this) { } @@ -268,6 +269,9 @@ void dsp56156_device::device_start() m_core.modC_state = false; m_core.reset_state = false; + /* Resolve line callbacks */ + portC_cb.resolve_safe(); + /* save states - dsp56156_core members */ save_item(NAME(m_core.modA_state)); save_item(NAME(m_core.modB_state)); diff --git a/src/devices/cpu/dsp56156/dsp56156.h b/src/devices/cpu/dsp56156/dsp56156.h index cc8ebe6741d..4778dd20438 100644 --- a/src/devices/cpu/dsp56156/dsp56156.h +++ b/src/devices/cpu/dsp56156/dsp56156.h @@ -23,9 +23,10 @@ #define DSP56156_IRQ_MODC 2 #define DSP56156_IRQ_RESET 3 /* Is this needed? */ - namespace DSP_56156 { +class dsp56156_device; + /*************************************************************************** STRUCTURES & TYPEDEFS ***************************************************************************/ @@ -182,15 +183,14 @@ struct dsp56156_core uint8_t repFlag; // Knowing if we're in a 'repeat' state (dunno how the processor does this) uint32_t repAddr; // The address of the instruction to repeat... - - /* MAME internal stuff */ + // MAME internal stuff int icount; uint32_t ppc; uint32_t op; - int interrupt_cycles; - void (*output_pins_changed)(uint32_t pins); - cpu_device *device; + int interrupt_cycles; + void (*output_pins_changed)(uint32_t pins); + dsp56156_device *device; memory_access<16, 1, -1, ENDIANNESS_LITTLE>::cache cache; memory_access<16, 1, -1, ENDIANNESS_LITTLE>::specific program; memory_access<16, 1, -1, ENDIANNESS_LITTLE>::specific data; @@ -211,10 +211,13 @@ public: void host_interface_write(uint8_t offset, uint8_t data); uint8_t host_interface_read(uint8_t offset); - uint16_t get_peripheral_memory(uint16_t addr); - void dsp56156_program_map(address_map &map); void dsp56156_x_data_map(address_map &map); + + auto portc_cb() { return portC_cb.bind(); } + + void output_portc(uint16_t value) { portC_cb(value); } + protected: // device-level overrides virtual void device_start() override; @@ -246,6 +249,8 @@ private: dsp56156_core m_core; + devcb_write16 portC_cb; + void agu_init(); void alu_init(); }; diff --git a/src/devices/cpu/dsp56156/dsp56mem.cpp b/src/devices/cpu/dsp56156/dsp56mem.cpp index 9f61089b9b4..4e53799e75a 100644 --- a/src/devices/cpu/dsp56156/dsp56mem.cpp +++ b/src/devices/cpu/dsp56156/dsp56mem.cpp @@ -47,6 +47,7 @@ void mem_reset(dsp56156_core* cpustate) /************************************/ void HCR_set(dsp56156_core* cpustate, uint16_t value) { + cpustate->device->logerror("HCR_set: %02x\n", value); HF3_bit_set (cpustate, (value & 0x0010) >> 4); HF2_bit_set (cpustate, (value & 0x0008) >> 3); HCIE_bit_set(cpustate, (value & 0x0004) >> 2); @@ -65,6 +66,7 @@ void HF3_bit_set(dsp56156_core* cpustate, uint16_t value) HCR &= ~(0x0010); HCR |= (value << 4); + cpustate->device->logerror("HF3_bit_set: %d\n", value); HF3_bit_host_set(cpustate, value); } void HF2_bit_set(dsp56156_core* cpustate, uint16_t value) @@ -73,6 +75,7 @@ void HF2_bit_set(dsp56156_core* cpustate, uint16_t value) HCR &= ~(0x0008); HCR |= (value << 3); + cpustate->device->logerror("HF2_bit_set: %d\n", value); HF2_bit_host_set(cpustate, value); } void HCIE_bit_set(dsp56156_core* cpustate, uint16_t value) @@ -468,12 +471,11 @@ void PCD_set(dsp56156_core* cpustate, uint16_t value) if (value & 0xf000) cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PCD. Ignoring.\n"); - /* TODO: Temporary */ - cpustate->device->logerror("Dsp56k : Setting general output port C data to 0x%04x\n", value); - value = value & 0x0fff; PCD &= ~(0x0fff); PCD |= (value << 0); + + cpustate->device->output_portc(PCD); } void dsp56156_io_reset(dsp56156_core* cpustate) @@ -888,18 +890,22 @@ uint8_t dsp56156_device::host_interface_read(uint8_t offset) { // Interrupt Control Register (ICR) case 0x00: + logerror("DSP: Returning ICR\n"); return ICR; // Command Vector Register (CVR) case 0x01: + logerror("DSP: Returning CVR\n"); return CVR; // Interrupt status register (ISR) case 0x02: + logerror("DSP: Returning ISR\n"); return ISR; // Interrupt vector register (IVR) case 0x03: + logerror("DSP: Returning IVR\n"); return IVR; // Read zeroes @@ -938,12 +944,5 @@ uint8_t dsp56156_device::host_interface_read(uint8_t offset) return 0xff; } -/* MISC*/ -uint16_t dsp56156_device::get_peripheral_memory(uint16_t addr) -{ - dsp56156_core* cpustate = &m_core; - return cpustate->peripheral_ram[A2O(addr)]; -} - } // namespace DSP_56156 diff --git a/src/devices/cpu/dsp56156/dsp56ops.hxx b/src/devices/cpu/dsp56156/dsp56ops.hxx index d6b2b82f97d..f61afaf7703 100644 --- a/src/devices/cpu/dsp56156/dsp56ops.hxx +++ b/src/devices/cpu/dsp56156/dsp56ops.hxx @@ -21,7 +21,6 @@ TODO: - 0x01ee: should this move sign extend? otherwise the test-against-minus means nothing. - Restore only the proper bits upon loop termination! - - BFCLR has some errata in the docs that may need to be applied. */ /************************/ @@ -1818,6 +1817,7 @@ static size_t dsp56156_op_dec24(dsp56156_core* cpustate, const uint16_t op_byte, /* TODO: I wonder if workBits24 should be signed? */ workBits24 = ((*((uint64_t*)D.addr)) & 0x000000ffffff0000U) >> 16; workBits24--; + bool carry(workBits24 & 0x01000000); workBits24 &= 0x00ffffff; /* Solves -x issues */ /* Set the D bits with the dec result */ @@ -1829,9 +1829,10 @@ static size_t dsp56156_op_dec24(dsp56156_core* cpustate, const uint16_t op_byte, /* S L E U N Z V C */ /* * * * * * ? * * */ - /* TODO: S, L, E, U, V, C */ + /* TODO: S, L, E, U, V */ if ( *((uint64_t*)D.addr) & 0x0000008000000000U) DSP56156_N_SET(); else DSP56156_N_CLEAR(); if ((*((uint64_t*)D.addr) & 0x000000ffffff0000U) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR(); + if (carry) DSP56156_C_SET(); else DSP56156_C_CLEAR(); cycles += 2; /* TODO: + mv oscillator clock cycles */ return 1; @@ -2185,12 +2186,12 @@ static size_t dsp56156_op_andi(dsp56156_core* cpustate, const uint16_t op, uint8 SR &= ((immediate << 8) | 0x00ff); break; - case 0x02: /* CCR */ - SR &= (immediate | 0xff00); + case 0x02: /* OMR */ + OMR &= (uint8_t)(immediate); break; - case 0x03: /* OMR */ - OMR &= (uint8_t)(immediate); + case 0x03: /* CCR */ + SR &= (immediate | 0xff00); break; default: @@ -2342,7 +2343,7 @@ static size_t dsp56156_op_bfop(dsp56156_core* cpustate, const uint16_t op, const case 0x12: /* BFCHG */ if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x04: /* BFCLR */ - if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; + if ((iVal & previousValue) == 0x0000) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x18: /* BFSET */ if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x10: /* BFTSTH */ @@ -2408,7 +2409,7 @@ static size_t dsp56156_op_bfop_1(dsp56156_core* cpustate, const uint16_t op, con case 0x12: /* BFCHG */ if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x04: /* BFCLR */ - if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; + if ((iVal & previousValue) == 0x0000) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x18: /* BFSET */ if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x10: /* BFTSTH */ @@ -2478,7 +2479,7 @@ static size_t dsp56156_op_bfop_2(dsp56156_core* cpustate, const uint16_t op, con case 0x12: /* BFCHG */ if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x04: /* BFCLR */ - if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; + if ((iVal & previousValue) == 0x0000) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x18: /* BFSET */ if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break; case 0x10: /* BFTSTH */ @@ -2855,7 +2856,8 @@ static size_t dsp56156_op_do_2(dsp56156_core* cpustate, const uint16_t op, const /* HACK */ if (lValue >= 0xfff0) { - cpustate->device->logerror("Dsp56156 : DO_2 operation changed %04x to 0000.\n", lValue); + cpustate->device->logerror("Dsp56156 : DO_2 operation changed %04x to 0000, pc:%04x ppc:%04x.\n", lValue, cpustate->PCU.pc, cpustate->ppc); + cpustate->device->machine().debug_break(); lValue = 0x0000; } @@ -2887,6 +2889,8 @@ static size_t dsp56156_op_do_2(dsp56156_core* cpustate, const uint16_t op, const /* Third instruction cycle */ LF_bit_set(cpustate, 1); + /* Undocumented, but it must be true to nest Dos in DoForevers */ + FV_bit_set(cpustate, 0); /* S L E U N Z V C */ /* - * - - - - - - */ |