diff options
author | 2020-01-29 09:13:48 -0600 | |
---|---|---|
committer | 2020-01-29 10:13:48 -0500 | |
commit | e6595b06a7781e5e9e3bc8a7957d4fa0ae50682c (patch) | |
tree | 85ff6b64d8173bf1d016d47035603b4bd38cecad /src/devices/cpu/arm7 | |
parent | a5783544e8026ebbca60e1ec0490ae4a075b9263 (diff) |
iphone2g wip (nw) (#6226)
* iphone2g wip (nw)
* fixup
* fixup
* fixup
* iphone2g: hacky spi and non-existent timers (nw)
Diffstat (limited to 'src/devices/cpu/arm7')
-rw-r--r-- | src/devices/cpu/arm7/arm7.cpp | 48 | ||||
-rw-r--r-- | src/devices/cpu/arm7/arm7.h | 8 | ||||
-rw-r--r-- | src/devices/cpu/arm7/arm7core.h | 2 |
3 files changed, 54 insertions, 4 deletions
diff --git a/src/devices/cpu/arm7/arm7.cpp b/src/devices/cpu/arm7/arm7.cpp index 76eefbb44d3..0637c42ddc4 100644 --- a/src/devices/cpu/arm7/arm7.cpp +++ b/src/devices/cpu/arm7/arm7.cpp @@ -42,7 +42,7 @@ TODO: #define LOG_COPRO_UNKNOWN (1 << 4) #define LOG_COPRO_RESERVED (1 << 5) -#define VERBOSE (0) +#define VERBOSE (0) //(LOG_MMU | LOG_COPRO_READS | LOG_COPRO_WRITES) #include "logmacro.h" #define PRINT_HAPYFSH2 (0) @@ -726,7 +726,6 @@ void arm946es_cpu_device::device_start() save_item(NAME(DTCM)); } - void arm7_cpu_device::state_export(const device_state_entry &entry) { switch (entry.index()) @@ -787,6 +786,11 @@ void arm7_cpu_device::device_reset() m_impstate.cache_dirty = true; } +void arm1176jzf_s_cpu_device::device_reset() +{ + arm7_cpu_device::device_reset(); + m_control = 0x00050078; +} #define UNEXECUTED() \ m_r[eR15] += 4; \ @@ -1413,7 +1417,7 @@ WRITE32_MEMBER( arm7_cpu_device::arm7_rt_w_callback ) #if ARM7_MMU_ENABLE_HACK if (((data & COPRO_CTRL_MMU_EN) != 0) && ((COPRO_CTRL & COPRO_CTRL_MMU_EN) == 0)) { - >m_mmu_enable_addr = R15; + m_mmu_enable_addr = R15; } if (((data & COPRO_CTRL_MMU_EN) == 0) && ((COPRO_CTRL & COPRO_CTRL_MMU_EN) != 0)) { @@ -1778,6 +1782,44 @@ void arm7_cpu_device::arm7_dt_w_callback(uint32_t insn, uint32_t *prn) } } +READ32_MEMBER( arm1176jzf_s_cpu_device::arm7_rt_r_callback ) +{ + uint32_t opcode = offset; + uint8_t crn = (opcode & INSN_COPRO_CREG) >> INSN_COPRO_CREG_SHIFT; + uint8_t op1 = (opcode & INSN_COPRO_OP1) >> INSN_COPRO_OP1_SHIFT; + uint8_t op2 = (opcode & INSN_COPRO_OP2) >> INSN_COPRO_OP2_SHIFT; + uint8_t crm = opcode & INSN_COPRO_OP3; + uint8_t cpnum = (opcode & INSN_COPRO_CPNUM) >> INSN_COPRO_CPNUM_SHIFT; + uint32_t data = 0; + +// printf("arm7946: copro %d write %x to cReg %d op2 %d op3 %d (mask %08x)\n", cpnum, data, cReg, op2, op3, mem_mask); + + if (cpnum == 15) + { + if(crn == 0 && op1 == 0 && crm == 0 && op2 == 0) data = 0x410FB767; //ARM1176JZF-S Main ID. + if(crn == 1 && op1 == 0 && crm == 0 && op2 == 0) data = m_control; + } + + return data; +} + +WRITE32_MEMBER( arm1176jzf_s_cpu_device::arm7_rt_w_callback ) +{ + uint32_t opcode = offset; + uint8_t crn = (opcode & INSN_COPRO_CREG) >> INSN_COPRO_CREG_SHIFT; + uint8_t op1 = (opcode & INSN_COPRO_OP1) >> INSN_COPRO_OP1_SHIFT; + uint8_t op2 = (opcode & INSN_COPRO_OP2) >> INSN_COPRO_OP2_SHIFT; + uint8_t crm = opcode & INSN_COPRO_OP3; + uint8_t cpnum = (opcode & INSN_COPRO_CPNUM) >> INSN_COPRO_CPNUM_SHIFT; + +// printf("arm7946: copro %d write %x to cReg %d op2 %d op3 %d (mask %08x)\n", cpnum, data, cReg, op2, op3, mem_mask); + + if (cpnum == 15) + { + LOGMASKED(LOG_COPRO_WRITES, "arm7_rt_w_callback: CP15 CRn %02x Op1 %02x CRm %02x Op2 %02x data %08x\n", crn, op1, crm, op2, data); + if(crn == 1 && op1 == 0 && crm == 0 && op2 == 0) m_control = data; + } +} /*************************************************************************** * Default Memory Handlers diff --git a/src/devices/cpu/arm7/arm7.h b/src/devices/cpu/arm7/arm7.h index 938950cc9d8..5a7ca665b6f 100644 --- a/src/devices/cpu/arm7/arm7.h +++ b/src/devices/cpu/arm7/arm7.h @@ -179,7 +179,7 @@ protected: uint32_t m_domainAccessControl; uint8_t m_decoded_access_control[16]; - uint8_t m_archRev; // ARM architecture revision (3, 4, and 5 are valid) + uint8_t m_archRev; // ARM architecture revision (3, 4, 5, and 6 are valid) uint32_t m_archFlags; // architecture flags uint32_t m_vectorbase; @@ -674,6 +674,12 @@ class arm1176jzf_s_cpu_device : public arm11_cpu_device public: // construction/destruction arm1176jzf_s_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + virtual DECLARE_READ32_MEMBER( arm7_rt_r_callback ) override; + virtual DECLARE_WRITE32_MEMBER( arm7_rt_w_callback ) override; + +protected: + virtual void device_reset() override; }; class igs036_cpu_device : public arm946es_cpu_device diff --git a/src/devices/cpu/arm7/arm7core.h b/src/devices/cpu/arm7/arm7core.h index a6a7838bed4..320638ce626 100644 --- a/src/devices/cpu/arm7/arm7core.h +++ b/src/devices/cpu/arm7/arm7core.h @@ -356,12 +356,14 @@ static const int sRegisterTable[ARM7_NUM_MODES][18] = #define INSN_RD_SHIFT 12 #define INSN_COND_SHIFT 28 +#define INSN_COPRO_OP1 ((uint32_t) 0x00e00000u) #define INSN_COPRO_N ((uint32_t) 0x00100000u) #define INSN_COPRO_CREG ((uint32_t) 0x000f0000u) #define INSN_COPRO_AREG ((uint32_t) 0x0000f000u) #define INSN_COPRO_CPNUM ((uint32_t) 0x00000f00u) #define INSN_COPRO_OP2 ((uint32_t) 0x000000e0u) #define INSN_COPRO_OP3 ((uint32_t) 0x0000000fu) +#define INSN_COPRO_OP1_SHIFT 21 #define INSN_COPRO_N_SHIFT 20 #define INSN_COPRO_CREG_SHIFT 16 #define INSN_COPRO_AREG_SHIFT 12 |