diff options
author | 2017-12-13 21:01:10 -0700 | |
---|---|---|
committer | 2017-12-13 21:01:10 -0700 | |
commit | 54155441e9ba9941e85d80c4834a66376a11e791 (patch) | |
tree | aa44bdaf0035cbe188d64c447f225f10f7d76d8d /src/devices/cpu/arm7/arm7core.h | |
parent | f537428e5a40ba6dde8ca9bf0fe9ae6b1f189ac4 (diff) |
Revert "Merge branch 'master' of https://github.com/mamedev/mame"
This reverts commit f537428e5a40ba6dde8ca9bf0fe9ae6b1f189ac4, reversing
changes made to 0d70d798107d4e4e8fb9f230410aeb1e888d65c5.
Diffstat (limited to 'src/devices/cpu/arm7/arm7core.h')
-rw-r--r-- | src/devices/cpu/arm7/arm7core.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/devices/cpu/arm7/arm7core.h b/src/devices/cpu/arm7/arm7core.h index c33bdee9dd2..9ae499ae109 100644 --- a/src/devices/cpu/arm7/arm7core.h +++ b/src/devices/cpu/arm7/arm7core.h @@ -470,6 +470,11 @@ enum COND_NV /* 0 never */ }; +#define LSL(v, s) ((v) << (s)) +#define LSR(v, s) ((v) >> (s)) +#define ROL(v, s) (LSL((v), (s)) | (LSR((v), 32u - (s)))) +#define ROR(v, s) (LSR((v), (s)) | (LSL((v), 32u - (s)))) + /* Convenience Macros */ #define R15 m_r[eR15] #define SPSR 17 // SPSR is always the 18th register in our 0 based array sRegisterTable[][18] |