diff options
author | 2017-07-05 11:44:49 +0200 | |
---|---|---|
committer | 2017-11-26 17:41:27 +0100 | |
commit | 6caef2579a1490f05d28bcede731cbdd45fc5c65 (patch) | |
tree | 8055384e183be3cb27e7d0894ac53dc96c09e6fa /src/devices/cpu/apexc | |
parent | 34b222062c89adbeed822f56be6130421777e11f (diff) |
dvdisasm: Overhaul [O. Galibert]
Disassemblers are now independant classes. Not only the code is
cleaner, but unidasm has access to all the cpu cores again. The
interface to the disassembly method has changed from byte buffers to
objects that give a result to read methods. This also adds support
for lfsr and/or paged PCs.
Diffstat (limited to 'src/devices/cpu/apexc')
-rw-r--r-- | src/devices/cpu/apexc/apexc.cpp | 7 | ||||
-rw-r--r-- | src/devices/cpu/apexc/apexc.h | 4 | ||||
-rw-r--r-- | src/devices/cpu/apexc/apexcdsm.cpp | 22 | ||||
-rw-r--r-- | src/devices/cpu/apexc/apexcdsm.h | 37 |
4 files changed, 50 insertions, 20 deletions
diff --git a/src/devices/cpu/apexc/apexc.cpp b/src/devices/cpu/apexc/apexc.cpp index e26c6c094b4..4278d5b2d48 100644 --- a/src/devices/cpu/apexc/apexc.cpp +++ b/src/devices/cpu/apexc/apexc.cpp @@ -327,6 +327,7 @@ field: X address D Function Y address D (part 2) #include "emu.h" #include "apexc.h" +#include "apexcdsm.h" #include "debugger.h" @@ -854,9 +855,7 @@ void apexc_cpu_device::execute_run() } while (m_icount > 0); } - -offs_t apexc_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) +util::disasm_interface *apexc_cpu_device::create_disassembler() { - extern CPU_DISASSEMBLE( apexc ); - return CPU_DISASSEMBLE_NAME(apexc)(this, stream, pc, oprom, opram, options); + return new apexc_disassembler; } diff --git a/src/devices/cpu/apexc/apexc.h b/src/devices/cpu/apexc/apexc.h index 76a91a98207..92cc60d7f09 100644 --- a/src/devices/cpu/apexc/apexc.h +++ b/src/devices/cpu/apexc/apexc.h @@ -40,9 +40,7 @@ protected: virtual void state_import(const device_state_entry &entry) override; // device_disasm_interface overrides - virtual uint32_t disasm_min_opcode_bytes() const override { return 4; } - virtual uint32_t disasm_max_opcode_bytes() const override { return 4; } - virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override; + virtual util::disasm_interface *create_disassembler() override; inline uint32_t apexc_readmem(uint32_t address) { return m_program->read_dword((address)<<2); } inline void apexc_writemem(uint32_t address, uint32_t data) { m_program->write_dword((address)<<2, (data)); } diff --git a/src/devices/cpu/apexc/apexcdsm.cpp b/src/devices/cpu/apexc/apexcdsm.cpp index e3626a40af9..bb581dd2850 100644 --- a/src/devices/cpu/apexc/apexcdsm.cpp +++ b/src/devices/cpu/apexc/apexcdsm.cpp @@ -10,9 +10,7 @@ #include "emu.h" -#include "debugger.h" - -#include "apexc.h" +#include "apexcdsm.h" /* Here is the format used for debugger output. @@ -63,15 +61,8 @@ The X value shows where the data word is located, and the Y value is the address of the next instruction. */ -enum format_type {branch, shiftl, shiftr, multiply, store, swap, one_address, two_address}; - -struct instr_desc -{ - const char *mnemonic; - format_type format; /* -> X and Y are format */ -}; -static const instr_desc instructions[16] = +const apexc_disassembler::instr_desc apexc_disassembler::instructions[16] = { { "Stop", one_address }, { "I", one_address }, { "P", one_address }, { "B", branch }, @@ -83,7 +74,12 @@ static const instr_desc instructions[16] = { "A", store }, { "S", swap } }; -CPU_DISASSEMBLE(apexc) +u32 apexc_disassembler::opcode_alignment() const +{ + return 4; +} + +offs_t apexc_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) { uint32_t instruction; /* 32-bit machine instruction */ int x, y, function, c6, vector; /* instruction fields */ @@ -92,7 +88,7 @@ CPU_DISASSEMBLE(apexc) char mnemonic[9]; /* storage for generated mnemonic */ /* read the instruction to disassemble */ - instruction = oprom[0] << 24 | oprom[1] << 16 | oprom[2] << 8 | oprom[3]; + instruction = opcodes.r32(pc); /* isolate the instruction fields */ x = (instruction >> 22) & 0x3FF; diff --git a/src/devices/cpu/apexc/apexcdsm.h b/src/devices/cpu/apexc/apexcdsm.h new file mode 100644 index 00000000000..b310df1f496 --- /dev/null +++ b/src/devices/cpu/apexc/apexcdsm.h @@ -0,0 +1,37 @@ +// license:BSD-3-Clause +// copyright-holders:Raphael Nabet +/* + cpu/apexc/apexcsm.c : APE(X)C CPU disassembler + + By Raphael Nabet + + see cpu/apexc.c for background and tech info +*/ + +#ifndef MAME_CPU_APEXC_APEXCDSM_H +#define MAME_CPU_APEXC_APEXCDSM_H + +#pragma once + +class apexc_disassembler : public util::disasm_interface +{ +public: + apexc_disassembler() = default; + virtual ~apexc_disassembler() = default; + + virtual u32 opcode_alignment() const override; + virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) override; + +private: + enum format_type {branch, shiftl, shiftr, multiply, store, swap, one_address, two_address}; + + struct instr_desc + { + const char *mnemonic; + format_type format; /* -> X and Y are format */ + }; + + static const instr_desc instructions[16]; +}; + +#endif |