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author Scott Stone <tafoid@gmail.com>2016-11-24 09:24:01 -0500
committer Scott Stone <tafoid@gmail.com>2016-11-24 09:24:01 -0500
commit30cda1d3e5b9195fbd1f23a3af4480666c750a34 (patch)
tree82f7b4b6bb3c61335c495d0925b393b212f6f3f0 /src/devices/cpu/apexc
parent7746690ddf1b6b806de046ec54fee954f09e182e (diff)
A round of spelling/typographical fixes to source comments (nw)
Diffstat (limited to 'src/devices/cpu/apexc')
-rw-r--r--src/devices/cpu/apexc/apexc.cpp8
-rw-r--r--src/devices/cpu/apexc/apexc.h2
2 files changed, 5 insertions, 5 deletions
diff --git a/src/devices/cpu/apexc/apexc.cpp b/src/devices/cpu/apexc/apexc.cpp
index cf132550263..c15f1210002 100644
--- a/src/devices/cpu/apexc/apexc.cpp
+++ b/src/devices/cpu/apexc/apexc.cpp
@@ -225,9 +225,9 @@ field: X address D Function Y address D (part 2)
n last bits of a word, leaving other bits in memory unaffected.
The LSBits are transferred first, since this enables to perform bit-per-bit add and
- substract. Otherwise, the CPU would need an additionnal register to store the second
+ substract. Otherwise, the CPU would need an additional register to store the second
operand, and it would be probably slower, since the operation could only
- take place after all the data has been transfered.
+ take place after all the data has been transferred.
Memory operations are synchronous with 2 clocks found on the memory controller:
* word clock: a pulse on each word boundary (3750rpm*32 -> 2kHz)
@@ -294,7 +294,7 @@ field: X address D Function Y address D (part 2)
although it appears that this delay is not applied when X is not read (cf cross-track
B in Booth p. 49).
However, and here comes the wacky part, analysis of Booth p. 55 shows that
- no additionnal delay is caused by an X instruction having its X operand
+ no additional delay is caused by an X instruction having its X operand
on another track. Maybe, just maybe, this is related to the fact that X does not
need to take the word count into account, any word in track is as good as any (yet,
this leaves the question of why this optimization could not be applied to vector
@@ -450,7 +450,7 @@ uint32_t apexc_cpu_device::load_ml(uint32_t address, uint32_t vector)
{
int delay;
- /* additionnal delay appears if we switch tracks */
+ /* additional delay appears if we switch tracks */
if (((m_ml & 0x3E0) != (address & 0x3E0)) /*|| vector*/)
delay = 6; /* if tracks are different, delay to allow for track switching */
else
diff --git a/src/devices/cpu/apexc/apexc.h b/src/devices/cpu/apexc/apexc.h
index 28aba6a5b52..dfb9bb5d58d 100644
--- a/src/devices/cpu/apexc/apexc.h
+++ b/src/devices/cpu/apexc/apexc.h
@@ -9,7 +9,7 @@
enum
{
APEXC_CR =1, /* control register */
- APEXC_A, /* acumulator */
+ APEXC_A, /* accumulator */
APEXC_R, /* register */
APEXC_ML, /* memory location */
APEXC_WS, /* working store */