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author hap <happppp@users.noreply.github.com>2020-08-01 19:02:26 +0200
committer hap <happppp@users.noreply.github.com>2020-08-01 19:02:40 +0200
commit18f2dd9ac1cda2fcae6203a24ee1568189b68a64 (patch)
tree784583a5dcd72ea3384218eceaefdcb13316ec36 /src/devices/bus
parent206767bf56870f62996e4e238744310ff5d64f33 (diff)
Software list items promoted to working
--------------------------------------- odyssey2: Chess Module (Euro) [hap]
Diffstat (limited to 'src/devices/bus')
-rw-r--r--src/devices/bus/odyssey2/chess.cpp65
-rw-r--r--src/devices/bus/odyssey2/chess.h26
-rw-r--r--src/devices/bus/odyssey2/slot.cpp12
-rw-r--r--src/devices/bus/odyssey2/slot.h6
-rw-r--r--src/devices/bus/odyssey2/voice.cpp11
5 files changed, 100 insertions, 20 deletions
diff --git a/src/devices/bus/odyssey2/chess.cpp b/src/devices/bus/odyssey2/chess.cpp
index e8226a4d3be..f1a871f1000 100644
--- a/src/devices/bus/odyssey2/chess.cpp
+++ b/src/devices/bus/odyssey2/chess.cpp
@@ -1,5 +1,5 @@
// license:BSD-3-Clause
-// copyright-holders:Fabio Priuli
+// copyright-holders:hap
/******************************************************************************
Videopac C7010 Chess Module emulation
@@ -11,10 +11,6 @@ Hardware notes:
Service manual with schematics is available.
-TODO:
-- this code is just a stub... hence, almost everything is still to do!
- most importantly, missing 8KB ROM dump
-
******************************************************************************/
#include "emu.h"
@@ -28,22 +24,38 @@ TODO:
DEFINE_DEVICE_TYPE(O2_ROM_CHESS, o2_chess_device, "o2_chess", "Odyssey 2 Videopac Chess Module")
-o2_chess_device::o2_chess_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : o2_rom_device(mconfig, O2_ROM_CHESS, tag, owner, clock)
- , m_cpu(*this, "subcpu")
+o2_chess_device::o2_chess_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+ o2_rom_device(mconfig, O2_ROM_CHESS, tag, owner, clock),
+ m_cpu(*this, "subcpu"),
+ m_latch(*this, "latch%u", 0)
+{ }
+
+void o2_chess_device::device_start()
+{
+ save_item(NAME(m_control));
+}
+
+void o2_chess_device::cart_init()
{
+ if (m_rom_size != 0x2800)
+ fatalerror("o2_chess_device: Wrong ROM region size\n");
}
+//-------------------------------------------------
+// address maps
+//-------------------------------------------------
+
void o2_chess_device::chess_mem(address_map &map)
{
- map(0x0000, 0x07ff).r(FUNC(o2_chess_device::read_rom04));
+ map(0x0000, 0x1fff).r(FUNC(o2_chess_device::internal_rom_r));
+ map(0xe000, 0xe7ff).mirror(0x1800).ram();
}
void o2_chess_device::chess_io(address_map &map)
{
- map.unmap_value_high();
- map.global_mask(0xff);
+ map.global_mask(0x01);
+ map(0x00, 0x01).r(m_latch[1], FUNC(generic_latch_8_device::read)).w(m_latch[0], FUNC(generic_latch_8_device::write));
}
@@ -56,4 +68,35 @@ void o2_chess_device::device_add_mconfig(machine_config &config)
NSC800(config, m_cpu, 4.433619_MHz_XTAL);
m_cpu->set_addrmap(AS_PROGRAM, &o2_chess_device::chess_mem);
m_cpu->set_addrmap(AS_IO, &o2_chess_device::chess_io);
+
+ GENERIC_LATCH_8(config, m_latch[0]);
+ GENERIC_LATCH_8(config, m_latch[1]);
+}
+
+
+//-------------------------------------------------
+// mapper specific handlers
+//-------------------------------------------------
+
+void o2_chess_device::write_bank(int bank)
+{
+ // P10: must be low to access latches
+ // P11: reset
+ m_cpu->set_input_line(INPUT_LINE_RESET, (bank & 2) ? CLEAR_LINE : ASSERT_LINE);
+
+ m_control = bank;
+}
+
+u8 o2_chess_device::io_read(offs_t offset)
+{
+ if (offset & 0x80 && offset & 0x20 && ~m_control & 1)
+ return m_latch[0]->read();
+ else
+ return 0xff;
+}
+
+void o2_chess_device::io_write(offs_t offset, u8 data)
+{
+ if (offset & 0x80 && ~m_control & 1)
+ m_latch[1]->write(data);
}
diff --git a/src/devices/bus/odyssey2/chess.h b/src/devices/bus/odyssey2/chess.h
index da8bee54b9d..d1f6ecbfc9f 100644
--- a/src/devices/bus/odyssey2/chess.h
+++ b/src/devices/bus/odyssey2/chess.h
@@ -1,5 +1,11 @@
// license:BSD-3-Clause
-// copyright-holders:Fabio Priuli
+// copyright-holders:hap
+/**********************************************************************
+
+ Videopac C7010 Chess Module emulation
+
+**********************************************************************/
+
#ifndef MAME_BUS_ODYSSEY2_CHESS_H
#define MAME_BUS_ODYSSEY2_CHESS_H
@@ -8,6 +14,7 @@
#include "slot.h"
#include "rom.h"
#include "cpu/z80/z80.h"
+#include "machine/gen_latch.h"
// ======================> o2_chess_device
@@ -19,14 +26,29 @@ public:
o2_chess_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
+ // device-level overrides
+ virtual void device_start() override;
virtual void device_add_mconfig(machine_config &config) override;
-// virtual const rom_entry *device_rom_region() const;
+
+ virtual void cart_init() override;
+
+ virtual u8 read_rom04(offs_t offset) override { return m_rom[offset + 0x2000]; }
+ virtual u8 read_rom0c(offs_t offset) override { return m_rom[offset + 0x2000]; }
+
+ virtual void write_bank(int bank) override;
+ virtual void io_write(offs_t offset, u8 data) override;
+ virtual u8 io_read(offs_t offset) override;
private:
required_device<nsc800_device> m_cpu;
+ required_device_array<generic_latch_8_device, 2> m_latch;
+
+ u8 internal_rom_r(offs_t offset) { return m_rom[offset]; }
void chess_io(address_map &map);
void chess_mem(address_map &map);
+
+ u8 m_control = 0;
};
// device type definition
diff --git a/src/devices/bus/odyssey2/slot.cpp b/src/devices/bus/odyssey2/slot.cpp
index 3b743b6964b..b5a2f71be67 100644
--- a/src/devices/bus/odyssey2/slot.cpp
+++ b/src/devices/bus/odyssey2/slot.cpp
@@ -174,7 +174,7 @@ image_init_result o2_cart_slot_device::call_load()
m_type = o2_get_pcb_id(pcb_name);
}
- //printf("Type: %s\n", o2_get_slot(m_type));
+ m_cart->cart_init();
return image_init_result::PASS;
}
@@ -231,7 +231,7 @@ uint8_t o2_cart_slot_device::read_rom0c(offs_t offset)
}
/*-------------------------------------------------
- io_write
+ io
-------------------------------------------------*/
void o2_cart_slot_device::io_write(offs_t offset, uint8_t data)
@@ -240,6 +240,14 @@ void o2_cart_slot_device::io_write(offs_t offset, uint8_t data)
m_cart->io_write(offset, data);
}
+uint8_t o2_cart_slot_device::io_read(offs_t offset)
+{
+ if (m_cart)
+ return m_cart->io_read(offset);
+ else
+ return 0xff;
+}
+
#include "bus/odyssey2/rom.h"
#include "bus/odyssey2/chess.h"
diff --git a/src/devices/bus/odyssey2/slot.h b/src/devices/bus/odyssey2/slot.h
index 69e107edc11..cec7e2b8eb5 100644
--- a/src/devices/bus/odyssey2/slot.h
+++ b/src/devices/bus/odyssey2/slot.h
@@ -38,8 +38,11 @@ public:
virtual void write_bank(int bank) { }
virtual void io_write(offs_t offset, uint8_t data) { }
+ virtual uint8_t io_read(offs_t offset) { return 0xff; }
virtual DECLARE_READ_LINE_MEMBER(t0_read) { return 0; }
+ virtual void cart_init() { } // called after loading ROM
+
void rom_alloc(uint32_t size, const char *tag);
void ram_alloc(uint32_t size);
uint8_t* get_rom_base() { return m_rom; }
@@ -100,9 +103,10 @@ public:
uint8_t read_rom04(offs_t offset);
uint8_t read_rom0c(offs_t offset);
void io_write(offs_t offset, uint8_t data);
+ uint8_t io_read(offs_t offset);
DECLARE_READ_LINE_MEMBER(t0_read) { if (m_cart) return m_cart->t0_read(); else return 0; }
- void write_bank(int bank) { if (m_cart) m_cart->write_bank(bank); }
+ void write_bank(int bank) { if (m_cart) m_cart->write_bank(bank); }
protected:
// device-level overrides
diff --git a/src/devices/bus/odyssey2/voice.cpp b/src/devices/bus/odyssey2/voice.cpp
index 490b9b286ad..b0c93670b78 100644
--- a/src/devices/bus/odyssey2/voice.cpp
+++ b/src/devices/bus/odyssey2/voice.cpp
@@ -88,8 +88,11 @@ WRITE_LINE_MEMBER(o2_voice_device::lrq_callback)
void o2_voice_device::io_write(offs_t offset, uint8_t data)
{
- if (data & 0x20)
- m_speech->ald_w(offset & 0x7f);
- else
- m_speech->reset();
+ if (offset & 0x80)
+ {
+ if (data & 0x20)
+ m_speech->ald_w(offset & 0x7f);
+ else
+ m_speech->reset();
+ }
}