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author Curt Coder <curtcoder@mail.com>2016-03-02 20:54:22 +0200
committer Curt Coder <curtcoder@mail.com>2016-03-02 20:54:32 +0200
commit99ba45ff754a254779a02daef9459912bc4a89b1 (patch)
treea8aa17d7be0b5d3283e56080f8513857ad3de3d5 /src/devices/bus/newbrain
parent7ccca7f3fc4f1257ac450cf690d983ff34d4fcb9 (diff)
newbrain: Dumped the COP internal ROM. [Chris Despinidis]
newbrain: Rewrote the driver to modern standards. [Curt Coder] cop400: Implemented the MICROBUS interface. [Curt Coder]
Diffstat (limited to 'src/devices/bus/newbrain')
-rw-r--r--src/devices/bus/newbrain/eim.cpp303
-rw-r--r--src/devices/bus/newbrain/eim.h90
-rw-r--r--src/devices/bus/newbrain/exp.cpp142
-rw-r--r--src/devices/bus/newbrain/exp.h127
-rw-r--r--src/devices/bus/newbrain/fdc.cpp340
-rw-r--r--src/devices/bus/newbrain/fdc.h79
6 files changed, 1081 insertions, 0 deletions
diff --git a/src/devices/bus/newbrain/eim.cpp b/src/devices/bus/newbrain/eim.cpp
new file mode 100644
index 00000000000..0080b51e938
--- /dev/null
+++ b/src/devices/bus/newbrain/eim.cpp
@@ -0,0 +1,303 @@
+// license:BSD-3-Clause
+// copyright-holders:Curt Coder
+/**********************************************************************
+
+ Grundy NewBrain Expansion Interface Module emulation
+
+**********************************************************************/
+
+/*
+
+ TODO:
+
+ - everything
+
+*/
+
+#include "eim.h"
+
+
+
+//**************************************************************************
+// MACROS / CONSTANTS
+//**************************************************************************
+
+#define LOG 0
+
+#define MC6850_TAG "459"
+#define ADC0809_TAG "427"
+#define DAC0808_TAG "461"
+#define Z80CTC_TAG "458"
+#define RS232_TAG "rs232"
+
+
+
+//**************************************************************************
+// DEVICE DEFINITIONS
+//**************************************************************************
+
+const device_type NEWBRAIN_EIM = &device_creator<newbrain_eim_t>;
+
+
+//-------------------------------------------------
+// ROM( newbrain_eim )
+//-------------------------------------------------
+
+ROM_START( newbrain_eim )
+ ROM_REGION( 0x10000, "eim", 0 )
+ ROM_LOAD( "e415-2.rom", 0x4000, 0x2000, CRC(5b0e390c) SHA1(0f99cae57af2e64f3f6b02e5325138d6ba015e72) )
+ ROM_LOAD( "e415-3.rom", 0x4000, 0x2000, CRC(2f88bae5) SHA1(04e03f230f4b368027442a7c2084dae877f53713) ) // 18/8/83.aci
+ ROM_LOAD( "e416-3.rom", 0x6000, 0x2000, CRC(8b5099d8) SHA1(19b0cfce4c8b220eb1648b467f94113bafcb14e0) ) // 10/8/83.mtv
+ ROM_LOAD( "e417-2.rom", 0x8000, 0x2000, CRC(6a7afa20) SHA1(f90db4f8318777313a862b3d5bab83c2fd260010) )
+ROM_END
+
+
+//-------------------------------------------------
+// rom_region - device-specific ROM region
+//-------------------------------------------------
+
+const rom_entry *newbrain_eim_t::device_rom_region() const
+{
+ return ROM_NAME( newbrain_eim );
+}
+
+
+//-------------------------------------------------
+// MACHINE_CONFIG_FRAGMENT( newbrain_eim )
+//-------------------------------------------------
+
+static MACHINE_CONFIG_FRAGMENT( newbrain_eim )
+ // devices
+ MCFG_DEVICE_ADD(Z80CTC_TAG, Z80CTC, XTAL_16MHz/8)
+ MCFG_Z80CTC_ZC0_CB(DEVWRITELINE(MC6850_TAG, acia6850_device, write_rxc))
+ MCFG_Z80CTC_ZC1_CB(DEVWRITELINE(MC6850_TAG, acia6850_device, write_txc))
+ MCFG_Z80CTC_ZC2_CB(WRITELINE(newbrain_eim_t, ctc_z2_w))
+
+ MCFG_TIMER_DRIVER_ADD_PERIODIC("z80ctc_c2", newbrain_eim_t, ctc_c2_tick, attotime::from_hz(XTAL_16MHz/4/13))
+ MCFG_DEVICE_ADD(ADC0809_TAG, ADC0808, 500000)
+ MCFG_ADC0808_OUT_EOC_CB(WRITELINE(newbrain_eim_t, adc_eoc_w))
+ MCFG_ADC0808_IN_VREF_POS_CB(newbrain_eim_t, adc_vref_pos_r)
+ MCFG_ADC0808_IN_VREF_NEG_CB(newbrain_eim_t, adc_vref_neg_r)
+ MCFG_ADC0808_IN_IN_0_CB(newbrain_eim_t, adc_input_r)
+ MCFG_ADC0808_IN_IN_1_CB(newbrain_eim_t, adc_input_r)
+ MCFG_ADC0808_IN_IN_2_CB(newbrain_eim_t, adc_input_r)
+ MCFG_ADC0808_IN_IN_3_CB(newbrain_eim_t, adc_input_r)
+ MCFG_ADC0808_IN_IN_4_CB(newbrain_eim_t, adc_input_r)
+ MCFG_ADC0808_IN_IN_5_CB(newbrain_eim_t, adc_input_r)
+ MCFG_ADC0808_IN_IN_6_CB(newbrain_eim_t, adc_input_r)
+ MCFG_ADC0808_IN_IN_7_CB(newbrain_eim_t, adc_input_r)
+
+ MCFG_DEVICE_ADD(MC6850_TAG, ACIA6850, 0)
+ MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(newbrain_eim_t, acia_interrupt))
+ MCFG_RS232_PORT_ADD(RS232_TAG, default_rs232_devices, nullptr)
+
+ MCFG_NEWBRAIN_EXPANSION_SLOT_ADD(NEWBRAIN_EXPANSION_SLOT_TAG, XTAL_16MHz/8, newbrain_expansion_cards, "fdc")
+
+ // internal ram
+ MCFG_RAM_ADD(RAM_TAG)
+ MCFG_RAM_DEFAULT_SIZE("96K")
+MACHINE_CONFIG_END
+
+
+//-------------------------------------------------
+// machine_config_additions - device-specific
+// machine configurations
+//-------------------------------------------------
+
+machine_config_constructor newbrain_eim_t::device_mconfig_additions() const
+{
+ return MACHINE_CONFIG_NAME( newbrain_eim );
+}
+
+
+
+//**************************************************************************
+// LIVE DEVICE
+//**************************************************************************
+
+//-------------------------------------------------
+// newbrain_eim_t - constructor
+//-------------------------------------------------
+
+newbrain_eim_t::newbrain_eim_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
+ device_t(mconfig, NEWBRAIN_EIM, "Newbrain EIM", tag, owner, clock, "newbrain_eim", __FILE__),
+ device_newbrain_expansion_slot_interface(mconfig, *this),
+ m_ctc(*this, Z80CTC_TAG),
+ m_acia(*this, MC6850_TAG),
+ m_exp(*this, NEWBRAIN_EXPANSION_SLOT_TAG),
+ m_rom(*this, "eim"),
+ m_ram(*this, RAM_TAG)
+{
+}
+
+
+//-------------------------------------------------
+// device_start - device-specific startup
+//-------------------------------------------------
+
+void newbrain_eim_t::device_start()
+{
+ // state saving
+ save_item(NAME(m_aciaint));
+ save_item(NAME(m_anint));
+}
+
+
+//-------------------------------------------------
+// device_reset - device-specific reset
+//-------------------------------------------------
+
+void newbrain_eim_t::device_reset()
+{
+}
+
+
+//-------------------------------------------------
+// mreq_r - memory request read
+//-------------------------------------------------
+
+UINT8 newbrain_eim_t::mreq_r(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh)
+{
+ return m_exp->mreq_r(space, offset, data, romov, exrm, raminh);
+}
+
+
+//-------------------------------------------------
+// mreq_w - memory request write
+//-------------------------------------------------
+
+void newbrain_eim_t::mreq_w(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh)
+{
+ m_exp->mreq_w(space, offset, data, romov, exrm, raminh);
+}
+
+
+//-------------------------------------------------
+// iorq_r - I/O request read
+//-------------------------------------------------
+
+UINT8 newbrain_eim_t::iorq_r(address_space &space, offs_t offset, UINT8 data, bool &prtov)
+{
+ return m_exp->iorq_r(space, offset, data, prtov);
+}
+
+
+//-------------------------------------------------
+// iorq_w - I/O request write
+//-------------------------------------------------
+
+void newbrain_eim_t::iorq_w(address_space &space, offs_t offset, UINT8 data, bool &prtov)
+{
+ m_exp->iorq_w(space, offset, data, prtov);
+}
+
+
+//-------------------------------------------------
+// anout_r -
+//-------------------------------------------------
+
+READ8_MEMBER( newbrain_eim_t::anout_r )
+{
+ return 0xff;
+}
+
+
+//-------------------------------------------------
+// anout_w -
+//-------------------------------------------------
+
+WRITE8_MEMBER( newbrain_eim_t::anout_w )
+{
+}
+
+
+//-------------------------------------------------
+// anin_r -
+//-------------------------------------------------
+
+READ8_MEMBER( newbrain_eim_t::anin_r )
+{
+ return 0;
+}
+
+
+//-------------------------------------------------
+// anio_w -
+//-------------------------------------------------
+
+WRITE8_MEMBER( newbrain_eim_t::anio_w )
+{
+}
+
+
+//-------------------------------------------------
+// adc_eoc_w -
+//-------------------------------------------------
+
+WRITE_LINE_MEMBER( newbrain_eim_t::adc_eoc_w )
+{
+ m_anint = state;
+}
+
+
+//-------------------------------------------------
+// adc_vref_pos_r -
+//-------------------------------------------------
+
+ADC0808_ANALOG_READ_CB( newbrain_eim_t::adc_vref_pos_r )
+{
+ return 5.0;
+}
+
+
+//-------------------------------------------------
+// adc_vref_neg_r -
+//-------------------------------------------------
+
+ADC0808_ANALOG_READ_CB( newbrain_eim_t::adc_vref_neg_r )
+{
+ return 0.0;
+}
+
+
+//-------------------------------------------------
+// adc_input_r -
+//-------------------------------------------------
+
+ADC0808_ANALOG_READ_CB( newbrain_eim_t::adc_input_r )
+{
+ return 0.0;
+}
+
+
+//-------------------------------------------------
+// acia_interrupt -
+//-------------------------------------------------
+
+WRITE_LINE_MEMBER( newbrain_eim_t::acia_interrupt )
+{
+ m_aciaint = state;
+}
+
+
+//-------------------------------------------------
+// ctc_z2_w -
+//-------------------------------------------------
+
+WRITE_LINE_MEMBER( newbrain_eim_t::ctc_z2_w )
+{
+ // connected to CTC channel 0/1 clock inputs
+ m_ctc->trg0(state);
+ m_ctc->trg1(state);
+}
+
+
+//-------------------------------------------------
+// adc_input_r -
+//-------------------------------------------------
+
+TIMER_DEVICE_CALLBACK_MEMBER(newbrain_eim_t::ctc_c2_tick)
+{
+ m_ctc->trg2(1);
+ m_ctc->trg2(0);
+}
diff --git a/src/devices/bus/newbrain/eim.h b/src/devices/bus/newbrain/eim.h
new file mode 100644
index 00000000000..490a6a15c03
--- /dev/null
+++ b/src/devices/bus/newbrain/eim.h
@@ -0,0 +1,90 @@
+// license:BSD-3-Clause
+// copyright-holders:Curt Coder
+/**********************************************************************
+
+ Grundy NewBrain Expansion Interface Module emulation
+
+**********************************************************************/
+
+#pragma once
+
+#ifndef __NEWBRAIN_EIM__
+#define __NEWBRAIN_EIM__
+
+#include "emu.h"
+#include "exp.h"
+#include "bus/rs232/rs232.h"
+#include "machine/6850acia.h"
+#include "machine/adc0808.h"
+#include "machine/z80ctc.h"
+#include "machine/ram.h"
+
+
+
+//**************************************************************************
+// TYPE DEFINITIONS
+//**************************************************************************
+
+// ======================> newbrain_eim_t
+
+class newbrain_eim_t : public device_t,
+ public device_newbrain_expansion_slot_interface
+{
+public:
+ // construction/destruction
+ newbrain_eim_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+ // optional information overrides
+ virtual const rom_entry *device_rom_region() const override;
+ virtual machine_config_constructor device_mconfig_additions() const override;
+
+ DECLARE_READ8_MEMBER( anout_r );
+ DECLARE_WRITE8_MEMBER( anout_w );
+ DECLARE_READ8_MEMBER( anin_r );
+ DECLARE_WRITE8_MEMBER( anio_w );
+ DECLARE_READ8_MEMBER( st0_r );
+ DECLARE_READ8_MEMBER( st1_r );
+ DECLARE_READ8_MEMBER( st2_r );
+ DECLARE_READ8_MEMBER( usbs_r );
+ DECLARE_WRITE8_MEMBER( usbs_w );
+ DECLARE_WRITE8_MEMBER( paging_w );
+ DECLARE_WRITE_LINE_MEMBER( acia_tx );
+ DECLARE_WRITE_LINE_MEMBER( acia_interrupt );
+ DECLARE_WRITE_LINE_MEMBER( ctc_z2_w );
+ DECLARE_WRITE_LINE_MEMBER( adc_eoc_w );
+
+ ADC0808_ANALOG_READ_CB(adc_vref_pos_r);
+ ADC0808_ANALOG_READ_CB(adc_vref_neg_r);
+ ADC0808_ANALOG_READ_CB(adc_input_r);
+
+ TIMER_DEVICE_CALLBACK_MEMBER(ctc_c2_tick);
+
+protected:
+ // device-level overrides
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ // device_newbrain_expansion_slot_interface overrides
+ virtual UINT8 mreq_r(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh) override;
+ virtual void mreq_w(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh) override;
+ virtual UINT8 iorq_r(address_space &space, offs_t offset, UINT8 data, bool &prtov) override;
+ virtual void iorq_w(address_space &space, offs_t offset, UINT8 data, bool &prtov) override;
+
+private:
+ required_device<z80ctc_device> m_ctc;
+ required_device<acia6850_device> m_acia;
+ required_device<newbrain_expansion_slot_t> m_exp;
+ required_memory_region m_rom;
+ optional_shared_ptr<UINT8> m_ram;
+
+ int m_aciaint;
+ int m_anint;
+};
+
+
+// device type definition
+extern const device_type NEWBRAIN_EIM;
+
+
+
+#endif
diff --git a/src/devices/bus/newbrain/exp.cpp b/src/devices/bus/newbrain/exp.cpp
new file mode 100644
index 00000000000..12f44ac243f
--- /dev/null
+++ b/src/devices/bus/newbrain/exp.cpp
@@ -0,0 +1,142 @@
+// license:BSD-3-Clause
+// copyright-holders:Curt Coder
+/**********************************************************************
+
+ Grundy NewBrain Expansion Port emulation
+
+**********************************************************************/
+
+#include "exp.h"
+
+
+
+//**************************************************************************
+// GLOBAL VARIABLES
+//**************************************************************************
+
+const device_type NEWBRAIN_EXPANSION_SLOT = &device_creator<newbrain_expansion_slot_t>;
+
+
+
+//**************************************************************************
+// CARD INTERFACE
+//**************************************************************************
+
+//-------------------------------------------------
+// device_newbrain_expansion_slot_interface - constructor
+//-------------------------------------------------
+
+device_newbrain_expansion_slot_interface::device_newbrain_expansion_slot_interface(const machine_config &mconfig, device_t &device) :
+ device_slot_card_interface(mconfig,device)
+{
+ m_slot = dynamic_cast<newbrain_expansion_slot_t *>(device.owner());
+}
+
+
+
+//**************************************************************************
+// LIVE DEVICE
+//**************************************************************************
+
+//-------------------------------------------------
+// newbrain_expansion_slot_t - constructor
+//-------------------------------------------------
+
+newbrain_expansion_slot_t::newbrain_expansion_slot_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
+ device_t(mconfig, NEWBRAIN_EXPANSION_SLOT, "NewBrain expansion port", tag, owner, clock, "newbrain_expansion_slot", __FILE__),
+ device_slot_interface(mconfig, *this), m_card(nullptr)
+{
+}
+
+
+//-------------------------------------------------
+// device_start - device-specific startup
+//-------------------------------------------------
+
+void newbrain_expansion_slot_t::device_start()
+{
+ m_card = dynamic_cast<device_newbrain_expansion_slot_interface *>(get_card_device());
+}
+
+
+//-------------------------------------------------
+// device_reset - device-specific reset
+//-------------------------------------------------
+
+void newbrain_expansion_slot_t::device_reset()
+{
+ if (m_card != nullptr)
+ {
+ m_card->device().reset();
+ }
+}
+
+
+//-------------------------------------------------
+// mreq_r - memory request read
+//-------------------------------------------------
+
+UINT8 newbrain_expansion_slot_t::mreq_r(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh)
+{
+ if (m_card != nullptr)
+ {
+ data = m_card->mreq_r(space, offset, data, romov, exrm, raminh);
+ }
+
+ return data;
+}
+
+
+//-------------------------------------------------
+// mreq_w - memory request write
+//-------------------------------------------------
+
+void newbrain_expansion_slot_t::mreq_w(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh)
+{
+ if (m_card != nullptr)
+ {
+ m_card->mreq_w(space, offset, data, romov, exrm, raminh);
+ }
+}
+
+
+//-------------------------------------------------
+// iorq_r - I/O request read
+//-------------------------------------------------
+
+UINT8 newbrain_expansion_slot_t::iorq_r(address_space &space, offs_t offset, UINT8 data, bool &prtov)
+{
+ if (m_card != nullptr)
+ {
+ data = m_card->iorq_r(space, offset, data, prtov);
+ }
+
+ return data;
+}
+
+
+//-------------------------------------------------
+// iorq_w - I/O request write
+//-------------------------------------------------
+
+void newbrain_expansion_slot_t::iorq_w(address_space &space, offs_t offset, UINT8 data, bool &prtov)
+{
+ if (m_card != nullptr)
+ {
+ m_card->iorq_w(space, offset, data, prtov);
+ }
+}
+
+
+//-------------------------------------------------
+// SLOT_INTERFACE( newbrain_expansion_cards )
+//-------------------------------------------------
+
+// slot devices
+#include "eim.h"
+#include "fdc.h"
+
+SLOT_INTERFACE_START( newbrain_expansion_cards )
+ SLOT_INTERFACE("eim", NEWBRAIN_EIM)
+ SLOT_INTERFACE("fdc", NEWBRAIN_FDC)
+SLOT_INTERFACE_END
diff --git a/src/devices/bus/newbrain/exp.h b/src/devices/bus/newbrain/exp.h
new file mode 100644
index 00000000000..dc8bbc87cf5
--- /dev/null
+++ b/src/devices/bus/newbrain/exp.h
@@ -0,0 +1,127 @@
+// license:BSD-3-Clause
+// copyright-holders:Curt Coder
+/**********************************************************************
+
+ Grundy NewBrain Expansion Port emulation
+
+**********************************************************************
+
+ GND 1 26 A6
+ 1/8C 2 27 _RAMENB
+ A14 3 28 EXRM2
+ A13 4 29 EXRM1
+ D5 5 30 EXRM0
+ RMSL 6 31 _ROMOV
+ D4 7 32 _BUSRQ
+ D3 8 33 _M1
+ D6 9 34 _RST
+ D7 10 35 _RFRSH
+ A11 11 36 _WAIT
+ A10 12 37 A4
+ A8 13 38 _BUSAK
+ A9 14 39 A15
+ A12 15 40 _WR
+ A7 16 41 _INT
+ A3 17 42 _RD
+ A2 18 43 _NMI
+ A1 19 44 _HALT
+ A0 20 45 _MREQ
+ D0 21 46 _IORQ
+ D1 22 47 PRTOV
+ _FCTR 23 48 _RAMINH
+ D2 24 49 +5V
+ A5 25 50 .
+
+**********************************************************************/
+
+#pragma once
+
+#ifndef __NEWBRAIN_EXPANSION_SLOT__
+#define __NEWBRAIN_EXPANSION_SLOT__
+
+#include "emu.h"
+
+
+
+//**************************************************************************
+// CONSTANTS
+//**************************************************************************
+
+#define NEWBRAIN_EXPANSION_SLOT_TAG "exp"
+
+
+
+//**************************************************************************
+// INTERFACE CONFIGURATION MACROS
+//**************************************************************************
+
+#define MCFG_NEWBRAIN_EXPANSION_SLOT_ADD(_tag, _clock, _slot_intf, _def_slot) \
+ MCFG_DEVICE_ADD(_tag, NEWBRAIN_EXPANSION_SLOT, _clock) \
+ MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
+
+
+
+//**************************************************************************
+// TYPE DEFINITIONS
+//**************************************************************************
+
+// ======================> newbrain_expansion_slot_t
+
+class device_newbrain_expansion_slot_interface;
+
+class newbrain_expansion_slot_t : public device_t,
+ public device_slot_interface
+{
+public:
+ // construction/destruction
+ newbrain_expansion_slot_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ virtual ~newbrain_expansion_slot_t() { }
+
+ // computer interface
+ UINT8 mreq_r(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh);
+ void mreq_w(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh);
+
+ UINT8 iorq_r(address_space &space, offs_t offset, UINT8 data, bool &prtov);
+ void iorq_w(address_space &space, offs_t offset, UINT8 data, bool &prtov);
+
+protected:
+ // device-level overrides
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ device_newbrain_expansion_slot_interface *m_card;
+};
+
+
+// ======================> device_newbrain_expansion_slot_interface
+
+// class representing interface-specific live newbrain_expansion card
+class device_newbrain_expansion_slot_interface : public device_slot_card_interface
+{
+public:
+ // construction/destruction
+ device_newbrain_expansion_slot_interface(const machine_config &mconfig, device_t &device);
+ virtual ~device_newbrain_expansion_slot_interface() { }
+
+ // memory access
+ virtual UINT8 mreq_r(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh) { return data; };
+ virtual void mreq_w(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh) { };
+
+ // I/O access
+ virtual UINT8 iorq_r(address_space &space, offs_t offset, UINT8 data, bool &prtov) { return data; };
+ virtual void iorq_w(address_space &space, offs_t offset, UINT8 data, bool &prtov) { };
+
+protected:
+ newbrain_expansion_slot_t *m_slot;
+};
+
+
+// device type definition
+extern const device_type NEWBRAIN_EXPANSION_SLOT;
+
+
+SLOT_INTERFACE_EXTERN( newbrain_expansion_cards );
+
+
+
+#endif
diff --git a/src/devices/bus/newbrain/fdc.cpp b/src/devices/bus/newbrain/fdc.cpp
new file mode 100644
index 00000000000..976cc6bf6fd
--- /dev/null
+++ b/src/devices/bus/newbrain/fdc.cpp
@@ -0,0 +1,340 @@
+// license:BSD-3-Clause
+// copyright-holders:Curt Coder
+/**********************************************************************
+
+ Grundy NewBrain Expansion Interface Module emulation
+
+**********************************************************************/
+
+/*
+
+ TODO:
+
+ - map d413 ROM to computer space
+ - paging
+
+*/
+
+#include "fdc.h"
+
+
+
+//**************************************************************************
+// MACROS / CONSTANTS
+//**************************************************************************
+
+#define LOG 0
+
+#define Z80_TAG "416"
+#define UPD765_TAG "418"
+
+
+
+//**************************************************************************
+// DEVICE DEFINITIONS
+//**************************************************************************
+
+const device_type NEWBRAIN_FDC = &device_creator<newbrain_fdc_t>;
+
+
+//-------------------------------------------------
+// ROM( newbrain_fdc )
+//-------------------------------------------------
+
+ROM_START( newbrain_fdc )
+ ROM_REGION( 0x2000, "d413", 0 )
+ ROM_LOAD( "d413-2.rom", 0x0000, 0x2000, CRC(097591f1) SHA1(c2aa1d27d4f3a24ab0c8135df746a4a44201a7f4) )
+
+ ROM_REGION( 0x2000, Z80_TAG, 0 )
+ ROM_DEFAULT_BIOS("issue2")
+ ROM_SYSTEM_BIOS( 0, "issue1", "Issue 1" )
+ ROMX_LOAD( "d417-1.rom", 0x0000, 0x2000, CRC(40fad31c) SHA1(5137be4cc026972c0ffd4fa6990e8583bdfce163), ROM_BIOS(1) )
+ ROM_SYSTEM_BIOS( 1, "issue2", "Issue 2" )
+ ROMX_LOAD( "d417-2.rom", 0x0000, 0x2000, CRC(e8bda8b9) SHA1(c85a76a5ff7054f4ef4a472ce99ebaed1abd269c), ROM_BIOS(2) )
+ROM_END
+
+
+//-------------------------------------------------
+// rom_region - device-specific ROM region
+//-------------------------------------------------
+
+const rom_entry *newbrain_fdc_t::device_rom_region() const
+{
+ return ROM_NAME( newbrain_fdc );
+}
+
+
+//-------------------------------------------------
+// ADDRESS_MAP( newbrain_fdc_mem )
+//-------------------------------------------------
+
+static ADDRESS_MAP_START( newbrain_fdc_mem, AS_PROGRAM, 8, newbrain_fdc_t )
+ ADDRESS_MAP_UNMAP_HIGH
+ AM_RANGE(0x0000, 0x1fff) AM_ROM
+ADDRESS_MAP_END
+
+
+//-------------------------------------------------
+// ADDRESS_MAP( newbrain_fdc_io )
+//-------------------------------------------------
+
+static ADDRESS_MAP_START( newbrain_fdc_io, AS_IO, 8, newbrain_fdc_t )
+ ADDRESS_MAP_UNMAP_HIGH
+ ADDRESS_MAP_GLOBAL_MASK(0xd1)
+ AM_RANGE(0x00, 0x01) AM_MIRROR(0x1e) AM_DEVICE(UPD765_TAG, upd765a_device, map)
+ AM_RANGE(0x20, 0x20) AM_MIRROR(0x1f) AM_WRITE(fdc_auxiliary_w)
+ AM_RANGE(0x40, 0x40) AM_MIRROR(0x1f) AM_READ(fdc_control_r)
+ADDRESS_MAP_END
+
+
+//-------------------------------------------------
+// newbrain_floppies
+//-------------------------------------------------
+
+static SLOT_INTERFACE_START( newbrain_floppies )
+ SLOT_INTERFACE( "525dd", FLOPPY_525_DD )
+SLOT_INTERFACE_END
+
+
+//-------------------------------------------------
+// MACHINE_CONFIG_FRAGMENT( newbrain_fdc )
+//-------------------------------------------------
+
+static MACHINE_CONFIG_FRAGMENT( newbrain_fdc )
+ MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_4MHz)
+ MCFG_CPU_PROGRAM_MAP(newbrain_fdc_mem)
+ MCFG_CPU_IO_MAP(newbrain_fdc_io)
+
+ MCFG_UPD765A_ADD(UPD765_TAG, false, true)
+ MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(newbrain_fdc_t, fdc_int_w))
+
+ MCFG_FLOPPY_DRIVE_ADD(UPD765_TAG ":0", newbrain_floppies, "525dd", floppy_image_device::default_floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD(UPD765_TAG ":1", newbrain_floppies, "525dd", floppy_image_device::default_floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD(UPD765_TAG ":2", newbrain_floppies, nullptr, floppy_image_device::default_floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD(UPD765_TAG ":3", newbrain_floppies, nullptr, floppy_image_device::default_floppy_formats)
+
+ MCFG_NEWBRAIN_EXPANSION_SLOT_ADD(NEWBRAIN_EXPANSION_SLOT_TAG, XTAL_16MHz/8, newbrain_expansion_cards, nullptr)
+MACHINE_CONFIG_END
+
+
+//-------------------------------------------------
+// machine_config_additions - device-specific
+// machine configurations
+//-------------------------------------------------
+
+machine_config_constructor newbrain_fdc_t::device_mconfig_additions() const
+{
+ return MACHINE_CONFIG_NAME( newbrain_fdc );
+}
+
+
+//**************************************************************************
+// LIVE DEVICE
+//**************************************************************************
+
+//-------------------------------------------------
+// newbrain_fdc_t - constructor
+//-------------------------------------------------
+
+newbrain_fdc_t::newbrain_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
+ device_t(mconfig, NEWBRAIN_FDC, "NewBrain FDC", tag, owner, clock, "newbrain_fdc", __FILE__),
+ device_newbrain_expansion_slot_interface(mconfig, *this),
+ m_maincpu(*this, Z80_TAG),
+ m_fdc(*this, UPD765_TAG),
+ m_floppy0(*this, UPD765_TAG ":0"),
+ m_floppy1(*this, UPD765_TAG ":1"),
+ m_floppy2(*this, UPD765_TAG ":2"),
+ m_floppy3(*this, UPD765_TAG ":3"),
+ m_exp(*this, NEWBRAIN_EXPANSION_SLOT_TAG)
+{
+}
+
+
+//-------------------------------------------------
+// device_start - device-specific startup
+//-------------------------------------------------
+
+void newbrain_fdc_t::device_start()
+{
+ save_item(NAME(m_paging));
+ save_item(NAME(m_ma16));
+ save_item(NAME(m_mpm));
+ save_item(NAME(m_fdc_att));
+ save_item(NAME(m_fdc_int));
+ save_item(NAME(m_pa15));
+}
+
+
+//-------------------------------------------------
+// device_reset - device-specific reset
+//-------------------------------------------------
+
+void newbrain_fdc_t::device_reset()
+{
+ m_maincpu->reset();
+
+ moton(0);
+ m_fdc->tc_w(0);
+ m_pa15 = 0;
+}
+
+
+//-------------------------------------------------
+// mreq_r - memory request read
+//-------------------------------------------------
+
+UINT8 newbrain_fdc_t::mreq_r(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh)
+{
+ return m_exp->mreq_r(space, offset, data, romov, exrm, raminh);
+}
+
+
+//-------------------------------------------------
+// mreq_w - memory request write
+//-------------------------------------------------
+
+void newbrain_fdc_t::mreq_w(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh)
+{
+ m_exp->mreq_w(space, offset, data, romov, exrm, raminh);
+}
+
+
+//-------------------------------------------------
+// iorq_r - I/O request read
+//-------------------------------------------------
+
+UINT8 newbrain_fdc_t::iorq_r(address_space &space, offs_t offset, UINT8 data, bool &prtov)
+{
+ return m_exp->iorq_r(space, offset, data, prtov);
+}
+
+
+//-------------------------------------------------
+// iorq_w - I/O request write
+//-------------------------------------------------
+
+void newbrain_fdc_t::iorq_w(address_space &space, offs_t offset, UINT8 data, bool &prtov)
+{
+ m_exp->iorq_w(space, offset, data, prtov);
+
+ if ((offset & 0x20f) == 0x20f)
+ {
+ io_dec_w(space, 0, data);
+ }
+}
+
+
+//-------------------------------------------------
+// moton - floppy motor on
+//-------------------------------------------------
+
+void newbrain_fdc_t::moton(int state)
+{
+ if (m_floppy0->get_device()) m_floppy0->get_device()->mon_w(!state);
+ if (m_floppy1->get_device()) m_floppy1->get_device()->mon_w(!state);
+ if (m_floppy2->get_device()) m_floppy2->get_device()->mon_w(!state);
+ if (m_floppy3->get_device()) m_floppy3->get_device()->mon_w(!state);
+}
+
+
+//-------------------------------------------------
+// fdc_int_w -
+//-------------------------------------------------
+
+WRITE_LINE_MEMBER( newbrain_fdc_t::fdc_int_w )
+{
+ m_fdc_int = state;
+}
+
+
+//-------------------------------------------------
+// fdc_auxiliary_w -
+//-------------------------------------------------
+
+WRITE8_MEMBER( newbrain_fdc_t::fdc_auxiliary_w )
+{
+ /*
+
+ bit description
+
+ 0 MOTON
+ 1 765 RESET
+ 2 TC
+ 3
+ 4
+ 5 PA15
+ 6
+ 7
+
+ */
+
+ moton(BIT(data, 0));
+
+ if (BIT(data, 1))
+ {
+ m_fdc->reset();
+ }
+
+ m_fdc->tc_w(BIT(data, 2));
+
+ m_pa15 = BIT(data, 5);
+}
+
+
+//-------------------------------------------------
+// fdc_control_r -
+//-------------------------------------------------
+
+READ8_MEMBER( newbrain_fdc_t::fdc_control_r )
+{
+ /*
+
+ bit description
+
+ 0
+ 1
+ 2
+ 3
+ 4
+ 5 FDC INT
+ 6 PAGING
+ 7 FDC ATT
+
+ */
+
+ return (m_fdc_att << 7) | (m_paging << 6) | (m_fdc_int << 5);
+}
+
+
+//-------------------------------------------------
+// io_dec_w - 0x20f
+//-------------------------------------------------
+
+WRITE8_MEMBER( newbrain_fdc_t::io_dec_w )
+{
+ /*
+
+ bit description
+
+ 0 PAGING
+ 1
+ 2 MA16
+ 3 MPM
+ 4
+ 5 _FDC RESET
+ 6
+ 7 FDC ATT
+
+ */
+
+ m_paging = BIT(data, 0);
+ m_ma16 = BIT(data, 2);
+ m_mpm = BIT(data, 3);
+
+ if (!BIT(data, 5))
+ {
+ device_reset();
+ }
+
+ m_fdc_att = BIT(data, 7);
+}
diff --git a/src/devices/bus/newbrain/fdc.h b/src/devices/bus/newbrain/fdc.h
new file mode 100644
index 00000000000..2e4e21abbc0
--- /dev/null
+++ b/src/devices/bus/newbrain/fdc.h
@@ -0,0 +1,79 @@
+// license:BSD-3-Clause
+// copyright-holders:Curt Coder
+/**********************************************************************
+
+ Grundy NewBrain FDC emulation
+
+**********************************************************************/
+
+#pragma once
+
+#ifndef __NEWBRAIN_FDC__
+#define __NEWBRAIN_FDC__
+
+#include "emu.h"
+#include "exp.h"
+#include "cpu/z80/z80.h"
+#include "machine/upd765.h"
+
+
+
+//**************************************************************************
+// TYPE DEFINITIONS
+//**************************************************************************
+
+// ======================> newbrain_fdc_t
+
+class newbrain_fdc_t : public device_t,
+ public device_newbrain_expansion_slot_interface
+{
+public:
+ // construction/destruction
+ newbrain_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+ // optional information overrides
+ virtual const rom_entry *device_rom_region() const override;
+ virtual machine_config_constructor device_mconfig_additions() const override;
+
+ DECLARE_WRITE_LINE_MEMBER( fdc_int_w );
+ DECLARE_WRITE8_MEMBER( fdc_auxiliary_w );
+ DECLARE_READ8_MEMBER( fdc_control_r );
+ DECLARE_WRITE8_MEMBER( io_dec_w );
+
+protected:
+ // device-level overrides
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ // device_newbrain_expansion_slot_interface overrides
+ virtual UINT8 mreq_r(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh) override;
+ virtual void mreq_w(address_space &space, offs_t offset, UINT8 data, bool &romov, int &exrm, bool &raminh) override;
+ virtual UINT8 iorq_r(address_space &space, offs_t offset, UINT8 data, bool &prtov) override;
+ virtual void iorq_w(address_space &space, offs_t offset, UINT8 data, bool &prtov) override;
+
+private:
+ required_device<z80_device> m_maincpu;
+ required_device<upd765a_device> m_fdc;
+ required_device<floppy_connector> m_floppy0;
+ required_device<floppy_connector> m_floppy1;
+ required_device<floppy_connector> m_floppy2;
+ required_device<floppy_connector> m_floppy3;
+ required_device<newbrain_expansion_slot_t> m_exp;
+
+ void moton(int state);
+
+ int m_paging;
+ int m_ma16;
+ int m_mpm;
+ int m_fdc_att;
+ int m_fdc_int;
+ int m_pa15;
+};
+
+
+// device type definition
+extern const device_type NEWBRAIN_FDC;
+
+
+
+#endif