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author Olivier Galibert <galibert@pobox.com>2017-12-15 12:45:49 +0100
committer Olivier Galibert <galibert@pobox.com>2017-12-16 13:22:21 +0100
commit77829f86719aa73ec3eddf08a9c7dfa71c89f5f3 (patch)
treefadd5f17e77cbe4c01646dcc326e665bb21df4ff /src/devices/bus/isa/xtide.cpp
parent00c799de12624a06d243ba9c36efdfbb33c36315 (diff)
ide: deambiguate cs access between 16 and 32 bits [O. Galibert]
Diffstat (limited to 'src/devices/bus/isa/xtide.cpp')
-rw-r--r--src/devices/bus/isa/xtide.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/devices/bus/isa/xtide.cpp b/src/devices/bus/isa/xtide.cpp
index 6226b0d801b..0b1ea0490bc 100644
--- a/src/devices/bus/isa/xtide.cpp
+++ b/src/devices/bus/isa/xtide.cpp
@@ -63,13 +63,13 @@ READ8_MEMBER( xtide_device::read )
if (offset == 0)
{
- uint16_t data16 = m_ata->read_cs0(space, offset & 7, 0xffff);
+ uint16_t data16 = m_ata->read16_cs0(space, offset & 7, 0xffff);
result = data16 & 0xff;
m_d8_d15_latch = data16 >> 8;
}
else if (offset < 8)
{
- result = m_ata->read_cs0(space, offset & 7, 0xff);
+ result = m_ata->read16_cs0(space, offset & 7, 0xff);
}
else if (offset == 8)
{
@@ -77,7 +77,7 @@ READ8_MEMBER( xtide_device::read )
}
else
{
- result = m_ata->read_cs1(space, offset & 7, 0xff);
+ result = m_ata->read16_cs1(space, offset & 7, 0xff);
}
// logerror("%s xtide_device::read: offset=%d, result=%2X\n",device->machine().describe_context(),offset,result);
@@ -93,11 +93,11 @@ WRITE8_MEMBER( xtide_device::write )
{
// Data register transfer low byte and latched high
uint16_t data16 = (m_d8_d15_latch << 8) | data;
- m_ata->write_cs0(space, offset & 7, data16, 0xffff);
+ m_ata->write16_cs0(space, offset & 7, data16, 0xffff);
}
else if (offset < 8)
{
- m_ata->write_cs0(space, offset & 7, data, 0xff);
+ m_ata->write16_cs0(space, offset & 7, data, 0xff);
}
else if (offset == 8)
{
@@ -105,7 +105,7 @@ WRITE8_MEMBER( xtide_device::write )
}
else
{
- m_ata->write_cs1(space, offset & 7, data, 0xff);
+ m_ata->write16_cs1(space, offset & 7, data, 0xff);
}
}