summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/bus/isa/xtide.cpp
diff options
context:
space:
mode:
author hap <happppp@users.noreply.github.com>2023-06-16 11:36:33 +0200
committer hap <happppp@users.noreply.github.com>2023-06-16 11:36:43 +0200
commit3e94326fe23d2b62a27a69a720d6f36bbf620496 (patch)
tree39cc8f2a3948aa2906556b4e9ae0a58a9710d98d /src/devices/bus/isa/xtide.cpp
parent0f014596d7e343c54c1954ea18b2e57e464b344b (diff)
turbo,zaxxon: set 8255 tristate to 0,
m6800: zerofill more class variables, misc: change "Bios" to "BIOS"
Diffstat (limited to 'src/devices/bus/isa/xtide.cpp')
-rw-r--r--src/devices/bus/isa/xtide.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/devices/bus/isa/xtide.cpp b/src/devices/bus/isa/xtide.cpp
index 4686edb6739..c21b6c12d54 100644
--- a/src/devices/bus/isa/xtide.cpp
+++ b/src/devices/bus/isa/xtide.cpp
@@ -11,7 +11,7 @@ Card has jumpers for I/O base address, and ROM base address, the default
rom images being we'll emulate an I/O base of 0x300 and a ROM base of 0xC8000.
If the I/O address is changed then you will need to use XTIDECFG to configure the ROM.
-The opensource bios is available from :
+The opensource BIOS is available from :
http://code.google.com/p/xtideuniversalbios/
The data high register is connected to a pair of latches that have the MSB of
@@ -175,10 +175,10 @@ ROM_START( xtide )
ROM_DEFAULT_BIOS("xub200b3xt")
- ROM_SYSTEM_BIOS( 0, "xtide_010", "Hargle's Bios v0.10" )
+ ROM_SYSTEM_BIOS( 0, "xtide_010", "Hargle's BIOS v0.10" )
ROMX_LOAD( "oprom.bin,v0.10", 0x000000, 0x002000, CRC(56075ac2) SHA1(f55285a1ed8414c8ddf2364421552e0548cf548f), ROM_BIOS(0) )
- ROM_SYSTEM_BIOS( 1, "xtide_011", "Hargle's Bios v0.11" )
+ ROM_SYSTEM_BIOS( 1, "xtide_011", "Hargle's BIOS v0.11" )
ROMX_LOAD( "oprom.bin,v0.11", 0x000000, 0x002000, CRC(c5fee6c5) SHA1(cc3a015d8d36208d99de8500c962828d2daea939), ROM_BIOS(1) )
ROM_SYSTEM_BIOS( 2, "xub110xt", "XTIDE_Universal_BIOS_v1.1.0 (XT)" )