diff options
author | Vas Crabb <vas@vastheman.com> | 2017-03-26 12:57:49 +1100 |
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committer | Vas Crabb <vas@vastheman.com> | 2017-03-26 12:57:49 +1100 |
commit | 6cb38b0771d189f412a7efae1e2d095b3cfa9c76 (patch) | |
tree | f140ee3a4396f3f4079ae1aab09a694dda410848 /src/devices/bus/hp_hil/hp_hil.h | |
parent | 770356315a434c9465510addb96211e060f8a928 (diff) |
srcclean (nw)
Diffstat (limited to 'src/devices/bus/hp_hil/hp_hil.h')
-rw-r--r-- | src/devices/bus/hp_hil/hp_hil.h | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/src/devices/bus/hp_hil/hp_hil.h b/src/devices/bus/hp_hil/hp_hil.h index ec531c6c3ff..7b805f1528f 100644 --- a/src/devices/bus/hp_hil/hp_hil.h +++ b/src/devices/bus/hp_hil/hp_hil.h @@ -14,51 +14,51 @@ #include "emu.h" -#define HPMLC_R1_OB 0x10 +#define HPMLC_R1_OB 0x10 -#define HPMLC_W1_C 0x0800 +#define HPMLC_W1_C 0x0800 -#define HPMLC_R2_PERR 0x01 -#define HPMLC_R2_FERR 0x02 -#define HPMLC_R2_FOF 0x04 +#define HPMLC_R2_PERR 0x01 +#define HPMLC_R2_FERR 0x02 +#define HPMLC_R2_FOF 0x04 -#define HPMLC_W2_TEST 0x01 -#define HPMLC_W2_IPF 0x04 +#define HPMLC_W2_TEST 0x01 +#define HPMLC_W2_IPF 0x04 -#define HPMLC_R3_INT 0x01 -#define HPMLC_R3_NMI 0x02 -#define HPMLC_R3_LERR 0x04 +#define HPMLC_R3_INT 0x01 +#define HPMLC_R3_NMI 0x02 +#define HPMLC_R3_LERR 0x04 -#define HPMLC_W3_APE 0x02 +#define HPMLC_W3_APE 0x02 // commands -#define HPHIL_IFC 0x00 // Interface Clear -#define HPHIL_EPT 0x01 // Enter Pass-Thru Mode -#define HPHIL_ELB 0x02 // Enter Loop-Back Mode -#define HPHIL_IDD 0x03 // Identify and Describe -#define HPHIL_DSR 0x04 // Device Soft Reset -#define HPHIL_PST 0x05 // Perform Self Test -#define HPHIL_RRG 0x06 // Read Register -#define HPHIL_WRG 0x07 // Write Register -#define HPHIL_ACF 0x08 // Auto Configure [08..0f] -#define HPHIL_POL 0x10 // Poll [10..1f] -#define HPHIL_RPL 0x20 // RePoll [20..2f] -#define HPHIL_RNM 0x30 // Report Name -#define HPHIL_RST 0x31 // Report Status -#define HPHIL_EXD 0x32 // Extended Describe -#define HPHIL_RSC 0x33 // Report Security Code -#define HPHIL_DKA 0x3D // Disable Keyswitch AutoRepeat -#define HPHIL_EK1 0x3E // Enable Keyswitch AutoRepeat 30cps -#define HPHIL_EK2 0x3F // Enable Keyswitch AutoRepeat 60cps -#define HPHIL_PR1 0x40 // Prompt 1..7 [40..46] -#define HPHIL_PRM 0x47 // Prompt (General Purpose) -#define HPHIL_AK1 0x48 // Acknowledge 1..7 [40..46] -#define HPHIL_ACK 0x4F // Acknowledge (General Purpose) -#define HPHIL_RIO 0xFA // Register I/O Error -#define HPHIL_SHR 0xFB // System Hard Reset -#define HPHIL_TER 0xFC // Transmission Error -#define HPHIL_CAE 0xFD // Configuration Address Error -#define HPHIL_DHR 0xFE // Device Hard Reset +#define HPHIL_IFC 0x00 // Interface Clear +#define HPHIL_EPT 0x01 // Enter Pass-Thru Mode +#define HPHIL_ELB 0x02 // Enter Loop-Back Mode +#define HPHIL_IDD 0x03 // Identify and Describe +#define HPHIL_DSR 0x04 // Device Soft Reset +#define HPHIL_PST 0x05 // Perform Self Test +#define HPHIL_RRG 0x06 // Read Register +#define HPHIL_WRG 0x07 // Write Register +#define HPHIL_ACF 0x08 // Auto Configure [08..0f] +#define HPHIL_POL 0x10 // Poll [10..1f] +#define HPHIL_RPL 0x20 // RePoll [20..2f] +#define HPHIL_RNM 0x30 // Report Name +#define HPHIL_RST 0x31 // Report Status +#define HPHIL_EXD 0x32 // Extended Describe +#define HPHIL_RSC 0x33 // Report Security Code +#define HPHIL_DKA 0x3D // Disable Keyswitch AutoRepeat +#define HPHIL_EK1 0x3E // Enable Keyswitch AutoRepeat 30cps +#define HPHIL_EK2 0x3F // Enable Keyswitch AutoRepeat 60cps +#define HPHIL_PR1 0x40 // Prompt 1..7 [40..46] +#define HPHIL_PRM 0x47 // Prompt (General Purpose) +#define HPHIL_AK1 0x48 // Acknowledge 1..7 [40..46] +#define HPHIL_ACK 0x4F // Acknowledge (General Purpose) +#define HPHIL_RIO 0xFA // Register I/O Error +#define HPHIL_SHR 0xFB // System Hard Reset +#define HPHIL_TER 0xFC // Transmission Error +#define HPHIL_CAE 0xFD // Configuration Address Error +#define HPHIL_DHR 0xFE // Device Hard Reset /* * init sequnce (p. 4-13) |