diff options
author | couriersud <couriersud@gmx.org> | 2019-03-31 12:32:22 +0200 |
---|---|---|
committer | couriersud <couriersud@gmx.org> | 2019-03-31 22:34:06 +0200 |
commit | 980dbcc69342e436f1097aa4b0bd4bac8542f79f (patch) | |
tree | 8c5796db2a959094120775ff83dd386188e7b4fb /nl_examples | |
parent | b8a104748ecd3ebe0d30038c78225b3a027aa225 (diff) |
Netlist: Add global parameter to disable semi-conductor capacitance
modelling. [Couriersud]
Added global NETLIST.DEFAULT_MOS_CAPMODEL parameter. Setting this to
zero disables using capitance modelling in mos models.
On a per mos device basis this can be achieved by adding CAPMODEL=0 to
the model definition, e.g. MOSFET(X, "NMOS(CAPMODEL=0)")
Improve MOSFET convergence by using log-stepping.
Diffstat (limited to 'nl_examples')
-rw-r--r-- | nl_examples/cmos_inverter_clk.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/nl_examples/cmos_inverter_clk.cpp b/nl_examples/cmos_inverter_clk.cpp index e869a478a6c..09064a59d19 100644 --- a/nl_examples/cmos_inverter_clk.cpp +++ b/nl_examples/cmos_inverter_clk.cpp @@ -19,7 +19,7 @@ NETLIST_START(cmos_inverter_clk) //SOLVER(Solver, 100000000000) PARAM(Solver.ACCURACY, 1e-7 ) PARAM(Solver.NR_LOOPS, 500000) - PARAM(Solver.DYNAMIC_TS, 1) + PARAM(Solver.DYNAMIC_TS, 0) PARAM(Solver.DYNAMIC_LTE, 1e-5) PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-8) ANALOG_INPUT(V5, 5) @@ -28,6 +28,7 @@ NETLIST_START(cmos_inverter_clk) #if (USE_CLOCK) CLOCK(V, 5000) + PARAM(NETLIST.DEFAULT_MOS_CAPMODEL, 0) // Disable capacitance modeling //CLOCK(V, 500000) #else VS(V, 5) |