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author | 2015-07-20 08:11:41 +0200 | |
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committer | 2015-07-20 08:11:41 +0200 | |
commit | 4bcb0c13f50ddb1cd3fd0341b4bb31d9c3c7fc7a (patch) | |
tree | 55eccacfca0e69435d0d4e6615205310ca11f271 /nl_examples/vs_cs.c | |
parent | d132946c6f45aa8d271c6180e86f72dd08243048 (diff) | |
parent | 229785f695b26c702c8490792611f59d0366a933 (diff) |
Merge pull request #5 from mamedev/master
Sync to base master
Diffstat (limited to 'nl_examples/vs_cs.c')
-rw-r--r-- | nl_examples/vs_cs.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/nl_examples/vs_cs.c b/nl_examples/vs_cs.c new file mode 100644 index 00000000000..4e6bb9615fe --- /dev/null +++ b/nl_examples/vs_cs.c @@ -0,0 +1,50 @@ +/* + * vs_cs.c + * + * Voltage and current source test + * + */ + +#include "netlist/devices/net_lib.h" + +NETLIST_START(rc) + + /* + * delay circuit + * + */ + + /* Standard stuff */ + + SOLVER(Solver, 48000) + PARAM(Solver.ACCURACY, 1e-6) + CLOCK(clk, 20000) + + /* Voltage source. Inner resistance will make clock visible */ + + RES(R1, 1000) + VS(VS1, 1) + NET_C(R1.1, clk) + NET_C(R1.2, VS1.P) + NET_C(GND, VS1.N) + + /* Current source. Current flows from "+" to "-", thus for a source we + * need negative current + */ + + RES(R2, 1000) + RES(R3, 1000) + CS(CS1, -0.001) + NET_C(CS1.P, R2.1) + NET_C(R2.2, R3.1) + NET_C(GND, CS1.N, R3.2) + + CAP(C1, CAP_U(1)) + NET_C(C1.1, R3.1) + NET_C(C1.2, R3.2) + + + LOG(tt, VS1.P) + LOG(tx, R2.2) + +NETLIST_END() |