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author couriersud <couriersud@gmx.org>2019-03-25 21:34:24 +0100
committer couriersud <couriersud@gmx.org>2019-03-25 21:45:37 +0100
commit39a7c420b1a956cfb680481077ed19f6315c6d37 (patch)
tree966378b573dcd8c08ac9e25000ef60c6dcb0ee39 /nl_examples/cmos_inverter.cpp
parenta105f9f456636c1de7396d5a79ad40c2237f6591 (diff)
netlist: add MOSFET model. [Couriersud]
- added MOSFET model. Currently capacitances are not modelled. This is a 3-pin model (Bulk connected to Source) with provisions to extend it to 4-pin at a later stage. - Add a capacitor generic model which is charge conserving. Switch netlist to use this model instead of constant capacity model. - Start putting constants into a central place. Please expect minor timing differences due to a different numerical path. The cmos inverter example illustrates the analog implementation of a cmos inverter gate. These were used a lot back in the 70s/80s to generate sinus waves. The model should also be able to better emulate 4066 analog switches. The addition of a relatively simple capacitor model is planned at a later stage. Expect everything from the MOSFET model at the current stage. Wrong results as well as convergence issues and crashes.
Diffstat (limited to 'nl_examples/cmos_inverter.cpp')
-rw-r--r--nl_examples/cmos_inverter.cpp42
1 files changed, 42 insertions, 0 deletions
diff --git a/nl_examples/cmos_inverter.cpp b/nl_examples/cmos_inverter.cpp
new file mode 100644
index 00000000000..e0936bfd3bc
--- /dev/null
+++ b/nl_examples/cmos_inverter.cpp
@@ -0,0 +1,42 @@
+// license:GPL-2.0+
+// copyright-holders:Couriersud
+/*
+ * bjt.c
+ *
+ */
+
+
+#include "netlist/devices/net_lib.h"
+#include "netlist/analog/nld_twoterm.h"
+
+NETLIST_START(cmos_inverter)
+ /* Standard stuff */
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-7)
+ PARAM(Solver.NR_LOOPS, 5000)
+ PARAM(Solver.METHOD, "MAT_CR")
+ ANALOG_INPUT(V5, 5)
+
+ VS(IN, 5)
+ PARAM(IN.FUNC, "T 5 *")
+
+ MOSFET(P, "PMOS(VTO=-1.0 KP=2e-3 LAMBDA=2E-2)")
+ MOSFET(M, "NMOS(VTO=1.0 KP=2e-3 LAMBDA=2E-2)")
+
+ NET_C(P.S, V5)
+ NET_C(P.D, M.D)
+ NET_C(GND, M.S, IN.N)
+
+ NET_C(IN.P, M.G, P.G)
+
+ // capacitance over D - S
+#if 0
+ CAP(C, CAP_N(1))
+ NET_C(M.D, C.1)
+ NET_C(M.S, C.2)
+#endif
+ LOG(log_G, M.G)
+ LOG(log_D, M.D)
+
+NETLIST_END()