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author MetalliC <0vetal0@gmail.com>2019-12-22 15:48:43 +0200
committer MetalliC <0vetal0@gmail.com>2019-12-22 15:48:43 +0200
commitf1adf2d106fd86e915b2355843e27b18e5f055ba (patch)
tree4ce946571121d20beff2013266ad3036ea1d0ce6
parenta61bd9e337329d3bcaf4355e57a1d6a18ca6f1c4 (diff)
sh3: handle INTEVT register
-rw-r--r--src/devices/cpu/sh/sh3comn.cpp10
-rw-r--r--src/devices/cpu/sh/sh3comn.h2
-rw-r--r--src/devices/cpu/sh/sh4comn.cpp50
3 files changed, 35 insertions, 27 deletions
diff --git a/src/devices/cpu/sh/sh3comn.cpp b/src/devices/cpu/sh/sh3comn.cpp
index 6871a1aef01..36c951840d4 100644
--- a/src/devices/cpu/sh/sh3comn.cpp
+++ b/src/devices/cpu/sh/sh3comn.cpp
@@ -123,10 +123,12 @@ READ32_MEMBER( sh3_base_device::sh3_internal_high_r )
return m_sh3internal_upper[offset];
case SH3_INTEVT_ADDR:
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
- fatalerror("INTEVT unsupported on SH3\n");
- // never executed
- //return m_sh3internal_upper[offset];
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
+ return m_sh3internal_upper[offset];
+
+ case SH3_SCSSR_ADDR:
+ // hack until SCI is not implemented
+ return 0x84<<24;
default:
diff --git a/src/devices/cpu/sh/sh3comn.h b/src/devices/cpu/sh/sh3comn.h
index 241035b993e..30f8e59ab68 100644
--- a/src/devices/cpu/sh/sh3comn.h
+++ b/src/devices/cpu/sh/sh3comn.h
@@ -78,6 +78,8 @@
#define SH3_ICR0_IPRA_ADDR ((0xfffffee0 - SH3_UPPER_REGBASE)/4)
#define SH3_IPRB_ADDR ((0xfffffee4 - SH3_UPPER_REGBASE)/4)
+#define SH3_SCSSR_ADDR ((0xfffffe88 - SH3_UPPER_REGBASE)/4)
+
#define SH3_TOCR_TSTR_ADDR ((0xfffffe90 - SH3_UPPER_REGBASE)/4)
#define SH3_TCOR0_ADDR ((0xfffffe94 - SH3_UPPER_REGBASE)/4)
#define SH3_TCNT0_ADDR ((0xfffffe98 - SH3_UPPER_REGBASE)/4)
diff --git a/src/devices/cpu/sh/sh4comn.cpp b/src/devices/cpu/sh/sh4comn.cpp
index 8c3e8cbc82c..4eaa267c31e 100644
--- a/src/devices/cpu/sh/sh4comn.cpp
+++ b/src/devices/cpu/sh/sh4comn.cpp
@@ -147,7 +147,7 @@ static const int exception_codes[] =
static const int sh3_intevt2_exception_codes[] =
{ 0x000, /* Power-on Reset */
- -1, /* Manual Reset */
+ 0x020, /* Manual Reset */
-1, /* H-UDI Reset */
-1, /* Inst TLB Multiple Hit */
-1, /* Data TLB Multiple Hit */
@@ -169,26 +169,26 @@ static const int sh3_intevt2_exception_codes[] =
-1, /* FPU Exception */
-1, /* Initial Page Write exception */
- -1, /* Unconditional TRAP */
+ 0x160, /* Unconditional TRAP */
-1, /* User break After Instruction */
- -1, /* NMI */ /* SH4_INTC_NMI=23 represents this location in this list.. */
-
- -1, /* EX Irq 0 */
- -1, /* 1 */
- -1, /* 2 */
- -1, /* 3 */
- -1, /* 4 */
- -1, /* 5 */
- -1, /* 6 */
- -1, /* 7 */
- -1, /* 8 */
- -1, /* 9 */
- -1, /* A */
- -1, /* B */
- -1, /* C */
- -1, /* D */
- -1, /* E */
+ 0x1C0, /* NMI */ /* SH4_INTC_NMI=23 represents this location in this list.. */
+
+ 0x200, /* EX Irq 0 */
+ 0x220, /* 1 */
+ 0x240, /* 2 */
+ 0x260, /* 3 */
+ 0x280, /* 4 */
+ 0x2A0, /* 5 */
+ 0x2C0, /* 6 */
+ 0x2E0, /* 7 */
+ 0x300, /* 8 */
+ 0x320, /* 9 */
+ 0x340, /* A */
+ 0x360, /* B */
+ 0x380, /* C */
+ 0x3A0, /* D */
+ 0x3C0, /* E */
0x600, /* SH4_INTC_IRL0 */
0x620, /* SH4_INTC_IRL1 */
@@ -198,10 +198,10 @@ static const int sh3_intevt2_exception_codes[] =
-1, /* HUDI */
-1, /* SH4_INTC_GPOI */
- -1, /* SH4_INTC_DMTE0 */
- -1, /* SH4_INTC_DMTE1 */
- -1, /* SH4_INTC_DMTE2 */
- -1, /* SH4_INTC_DMTE3 */
+ 0x800, /* SH4_INTC_DMTE0 */
+ 0x820, /* SH4_INTC_DMTE1 */
+ 0x840, /* SH4_INTC_DMTE2 */
+ 0x860, /* SH4_INTC_DMTE3 */
-1, /* SH4_INTC_DMTE4 */
-1, /* SH4_INTC_DMTE5 */
@@ -458,6 +458,10 @@ void sh34_base_device::sh4_exception(const char *message, int exception) // hand
m_sh3internal_lower[INTEVT2] = sh3_intevt2_exception_codes[exception];
m_sh3internal_upper[SH3_EXPEVT_ADDR] = exception_codes[exception];
+ if (sh3_intevt2_exception_codes[exception] >= 0x600)
+ m_sh3internal_upper[SH3_INTEVT_ADDR] = 0x3E0 - ((m_exception_priority[exception] >> 8) & 255) * 0x20;
+ else
+ m_sh3internal_upper[SH3_INTEVT_ADDR] = sh3_intevt2_exception_codes[exception];
LOG(("SH-3 '%s' interrupt exception #%d after [%s]\n", tag(), exception, message));