diff options
| author | 2025-10-19 10:34:47 +1300 | |
|---|---|---|
| committer | 2025-10-19 10:34:47 +1300 | |
| commit | ea74372dd8badc286f8ca4d9b7ecfa3a30dcf4d2 (patch) | |
| tree | d6de02c5a51a7cbfd1e1ed23d108f96927d73d32 | |
| parent | ef1f82b968de05f83125562752b801126a278b9f (diff) | |
ngen: prevent floppy/HD module from being used in 80386 based systems, it is not compatible with these.
| -rw-r--r-- | src/mame/skeleton/ngen.cpp | 83 |
1 files changed, 71 insertions, 12 deletions
diff --git a/src/mame/skeleton/ngen.cpp b/src/mame/skeleton/ngen.cpp index 31bee747868..2df66b407ff 100644 --- a/src/mame/skeleton/ngen.cpp +++ b/src/mame/skeleton/ngen.cpp @@ -178,6 +178,10 @@ private: void b38_keyboard_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); uint16_t b38_crtc_r(offs_t offset, uint16_t mem_mask = ~0); void b38_crtc_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); + void periph141_w(offs_t offset, uint16_t data, uint16_t mem_mask); + uint16_t periph141_r(offs_t offset, uint16_t mem_mask); + void dma_bank_w(offs_t offset, uint16_t data, uint16_t mem_mask); + uint16_t dma_bank_r(offs_t offset, uint16_t mem_mask); void ngen_io(address_map &map) ATTR_COLD; void ngen_mem(address_map &map) ATTR_COLD; @@ -291,6 +295,8 @@ void ngen_state::cpu_peripheral_cb(offs_t offset, uint16_t data, uint16_t mem_ma // Largely guesswork at this stage void ngen_state::peripheral_w(offs_t offset, uint16_t data, uint16_t mem_mask) { +// if(offset < 0x140) +// logerror("Peripheral write %04x data %04x mask %04x\n",offset,data,mem_mask); switch(offset) { case 0x00: @@ -316,8 +322,7 @@ void ngen_state::peripheral_w(offs_t offset, uint16_t data, uint16_t mem_mask) case 0x81: case 0x82: case 0x83: - if(ACCESSING_BITS_0_7) - m_dma_offset[offset-0x80] = data & 0xff; + dma_bank_w(offset-0x80,data & 0xff, 0xffff); break; case 0xc0: // X-Bus modules reset m_xbus_current = 0; @@ -391,8 +396,7 @@ uint16_t ngen_state::peripheral_r(offs_t offset, uint16_t mem_mask) case 0x81: case 0x82: case 0x83: - if(ACCESSING_BITS_0_7) - ret = m_dma_offset[offset-0x80] & 0xff; + ret = dma_bank_r(offset, 0xffff); break; case 0x10c: if(ACCESSING_BITS_0_7) @@ -429,8 +433,8 @@ uint16_t ngen_state::peripheral_r(offs_t offset, uint16_t mem_mask) case 0x1a0: // I/O control register? ret = m_control; // end of DMA transfer? (maybe a per-channel EOP?) Bit 6 is set during a transfer? break; -// default: -// logerror("Unknown 80186 peripheral read offset %04x mask %04x returning %04x\n",offset,mem_mask,ret); + default: + logerror("Unknown 80186 peripheral read offset %04x mask %04x returning %04x\n",offset,mem_mask,ret); } return ret; } @@ -452,8 +456,11 @@ void ngen_state::xbus_w(uint16_t data) address_space& io = cpu->space(AS_IO); switch(m_xbus_current) { - case 0x00: // Floppy/Hard disk module - io.install_readwrite_handler(addr,addr+0xff, read16s_delegate(*this, FUNC(ngen_state::hfd_r)), write16s_delegate(*this, FUNC(ngen_state::hfd_w)), 0xffffffff); + case 0x00: // Floppy/Hard disk module - only works with the 80186 NGEN + if(m_maincpu) + io.install_readwrite_handler(addr,addr+0xff, read16s_delegate(*this, FUNC(ngen_state::hfd_r)), write16s_delegate(*this, FUNC(ngen_state::hfd_w)), 0xffffffff); + else + cpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero); // reached end of the modules break; default: cpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero); // reached end of the modules @@ -468,7 +475,22 @@ void ngen_state::xbus_w(uint16_t data) // bit 6, I think, indicates a bootable device // Known module IDs: // 0x1070 - Floppy/Hard disk module +// 0x2fxx - PC001 // 0x3141 - QIC Tape module +// 0x32xx - 0x33xx - "phone" +// 0x34xx - 0x35xx - ethernet +// 0x38xx - monochrome gtaphics +// 0x39xx - colour graphics +// 0x3cxx - 0x3fxx - GC003 +// 0x44xx - GC102 +// 0x50xx - 0x5fxx - GCX04 +// 0x84xx - Unisys QIC +// 0xc3xx - Unisys EN3 +// 0xc4xx - Unisys TR2 +// 0xc5xx - Unisys ID2 +// 0xc8xx - ISDN +// 0xc9xx - SuperGen Ethernet + uint16_t ngen_state::xbus_r() { uint16_t ret = 0xffff; @@ -476,7 +498,13 @@ uint16_t ngen_state::xbus_r() switch(m_xbus_current) { case 0x00: - ret = 0x1070; // Floppy/Hard disk module + if(m_maincpu) + ret = 0x1070; // Floppy/Hard disk module - 80186 NGEN only + else + { + m_i386cpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero); + ret = 0x0080; + } break; default: if(m_maincpu) @@ -782,6 +810,19 @@ uint8_t ngen_state::irq_cb() return m_pic->acknowledge(); } +void ngen_state::dma_bank_w(offs_t offset, uint16_t data, uint16_t mem_mask) +{ + if(ACCESSING_BITS_0_7) + m_dma_offset[offset] = data & 0xff; +} + +uint16_t ngen_state::dma_bank_r(offs_t offset, uint16_t mem_mask) +{ + if(ACCESSING_BITS_0_7) + return m_dma_offset[offset] & 0xff; + return 0xff; +} + uint16_t ngen_state::b38_keyboard_r(offs_t offset, uint16_t mem_mask) { uint8_t ret = 0; @@ -816,11 +857,11 @@ uint16_t ngen_state::b38_crtc_r(offs_t offset, uint16_t mem_mask) { case 0: if(ACCESSING_BITS_0_7) - ret = m_crtc->register_r(); + ret = m_crtc->status_r(); break; case 1: if(ACCESSING_BITS_0_7) - ret = m_viduart->data_r(); + ret = m_crtc->register_r(); break; } return ret; @@ -841,6 +882,17 @@ void ngen_state::b38_crtc_w(offs_t offset, uint16_t data, uint16_t mem_mask) } } +void ngen_state::periph141_w(offs_t offset, uint16_t data, uint16_t mem_mask) +{ + // bit 1 enables speaker? + COMBINE_DATA(&m_periph141); +} + +uint16_t ngen_state::periph141_r(offs_t offset, uint16_t mem_mask) +{ + return m_periph141; +} + void ngen_state::machine_start() { memory_share* vidshare = memshare("vram"); @@ -910,9 +962,16 @@ void ngen_state::ngen386i_mem(address_map &map) void ngen_state::ngen386_io(address_map &map) { map(0x0000, 0x0001).rw(FUNC(ngen_state::xbus_r), FUNC(ngen_state::xbus_w)); -// map(0xf800, 0xfeff).rw(FUNC(ngen_state::peripheral_r), FUNC(ngen_state::peripheral_w)); +// map(0xf800, 0xfeff).rw(FUNC(ngen_state::peripheral_r), FUNC(ngen_state::peripheral_w)).umask16(0x00ff); +// map(0xf904, 0xf907).rw("pit",FUNC(pit8254_device::read), FUNC(pit8254_device::write)).umask32(0x00ff00ff); + map(0xf800, 0xf81f).rw("dmac",FUNC(am9517a_device::read), FUNC(am9517a_device::write)).umask32(0x00ff00ff); + map(0xf828, 0xf83f).rw(FUNC(ngen_state::dma_bank_r), FUNC(ngen_state::dma_bank_w)).umask32(0x0000ffff); + map(0xfc24, 0xfc27).rw("pic",FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask32(0x00ff00ff); + map(0xfc34, 0xfc3f).rw("pit",FUNC(pit8254_device::read), FUNC(pit8254_device::write)).umask32(0x00ff00ff); + map(0xfd02, 0xfd03).rw(FUNC(ngen_state::periph141_r), FUNC(ngen_state::periph141_w)); map(0xfd08, 0xfd0b).rw(FUNC(ngen_state::b38_crtc_r), FUNC(ngen_state::b38_crtc_w)); map(0xfd0c, 0xfd0f).rw(FUNC(ngen_state::b38_keyboard_r), FUNC(ngen_state::b38_keyboard_w)); + //map(0xfe40, 0xfe4f).rw("videouart", FUNC(i8251_device::read), FUNC(i8251_device::write)).umask32(0x00ff00ff); } static INPUT_PORTS_START( ngen ) |
