diff options
author | 2018-04-12 18:42:17 +0700 | |
---|---|---|
committer | 2018-04-12 23:00:42 +1000 | |
commit | e50bff084dcd23d75b3543ba23d6de6a1966225c (patch) | |
tree | 3cf4bb27c8f73223bf0db0a0ff0e6d79dc66e586 | |
parent | 7cf95e857a95152044bf8cbff4492c76ad101b36 (diff) |
interpro: minor changes (nw)
* debugger address translation
* documentation edits
-rw-r--r-- | src/devices/bus/interpro/sr/sr.h | 2 | ||||
-rw-r--r-- | src/devices/cpu/clipper/clipper.cpp | 9 | ||||
-rw-r--r-- | src/devices/cpu/clipper/clipper.h | 1 | ||||
-rw-r--r-- | src/mame/drivers/interpro.cpp | 39 | ||||
-rw-r--r-- | src/mame/machine/cammu.cpp | 21 | ||||
-rw-r--r-- | src/mame/machine/cammu.h | 3 |
6 files changed, 57 insertions, 18 deletions
diff --git a/src/devices/bus/interpro/sr/sr.h b/src/devices/bus/interpro/sr/sr.h index c4a03c42aa5..9be58c9ac12 100644 --- a/src/devices/bus/interpro/sr/sr.h +++ b/src/devices/bus/interpro/sr/sr.h @@ -118,7 +118,7 @@ public: virtual ~device_sr_card_interface(); void set_sr_device(); - void irq(int status); + void irq(int state); // inline configuration void set_sr_tag(const char *tag, const char *slot_tag) { m_sr_tag = tag; m_sr_slot_tag = slot_tag; } diff --git a/src/devices/cpu/clipper/clipper.cpp b/src/devices/cpu/clipper/clipper.cpp index ef9cf68d344..ee77197e967 100644 --- a/src/devices/cpu/clipper/clipper.cpp +++ b/src/devices/cpu/clipper/clipper.cpp @@ -326,6 +326,11 @@ device_memory_interface::space_config_vector clipper_device::memory_space_config }; } +bool clipper_device::memory_translate(int spacenum, int intention, offs_t &address) +{ + return ((intention & TRANSLATE_TYPE_MASK) == TRANSLATE_FETCH ? get_icammu() : get_dcammu()).memory_translate(m_ssw, spacenum, intention, address); +} + WRITE16_MEMBER(clipper_device::set_exception) { LOGMASKED(LOG_EXCEPTION, "external exception 0x%04x triggered\n", data); @@ -1495,6 +1500,8 @@ u32 clipper_device::intrap(const u16 vector, const u32 old_pc) const u32 old_psw = m_psw; u32 new_pc = 0, new_ssw = 0; + debugger_exception_hook(vector); + // clear ssw bits to enable supervisor memory access m_ssw &= ~(SSW_U | SSW_K | SSW_UU | SSW_KU); @@ -1578,6 +1585,8 @@ u32 clipper_c400_device::intrap(const u16 vector, const u32 old_pc) const u32 old_psw = m_psw; u32 new_pc = 0, new_ssw = 0; + debugger_exception_hook(vector); + // clear ssw bits to enable supervisor memory access m_ssw &= ~(SSW_U | SSW_K | SSW_UU | SSW_KU); diff --git a/src/devices/cpu/clipper/clipper.h b/src/devices/cpu/clipper/clipper.h index 500a3fa046e..995ca53d7f7 100644 --- a/src/devices/cpu/clipper/clipper.h +++ b/src/devices/cpu/clipper/clipper.h @@ -161,6 +161,7 @@ protected: // device_memory_interface overrides virtual space_config_vector memory_space_config() const override; + virtual bool memory_translate(int spacenum, int intention, offs_t &address) override; // device_state_interface overrides virtual void state_string_export(const device_state_entry &entry, std::string &str) const override; diff --git a/src/mame/drivers/interpro.cpp b/src/mame/drivers/interpro.cpp index d517cfbf9f9..a7126aa3525 100644 --- a/src/mame/drivers/interpro.cpp +++ b/src/mame/drivers/interpro.cpp @@ -6,7 +6,7 @@ * UNIX workstations. * * The first systems were built using the original C100 CLIPPER CPU, and used - * an additional Intel 80186 as an I/O processor, later moving to a C300 with + * an additional Intel 80186 as an I/O processor, later upgraded to a C300 and * 80386 IOP. Around 1990, the CLIPPER became fast enough to obviate the need * for the separate I/O processor, and systems from that point used the main * CPU for both compute and I/O, along with some custom ASICs. @@ -16,10 +16,11 @@ * * Year Family Models CPU * 1986 amethyst 32C/100/200 C100 (80186 IOP) - * 1988 topaz 300/3000/4000/5000 C300/C300Plus (80386 IOP) + * 300 C100 (80386 IOP) + * 1988 topaz 3000/4000/5000 C300/C300Plus (80386 IOP) * 1990 emerald 6000/6100/6200/6500 C300/C300Plus * 1990 turquoise 2000 C300 - * 1991 emerald? 6600 C4? + * 1991 emerald 6600 C4? * 1992 sapphire 2400/6400 C4T * 1993 sapphire 2500/2700/6700/6800 C4I * 1994 sapphire 2800 C4I @@ -28,12 +29,15 @@ * * Model Year CPU Performance Clock Family Bus * 6000 1990 C300 10 MIPS 40MHz emerald SRX - * 6100 1990 14 MIPS emerald IOI?, 6105 has 5-slot chassis - * 6500 C300+ emerald IOI, QWIC bus? + * 1991 12 MIPS + * 6100 1990 C300+? 14 MIPS emerald IOI, 12-slot + 1991 15.5 MIPS + * 6500 1990 C300+ 20 MIPS emerald IOI, QWIC bus?, 12-slot * 6200 1990 C300+ 14 MIPS 60MHz emerald * 1991 18 MIPS * 2000 1990 C300 12.5 MIPS 50MHz? turquoise CBUS - * 6600 1991 C400 40 MIPS emerald? IOI, SRX bus? + * 1991 16 MIPS + * 6600 1991 C400 40 MIPS emerald IOI, SRX bus? * 2400 1992 C4T 36 MIPS/33 SPECmarks 40MHz? sapphire CBUS * 6400 1992 C4T 36 MIPS/33 SPECmarks 40MHz sapphire SRX * 2700 1993 C400I 40.1 SPECmark89 sapphire 2 CBUS @@ -73,10 +77,12 @@ * GT 1990? 360k 2D vec/s (in a 2020) * EDGE-1 8 planes + 1 highlight plane, double buffered (6040) * EDGE-2 24 bit, 400k 2D vec/s, 350k 3D vec/s (6280) - * GT+ 760k 2D vec/s, 530k 3D vec/s (in a 2730) - * GTII 830k 2D vec/s, 640k 3D vec/s (in a 6750) + * GT+ 500k 2D vec/s, 300k 2D vec/s (in a 2430) + * 760k 2D vec/s, 530k 3D vec/s (in a 2730) + * GTII 800k 2D vec/s, 500k 3D vec/s (in a 6450) + * 830k 2D vec/s, 640k 3D vec/s (in a 6750) * 900k 2D vec/s, 700k 3D vec/s (in a 6850) - * EDGE II+ 50k Gouraud-shaded poly/s (in a 6780) + * EDGE II+ 600k 2D vec/s, 500k 3D vec/s, 50k shaded poly/s (in a 6480) * * GT graphics are also referred to in various places as Memory Mapped Graphics * or MMG. EDGE stands for Extensible Display Geometry Engine. @@ -94,7 +100,7 @@ * U39 Intel 82586 Ethernet controller * U40 Zilog 8530 SCC Keyboard and console serial controller * U41 Zilog 8530 SCC Serial controller for serial port 0 and 1 - * U42 Xilinix XC3020-50 Plotter control FPGA? + * U42 Xilinx XC3020-50 Plotter control FPGA? * U43 (MPRGM610C) Bitstream for XC3020? * U54 4.9152 MHz crystal Clock source for 8530s? * U55 20.0 MHz crystal @@ -111,7 +117,7 @@ * Ref Part Function * U31 Zilog Z85C30 SCC Keyboard and console serial controller * U32 Zilog Z85230 ESCC Serial controller for serial port 0 and 1 - * U34 Xilinix XC3020-50 Plotter control FPGA? + * U34 Xilinx XC3020-50 Plotter control FPGA? * U35 128 kB EPROM (MPRGW510B) Boot ROM * U43? (MPRGM610P) Bitstream for XC3020? * U44 Intel 82596SX-20 Ethernet controller @@ -137,7 +143,7 @@ * Ref Part Function * U31 Zilog Z85C30 SCC Keyboard and console serial controller * U32 Zilog Z85230 ESCC Serial controller for serial port 0 and 1 - * U34 Xilinix XC3020-70 Plotter control FPGA? + * U34 Xilinx XC3020-70 Plotter control FPGA? * U35 128 kB EPROM (MPRGZ530A) Boot ROM * U43? (MPRGM610P) Bitstream for XC3020? * U44 Intel 82596SX-20 Ethernet controller @@ -172,7 +178,7 @@ * SMT098B 6400 32-MHz Sapphire System Board * SMT127 6700 Series System Board MSMT1040A C4I: C4 CPU Rev 3 + C4 FPU Rev 3 + C4I CAMMU * SMT128 2700 Series System Board MSMT1040A C4I: C4 CPU Rev 3 + C4 FPU Rev 3 + C4I CAMMU - * SMT144 6800 Series System Board + * SMT144 6800 Series System Board integrated cpu? * SMT145 2800 Series System Board */ @@ -442,13 +448,14 @@ void sapphire_state::sapphire_io_map(address_map &map) map(0x00000000, 0x00001fff).m(m_mmu, FUNC(cammu_c4_device::map)); } -ADDRESS_MAP_START(interpro_state::interpro_boot_map) +void interpro_state::interpro_boot_map(address_map &map) +{ // FIXME: the real system may have some initial boot instructions in this boot // memory space which jump to the start of the boot eprom code, or there may // be some special address decoding logic for boot. For now, we fake it in the // CPU by hard-coding the start address to point at the eprom. - AM_RANGE(0x00000000, 0x00001fff) AM_RAM -ADDRESS_MAP_END + map(0x00000000, 0x00001fff).ram(); +} void turquoise_state::interpro_82586_map(address_map &map) { diff --git a/src/mame/machine/cammu.cpp b/src/mame/machine/cammu.cpp index 17ac438931b..c027d2d59e5 100644 --- a/src/mame/machine/cammu.cpp +++ b/src/mame/machine/cammu.cpp @@ -224,13 +224,32 @@ void cammu_device::set_spaces(std::vector<address_space *> spaces) std::copy(spaces.begin(), spaces.end(), std::begin(m_space)); } +bool cammu_device::memory_translate(const u32 ssw, const int spacenum, const int intention, offs_t &address) +{ + // translate the address + translated_t translated = translate_address(ssw, address, BYTE, + (intention & TRANSLATE_TYPE_MASK) == TRANSLATE_READ ? READ : + (intention & TRANSLATE_TYPE_MASK) == TRANSLATE_WRITE ? WRITE : + EXECUTE); + + // check that the requested space number matches the mapped space + if (translated.space != nullptr && translated.space->spacenum() == spacenum) + { + address = translated.address; + + return true; + } + + return false; +} + cammu_device::translated_t cammu_device::translate_address(const u32 ssw, const u32 virtual_address, const access_size size, const access_type mode) { // get effective user/supervisor mode const bool user = mode == EXECUTE ? ssw & SSW_U : ssw & (SSW_U | SSW_UU); // check for alignment faults - if (get_alignment() && !machine().side_effects_disabled()) + if (!machine().side_effects_disabled() && get_alignment()) { if ((mode == EXECUTE && (virtual_address & 0x1)) || (mode != EXECUTE && virtual_address & (size - 1))) { diff --git a/src/mame/machine/cammu.h b/src/mame/machine/cammu.h index a8f6a1d9330..5060fc96518 100644 --- a/src/mame/machine/cammu.h +++ b/src/mame/machine/cammu.h @@ -155,6 +155,9 @@ public: return false; } + // address translation for debugger + bool memory_translate(const u32 ssw, const int spacenum, const int intention, offs_t &address); + protected: cammu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); |