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author AJR <ajrhacker@users.noreply.github.com>2020-01-01 12:29:16 -0500
committer AJR <ajrhacker@users.noreply.github.com>2020-01-01 12:30:57 -0500
commite3da013733c63667a805bc85006b96a5e6ebdcff (patch)
tree5a3d05c0a89e0fd27cd68b8b67ed7b6f6e7912c7
parent2240929c28b8ce6a4758b1da368fbcf470de543d (diff)
pace, we32100: Notes (nw)
t11: Fix empty disassembler output for some invalid opcodes (nw)
-rw-r--r--src/devices/cpu/pace/pace.cpp10
-rw-r--r--src/devices/cpu/t11/t11dasm.cpp5
-rw-r--r--src/devices/cpu/we32000/we32100d.cpp3
3 files changed, 13 insertions, 5 deletions
diff --git a/src/devices/cpu/pace/pace.cpp b/src/devices/cpu/pace/pace.cpp
index bc0e6f5b62a..03b36312930 100644
--- a/src/devices/cpu/pace/pace.cpp
+++ b/src/devices/cpu/pace/pace.cpp
@@ -6,10 +6,12 @@
The IPC-16A PACE (Processing and Control Element) was one of the first
commercially available 16-bit microprocessors. It was a successor to
- the multiple-chip IMP-16 processor and implemented a similar four-
- accumulator architecture in a single PMOS LSI package using internal
- microcode. PACE requires two clock inputs with non-overlapping low
- phases and frequencies between 1.25 and 1.538 MHz.
+ the multiple-chip IMP-16 processor (itself loosely based on the Data
+ General Nova) and implemented a similar four-accumulator architecture
+ in a single PMOS LSI package using internal microcode. The two clock
+ inputs with non-overlapping low phases required by PACE may be
+ generated by the DP8302 STE (System Timing Element), which divides its
+ oscillator input by 2.
The standard machine cycle takes 4 clock periods (and the shortest
instructions take 4 cycles each), though cycles can be stretched by
diff --git a/src/devices/cpu/t11/t11dasm.cpp b/src/devices/cpu/t11/t11dasm.cpp
index 6300758aa73..536d811eff0 100644
--- a/src/devices/cpu/t11/t11dasm.cpp
+++ b/src/devices/cpu/t11/t11dasm.cpp
@@ -166,6 +166,9 @@ offs_t t11_disassembler::disassemble(std::ostream &stream, offs_t pc, const data
default: util::stream_format(stream, "Scc #%02o", lo & 15); break;
}
break;
+ default:
+ util::stream_format(stream, ".WORD %06o", op);
+ break;
}
break;
case 0000300:
@@ -522,6 +525,8 @@ offs_t t11_disassembler::disassemble(std::ostream &stream, offs_t pc, const data
util::stream_format(stream, "SUB %s,%s", ea1, ea2);
break;
+ // 17xxxx: floating point (not implemented on T-11)
+
default:
util::stream_format(stream, ".WORD %06o", op);
break;
diff --git a/src/devices/cpu/we32000/we32100d.cpp b/src/devices/cpu/we32000/we32100d.cpp
index a14cae7008a..955cbbd63d9 100644
--- a/src/devices/cpu/we32000/we32100d.cpp
+++ b/src/devices/cpu/we32000/we32100d.cpp
@@ -5,7 +5,8 @@
Disassembler for AT&T's WE32100 processor.
Operands are formatted similarly to AT&T's m32dis. Note that operand
- encoding is little-endian even though memory accesses are big-endian.
+ encoding is little-endian even though memory accesses are big-endian
+ (and must also be aligned).
***************************************************************************/