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author AJR <ajrhacker@users.noreply.github.com>2019-03-31 11:03:29 -0400
committer AJR <ajrhacker@users.noreply.github.com>2019-03-31 11:03:33 -0400
commitde8c9b94646186a0e5e922bbc585be4ae5acbfb8 (patch)
tree627dc9ea263293df7e075d7c3a030943cfa26eb2
parent652b654206445f91f323726c49084255b6fde9ac (diff)
aic6250: Preliminary, untested implementation of processor memory requests (nw)
-rw-r--r--src/devices/machine/aic6250.cpp110
1 files changed, 87 insertions, 23 deletions
diff --git a/src/devices/machine/aic6250.cpp b/src/devices/machine/aic6250.cpp
index adf90fe99b5..1e85bd571a4 100644
--- a/src/devices/machine/aic6250.cpp
+++ b/src/devices/machine/aic6250.cpp
@@ -21,7 +21,7 @@
*
* TODO
* - fix problems with ATN
- * - 16 bit DMA odd address start
+ * - 16 bit DMA odd address start and HBV/LBV selection
* - disconnect/reselect
* - phase checks
*/
@@ -408,7 +408,11 @@ void aic6250_device::control_reg_0_w(u8 data)
data & R07W_TARGET_MODE ? "target" : "initiator");
if (data & R07W_P_MEM_CYCLE_REQ)
- logerror("processor memory %s request not supported\n", data & R07W_P_MEM_RW ? "write" : "read");
+ {
+ LOGMASKED(LOG_DMA, "processor memory %s request initiated\n", data & R07W_P_MEM_RW ? "write" : "read");
+ m_status_reg_1 &= ~R08R_MEM_CYCLE_CMPL;
+ m_breq_cb(1);
+ }
m_control_reg_0 = data;
}
@@ -1015,49 +1019,109 @@ WRITE_LINE_MEMBER(aic6250_device::back_w)
m_breq_cb(0);
- if (m_dma_cntrl & R05W_TRANSFER_DIR)
- if (m_fifo.full() || m_dma_count < 8)
- m_state_timer->adjust(attotime::zero);
- else
- m_breq_cb(1);
- else
- if (m_fifo.empty())
- m_state_timer->adjust(attotime::zero);
+ if (!(m_control_reg_0 & R07W_P_MEM_CYCLE_REQ))
+ {
+ if (m_dma_cntrl & R05W_TRANSFER_DIR)
+ if (m_fifo.full() || m_dma_count < 8)
+ m_state_timer->adjust(attotime::zero);
+ else
+ m_breq_cb(1);
else
- m_breq_cb(1);
+ if (m_fifo.empty())
+ m_state_timer->adjust(attotime::zero);
+ else
+ m_breq_cb(1);
+ }
}
u8 aic6250_device::dma_r()
{
- u8 const data = m_fifo.dequeue();
+ if ((m_control_reg_0 & R07W_P_MEM_CYCLE_REQ) && (m_control_reg_0 & R07W_P_MEM_RW))
+ {
+ // 8-bit memory write cycle
+ u8 const data = m_memory_data;
- LOGMASKED(LOG_DMA, "dma_r 0x%02x\n", data);
+ LOGMASKED(LOG_DMA, "DMA 0x%02x from reg 0C\n", data);
- return data;
+ m_status_reg_1 |= R08R_MEM_CYCLE_CMPL;
+ m_control_reg_0 &= ~R07W_P_MEM_CYCLE_REQ;
+
+ return data;
+ }
+ else
+ {
+ u8 const data = m_fifo.dequeue();
+
+ LOGMASKED(LOG_DMA, "DMA 0x%02x from FIFO\n", data);
+
+ return data;
+ }
}
u16 aic6250_device::dma16_r()
{
- u16 data = m_fifo.dequeue();
+ if ((m_control_reg_0 & R07W_P_MEM_CYCLE_REQ) && (m_control_reg_0 & R07W_P_MEM_RW))
+ {
+ // 16-bit memory write cycle
+ u16 const data = m_memory_data | (u16(m_port_b_latch) << 8);
- data |= u16(m_fifo.dequeue()) << 8;
+ LOGMASKED(LOG_DMA, "DMA 0x%04x from reg 0C and 0E\n", data);
- LOGMASKED(LOG_DMA, "dma16_r 0x%04x\n", data);
+ m_status_reg_1 |= R08R_MEM_CYCLE_CMPL;
+ m_control_reg_0 &= ~R07W_P_MEM_CYCLE_REQ;
- return data;
+ return data;
+ }
+ else
+ {
+ u16 data = m_fifo.dequeue();
+
+ data |= u16(m_fifo.dequeue()) << 8;
+
+ LOGMASKED(LOG_DMA, "dma16_r 0x%04x\n", data);
+
+ return data;
+ }
}
void aic6250_device::dma_w(u8 data)
{
- LOGMASKED(LOG_DMA, "dma_w 0x%02x\n", data);
+ if ((m_control_reg_0 & R07W_P_MEM_CYCLE_REQ) && !(m_control_reg_0 & R07W_P_MEM_RW))
+ {
+ // 8-bit memory read cycle
+ LOGMASKED(LOG_DMA, "DMA 0x%02x to reg 0C\n", data);
+
+ m_status_reg_1 |= R08R_MEM_CYCLE_CMPL;
+ m_control_reg_0 &= ~R07W_P_MEM_CYCLE_REQ;
- m_fifo.enqueue(data);
+ m_memory_data = data;
+ }
+ else
+ {
+ LOGMASKED(LOG_DMA, "DMA 0x%02x to FIFO\n", data);
+
+ m_fifo.enqueue(data);
+ }
}
void aic6250_device::dma16_w(u16 data)
{
- LOGMASKED(LOG_DMA, "dma16_w 0x%04x\n", data);
+ if ((m_control_reg_0 & R07W_P_MEM_CYCLE_REQ) && !(m_control_reg_0 & R07W_P_MEM_RW))
+ {
+ // 16-bit memory read cycle
+ LOGMASKED(LOG_DMA, "DMA 0x%04x to reg 0C and 0E\n", data);
+
+ m_status_reg_1 |= R08R_MEM_CYCLE_CMPL;
+ m_control_reg_0 &= ~R07W_P_MEM_CYCLE_REQ;
- m_fifo.enqueue(data);
- m_fifo.enqueue(data >> 8);
+ m_memory_data = data;
+ m_port_b_latch = data >> 8;
+ }
+ else
+ {
+ LOGMASKED(LOG_DMA, "DMA 0x%04x to FIFO\n", data);
+
+ m_fifo.enqueue(data);
+ m_fifo.enqueue(data >> 8);
+ }
}