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author AJR <ajrhacker@users.noreply.github.com>2017-05-26 16:31:56 -0400
committer AJR <ajrhacker@users.noreply.github.com>2017-05-26 17:08:54 -0400
commitd1fb75b2e7f6e5fb24d9df97e8fe6c7aec1e6b30 (patch)
treeaef650646fd36f40956b4e2fcfa8fda51f4bd2cd
parent2b7d87317bca96353a23e7b178c92fed432b30af (diff)
Quick and dirty split of most MC6801/MC6803/HD63701 features from base M6800 class (nw)
The code remains generally archaic and awful and in need of a sweeping rewrite. At least one static variable is no more.
-rw-r--r--scripts/src/cpu.lua2
-rw-r--r--src/devices/bus/adamnet/ddp.h2
-rw-r--r--src/devices/bus/adamnet/fdc.h2
-rw-r--r--src/devices/bus/adamnet/kb.h2
-rw-r--r--src/devices/bus/adamnet/printer.h2
-rw-r--r--src/devices/bus/adamnet/spi.h2
-rw-r--r--src/devices/bus/epson_sio/pf10.h2
-rw-r--r--src/devices/cpu/m6800/6800ops.hxx6
-rw-r--r--src/devices/cpu/m6800/6800tbl.hxx70
-rw-r--r--src/devices/cpu/m6800/m6800.cpp1211
-rw-r--r--src/devices/cpu/m6800/m6800.h190
-rw-r--r--src/devices/cpu/m6800/m6801.cpp1296
-rw-r--r--src/devices/cpu/m6800/m6801.h219
-rw-r--r--src/devices/machine/mpu401.h2
-rw-r--r--src/mame/audio/irem.cpp2
-rw-r--r--src/mame/drivers/acesp.cpp2
-rw-r--r--src/mame/drivers/apricotp.cpp2
-rw-r--r--src/mame/drivers/banctec.cpp2
-rw-r--r--src/mame/drivers/baraduke.cpp2
-rw-r--r--src/mame/drivers/bublbobl.cpp2
-rw-r--r--src/mame/drivers/by6803.cpp2
-rw-r--r--src/mame/drivers/by68701.cpp2
-rw-r--r--src/mame/drivers/byvid.cpp2
-rw-r--r--src/mame/drivers/canon_s80.cpp2
-rw-r--r--src/mame/drivers/castle.cpp2
-rw-r--r--src/mame/drivers/ddragon.cpp2
-rw-r--r--src/mame/drivers/itech32.cpp2
-rw-r--r--src/mame/drivers/kncljoe.cpp2
-rw-r--r--src/mame/drivers/ltd.cpp2
-rw-r--r--src/mame/drivers/mc10.cpp2
-rw-r--r--src/mame/drivers/namcos1.cpp2
-rw-r--r--src/mame/drivers/namcos86.cpp2
-rw-r--r--src/mame/drivers/pacland.cpp2
-rw-r--r--src/mame/drivers/rvoice.cpp2
-rw-r--r--src/mame/drivers/skykid.cpp2
-rw-r--r--src/mame/drivers/tceptor.cpp2
-rw-r--r--src/mame/includes/adam.h2
-rw-r--r--src/mame/includes/atarist.h2
-rw-r--r--src/mame/includes/hx20.h2
-rw-r--r--src/mame/includes/psion.h2
-rw-r--r--src/mame/includes/px8.h2
-rw-r--r--src/mame/includes/slapstic.h3
-rw-r--r--src/mame/machine/slapstic.cpp3
43 files changed, 1577 insertions, 1491 deletions
diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua
index 4e04557f487..d1708cd0029 100644
--- a/scripts/src/cpu.lua
+++ b/scripts/src/cpu.lua
@@ -1315,6 +1315,8 @@ if (CPUS["M6800"]~=null) then
files {
MAME_DIR .. "src/devices/cpu/m6800/m6800.cpp",
MAME_DIR .. "src/devices/cpu/m6800/m6800.h",
+ MAME_DIR .. "src/devices/cpu/m6800/m6801.cpp",
+ MAME_DIR .. "src/devices/cpu/m6800/m6801.h",
MAME_DIR .. "src/devices/cpu/m6800/6800ops.hxx",
MAME_DIR .. "src/devices/cpu/m6800/6800tbl.hxx",
}
diff --git a/src/devices/bus/adamnet/ddp.h b/src/devices/bus/adamnet/ddp.h
index 2ba54d7e006..28fafd1c2b0 100644
--- a/src/devices/bus/adamnet/ddp.h
+++ b/src/devices/bus/adamnet/ddp.h
@@ -12,7 +12,7 @@
#pragma once
#include "adamnet.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "formats/adam_cas.h"
#include "imagedev/cassette.h"
diff --git a/src/devices/bus/adamnet/fdc.h b/src/devices/bus/adamnet/fdc.h
index b966d938e33..962c8bf7e2b 100644
--- a/src/devices/bus/adamnet/fdc.h
+++ b/src/devices/bus/adamnet/fdc.h
@@ -12,7 +12,7 @@
#pragma once
#include "adamnet.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "formats/adam_dsk.h"
#include "machine/wd_fdc.h"
diff --git a/src/devices/bus/adamnet/kb.h b/src/devices/bus/adamnet/kb.h
index e438ec17b68..bd1c7631966 100644
--- a/src/devices/bus/adamnet/kb.h
+++ b/src/devices/bus/adamnet/kb.h
@@ -12,7 +12,7 @@
#pragma once
#include "adamnet.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
diff --git a/src/devices/bus/adamnet/printer.h b/src/devices/bus/adamnet/printer.h
index 543cbfdded6..fe246bf9cca 100644
--- a/src/devices/bus/adamnet/printer.h
+++ b/src/devices/bus/adamnet/printer.h
@@ -12,7 +12,7 @@
#pragma once
#include "adamnet.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
diff --git a/src/devices/bus/adamnet/spi.h b/src/devices/bus/adamnet/spi.h
index 01e86d5c67f..0f97c5e7d81 100644
--- a/src/devices/bus/adamnet/spi.h
+++ b/src/devices/bus/adamnet/spi.h
@@ -14,7 +14,7 @@
#include "adamnet.h"
#include "bus/centronics/ctronics.h"
#include "bus/rs232/rs232.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "machine/mc2661.h"
diff --git a/src/devices/bus/epson_sio/pf10.h b/src/devices/bus/epson_sio/pf10.h
index e3d4f01e69c..6aff101af70 100644
--- a/src/devices/bus/epson_sio/pf10.h
+++ b/src/devices/bus/epson_sio/pf10.h
@@ -14,7 +14,7 @@
#pragma once
#include "epson_sio.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "machine/upd765.h"
diff --git a/src/devices/cpu/m6800/6800ops.hxx b/src/devices/cpu/m6800/6800ops.hxx
index a2acf33292c..d8d8ae6da53 100644
--- a/src/devices/cpu/m6800/6800ops.hxx
+++ b/src/devices/cpu/m6800/6800ops.hxx
@@ -41,7 +41,7 @@ OP_HANDLER( illegl3 )
OP_HANDLER( trap )
{
logerror("m6800: illegal opcode: address %04X, op %02X\n",PC-1,(int) M_RDOP_ARG(PC-1)&0xFF);
- TAKE_TRAP;
+ TAKE_TRAP();
}
/* $00 ILLEGAL */
@@ -219,7 +219,7 @@ OP_HANDLER( slp )
{
/* wait for next IRQ (same as waiting of wai) */
m_wai_state |= M6800_SLP;
- EAT_CYCLES;
+ EAT_CYCLES();
}
/* $1b ABA inherent ***** */
@@ -459,7 +459,7 @@ OP_HANDLER( wai )
PUSHBYTE(B);
PUSHBYTE(CC);
CHECK_IRQ_LINES();
- if (m_wai_state & M6800_WAI) EAT_CYCLES;
+ if (m_wai_state & M6800_WAI) EAT_CYCLES();
}
/* $3f SWI absolute indirect ----- */
diff --git a/src/devices/cpu/m6800/6800tbl.hxx b/src/devices/cpu/m6800/6800tbl.hxx
index 084f63501c0..4581d59632e 100644
--- a/src/devices/cpu/m6800/6800tbl.hxx
+++ b/src/devices/cpu/m6800/6800tbl.hxx
@@ -35,76 +35,6 @@ const m6800_cpu_device::op_func m6800_cpu_device::m6800_insn[0x100] = {
&m6800_cpu_device::eorb_ex,&m6800_cpu_device::adcb_ex,&m6800_cpu_device::orb_ex, &m6800_cpu_device::addb_ex,&m6800_cpu_device::illegl3,&m6800_cpu_device::illegl3,&m6800_cpu_device::ldx_ex, &m6800_cpu_device::stx_ex
};
-const m6800_cpu_device::op_func m6800_cpu_device::m6803_insn[0x100] = {
-&m6800_cpu_device::illegl1,&m6800_cpu_device::nop, &m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,&m6800_cpu_device::lsrd, &m6800_cpu_device::asld, &m6800_cpu_device::tap, &m6800_cpu_device::tpa,
-&m6800_cpu_device::inx, &m6800_cpu_device::dex, &m6800_cpu_device::clv, &m6800_cpu_device::sev, &m6800_cpu_device::clc, &m6800_cpu_device::sec, &m6800_cpu_device::cli, &m6800_cpu_device::sei,
-&m6800_cpu_device::sba, &m6800_cpu_device::cba, &m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,&m6800_cpu_device::tab, &m6800_cpu_device::tba,
-&m6800_cpu_device::illegl1,&m6800_cpu_device::daa, &m6800_cpu_device::illegl1,&m6800_cpu_device::aba, &m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,
-&m6800_cpu_device::bra, &m6800_cpu_device::brn, &m6800_cpu_device::bhi, &m6800_cpu_device::bls, &m6800_cpu_device::bcc, &m6800_cpu_device::bcs, &m6800_cpu_device::bne, &m6800_cpu_device::beq,
-&m6800_cpu_device::bvc, &m6800_cpu_device::bvs, &m6800_cpu_device::bpl, &m6800_cpu_device::bmi, &m6800_cpu_device::bge, &m6800_cpu_device::blt, &m6800_cpu_device::bgt, &m6800_cpu_device::ble,
-&m6800_cpu_device::tsx, &m6800_cpu_device::ins, &m6800_cpu_device::pula, &m6800_cpu_device::pulb, &m6800_cpu_device::des, &m6800_cpu_device::txs, &m6800_cpu_device::psha, &m6800_cpu_device::pshb,
-&m6800_cpu_device::pulx, &m6800_cpu_device::rts, &m6800_cpu_device::abx, &m6800_cpu_device::rti, &m6800_cpu_device::pshx, &m6800_cpu_device::mul, &m6800_cpu_device::wai, &m6800_cpu_device::swi,
-&m6800_cpu_device::nega, &m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,&m6800_cpu_device::coma, &m6800_cpu_device::lsra, &m6800_cpu_device::illegl1,&m6800_cpu_device::rora, &m6800_cpu_device::asra,
-&m6800_cpu_device::asla, &m6800_cpu_device::rola, &m6800_cpu_device::deca, &m6800_cpu_device::illegl1,&m6800_cpu_device::inca, &m6800_cpu_device::tsta, &m6800_cpu_device::illegl1,&m6800_cpu_device::clra,
-&m6800_cpu_device::negb, &m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,&m6800_cpu_device::comb, &m6800_cpu_device::lsrb, &m6800_cpu_device::illegl1,&m6800_cpu_device::rorb, &m6800_cpu_device::asrb,
-&m6800_cpu_device::aslb, &m6800_cpu_device::rolb, &m6800_cpu_device::decb, &m6800_cpu_device::illegl1,&m6800_cpu_device::incb, &m6800_cpu_device::tstb, &m6800_cpu_device::illegl1,&m6800_cpu_device::clrb,
-&m6800_cpu_device::neg_ix, &m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,&m6800_cpu_device::com_ix, &m6800_cpu_device::lsr_ix, &m6800_cpu_device::illegl1,&m6800_cpu_device::ror_ix, &m6800_cpu_device::asr_ix,
-&m6800_cpu_device::asl_ix, &m6800_cpu_device::rol_ix, &m6800_cpu_device::dec_ix, &m6800_cpu_device::illegl1,&m6800_cpu_device::inc_ix, &m6800_cpu_device::tst_ix, &m6800_cpu_device::jmp_ix, &m6800_cpu_device::clr_ix,
-&m6800_cpu_device::neg_ex, &m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,&m6800_cpu_device::com_ex, &m6800_cpu_device::lsr_ex, &m6800_cpu_device::illegl1,&m6800_cpu_device::ror_ex, &m6800_cpu_device::asr_ex,
-&m6800_cpu_device::asl_ex, &m6800_cpu_device::rol_ex, &m6800_cpu_device::dec_ex, &m6800_cpu_device::illegl1,&m6800_cpu_device::inc_ex, &m6800_cpu_device::tst_ex, &m6800_cpu_device::jmp_ex, &m6800_cpu_device::clr_ex,
-&m6800_cpu_device::suba_im,&m6800_cpu_device::cmpa_im,&m6800_cpu_device::sbca_im,&m6800_cpu_device::subd_im,&m6800_cpu_device::anda_im,&m6800_cpu_device::bita_im,&m6800_cpu_device::lda_im, &m6800_cpu_device::sta_im,
-&m6800_cpu_device::eora_im,&m6800_cpu_device::adca_im,&m6800_cpu_device::ora_im, &m6800_cpu_device::adda_im,&m6800_cpu_device::cpx_im ,&m6800_cpu_device::bsr, &m6800_cpu_device::lds_im, &m6800_cpu_device::sts_im,
-&m6800_cpu_device::suba_di,&m6800_cpu_device::cmpa_di,&m6800_cpu_device::sbca_di,&m6800_cpu_device::subd_di,&m6800_cpu_device::anda_di,&m6800_cpu_device::bita_di,&m6800_cpu_device::lda_di, &m6800_cpu_device::sta_di,
-&m6800_cpu_device::eora_di,&m6800_cpu_device::adca_di,&m6800_cpu_device::ora_di, &m6800_cpu_device::adda_di,&m6800_cpu_device::cpx_di ,&m6800_cpu_device::jsr_di, &m6800_cpu_device::lds_di, &m6800_cpu_device::sts_di,
-&m6800_cpu_device::suba_ix,&m6800_cpu_device::cmpa_ix,&m6800_cpu_device::sbca_ix,&m6800_cpu_device::subd_ix,&m6800_cpu_device::anda_ix,&m6800_cpu_device::bita_ix,&m6800_cpu_device::lda_ix, &m6800_cpu_device::sta_ix,
-&m6800_cpu_device::eora_ix,&m6800_cpu_device::adca_ix,&m6800_cpu_device::ora_ix, &m6800_cpu_device::adda_ix,&m6800_cpu_device::cpx_ix ,&m6800_cpu_device::jsr_ix, &m6800_cpu_device::lds_ix, &m6800_cpu_device::sts_ix,
-&m6800_cpu_device::suba_ex,&m6800_cpu_device::cmpa_ex,&m6800_cpu_device::sbca_ex,&m6800_cpu_device::subd_ex,&m6800_cpu_device::anda_ex,&m6800_cpu_device::bita_ex,&m6800_cpu_device::lda_ex, &m6800_cpu_device::sta_ex,
-&m6800_cpu_device::eora_ex,&m6800_cpu_device::adca_ex,&m6800_cpu_device::ora_ex, &m6800_cpu_device::adda_ex,&m6800_cpu_device::cpx_ex ,&m6800_cpu_device::jsr_ex, &m6800_cpu_device::lds_ex, &m6800_cpu_device::sts_ex,
-&m6800_cpu_device::subb_im,&m6800_cpu_device::cmpb_im,&m6800_cpu_device::sbcb_im,&m6800_cpu_device::addd_im,&m6800_cpu_device::andb_im,&m6800_cpu_device::bitb_im,&m6800_cpu_device::ldb_im, &m6800_cpu_device::stb_im,
-&m6800_cpu_device::eorb_im,&m6800_cpu_device::adcb_im,&m6800_cpu_device::orb_im, &m6800_cpu_device::addb_im,&m6800_cpu_device::ldd_im, &m6800_cpu_device::std_im, &m6800_cpu_device::ldx_im, &m6800_cpu_device::stx_im,
-&m6800_cpu_device::subb_di,&m6800_cpu_device::cmpb_di,&m6800_cpu_device::sbcb_di,&m6800_cpu_device::addd_di,&m6800_cpu_device::andb_di,&m6800_cpu_device::bitb_di,&m6800_cpu_device::ldb_di, &m6800_cpu_device::stb_di,
-&m6800_cpu_device::eorb_di,&m6800_cpu_device::adcb_di,&m6800_cpu_device::orb_di, &m6800_cpu_device::addb_di,&m6800_cpu_device::ldd_di, &m6800_cpu_device::std_di, &m6800_cpu_device::ldx_di, &m6800_cpu_device::stx_di,
-&m6800_cpu_device::subb_ix,&m6800_cpu_device::cmpb_ix,&m6800_cpu_device::sbcb_ix,&m6800_cpu_device::addd_ix,&m6800_cpu_device::andb_ix,&m6800_cpu_device::bitb_ix,&m6800_cpu_device::ldb_ix, &m6800_cpu_device::stb_ix,
-&m6800_cpu_device::eorb_ix,&m6800_cpu_device::adcb_ix,&m6800_cpu_device::orb_ix, &m6800_cpu_device::addb_ix,&m6800_cpu_device::ldd_ix, &m6800_cpu_device::std_ix, &m6800_cpu_device::ldx_ix, &m6800_cpu_device::stx_ix,
-&m6800_cpu_device::subb_ex,&m6800_cpu_device::cmpb_ex,&m6800_cpu_device::sbcb_ex,&m6800_cpu_device::addd_ex,&m6800_cpu_device::andb_ex,&m6800_cpu_device::bitb_ex,&m6800_cpu_device::ldb_ex, &m6800_cpu_device::stb_ex,
-&m6800_cpu_device::eorb_ex,&m6800_cpu_device::adcb_ex,&m6800_cpu_device::orb_ex, &m6800_cpu_device::addb_ex,&m6800_cpu_device::ldd_ex, &m6800_cpu_device::std_ex, &m6800_cpu_device::ldx_ex, &m6800_cpu_device::stx_ex
-};
-
-const m6800_cpu_device::op_func m6800_cpu_device::hd63701_insn[0x100] = {
-&m6800_cpu_device::trap, &m6800_cpu_device::nop, &m6800_cpu_device::trap, &m6800_cpu_device::trap, &m6800_cpu_device::lsrd, &m6800_cpu_device::asld, &m6800_cpu_device::tap, &m6800_cpu_device::tpa,
-&m6800_cpu_device::inx, &m6800_cpu_device::dex, &m6800_cpu_device::clv, &m6800_cpu_device::sev, &m6800_cpu_device::clc, &m6800_cpu_device::sec, &m6800_cpu_device::cli, &m6800_cpu_device::sei,
-&m6800_cpu_device::sba, &m6800_cpu_device::cba, &m6800_cpu_device::undoc1, &m6800_cpu_device::undoc2, &m6800_cpu_device::trap, &m6800_cpu_device::trap, &m6800_cpu_device::tab, &m6800_cpu_device::tba,
-&m6800_cpu_device::xgdx, &m6800_cpu_device::daa, &m6800_cpu_device::slp, &m6800_cpu_device::aba, &m6800_cpu_device::trap, &m6800_cpu_device::trap, &m6800_cpu_device::trap, &m6800_cpu_device::trap,
-&m6800_cpu_device::bra, &m6800_cpu_device::brn, &m6800_cpu_device::bhi, &m6800_cpu_device::bls, &m6800_cpu_device::bcc, &m6800_cpu_device::bcs, &m6800_cpu_device::bne, &m6800_cpu_device::beq,
-&m6800_cpu_device::bvc, &m6800_cpu_device::bvs, &m6800_cpu_device::bpl, &m6800_cpu_device::bmi, &m6800_cpu_device::bge, &m6800_cpu_device::blt, &m6800_cpu_device::bgt, &m6800_cpu_device::ble,
-&m6800_cpu_device::tsx, &m6800_cpu_device::ins, &m6800_cpu_device::pula, &m6800_cpu_device::pulb, &m6800_cpu_device::des, &m6800_cpu_device::txs, &m6800_cpu_device::psha, &m6800_cpu_device::pshb,
-&m6800_cpu_device::pulx, &m6800_cpu_device::rts, &m6800_cpu_device::abx, &m6800_cpu_device::rti, &m6800_cpu_device::pshx, &m6800_cpu_device::mul, &m6800_cpu_device::wai, &m6800_cpu_device::swi,
-&m6800_cpu_device::nega, &m6800_cpu_device::trap, &m6800_cpu_device::trap, &m6800_cpu_device::coma, &m6800_cpu_device::lsra, &m6800_cpu_device::trap, &m6800_cpu_device::rora, &m6800_cpu_device::asra,
-&m6800_cpu_device::asla, &m6800_cpu_device::rola, &m6800_cpu_device::deca, &m6800_cpu_device::trap, &m6800_cpu_device::inca, &m6800_cpu_device::tsta, &m6800_cpu_device::trap, &m6800_cpu_device::clra,
-&m6800_cpu_device::negb, &m6800_cpu_device::trap, &m6800_cpu_device::trap, &m6800_cpu_device::comb, &m6800_cpu_device::lsrb, &m6800_cpu_device::trap, &m6800_cpu_device::rorb, &m6800_cpu_device::asrb,
-&m6800_cpu_device::aslb, &m6800_cpu_device::rolb, &m6800_cpu_device::decb, &m6800_cpu_device::trap, &m6800_cpu_device::incb, &m6800_cpu_device::tstb, &m6800_cpu_device::trap, &m6800_cpu_device::clrb,
-&m6800_cpu_device::neg_ix, &m6800_cpu_device::aim_ix, &m6800_cpu_device::oim_ix, &m6800_cpu_device::com_ix, &m6800_cpu_device::lsr_ix, &m6800_cpu_device::eim_ix, &m6800_cpu_device::ror_ix, &m6800_cpu_device::asr_ix,
-&m6800_cpu_device::asl_ix, &m6800_cpu_device::rol_ix, &m6800_cpu_device::dec_ix, &m6800_cpu_device::tim_ix, &m6800_cpu_device::inc_ix, &m6800_cpu_device::tst_ix, &m6800_cpu_device::jmp_ix, &m6800_cpu_device::clr_ix,
-&m6800_cpu_device::neg_ex, &m6800_cpu_device::aim_di, &m6800_cpu_device::oim_di, &m6800_cpu_device::com_ex, &m6800_cpu_device::lsr_ex, &m6800_cpu_device::eim_di, &m6800_cpu_device::ror_ex, &m6800_cpu_device::asr_ex,
-&m6800_cpu_device::asl_ex, &m6800_cpu_device::rol_ex, &m6800_cpu_device::dec_ex, &m6800_cpu_device::tim_di, &m6800_cpu_device::inc_ex, &m6800_cpu_device::tst_ex, &m6800_cpu_device::jmp_ex, &m6800_cpu_device::clr_ex,
-&m6800_cpu_device::suba_im,&m6800_cpu_device::cmpa_im,&m6800_cpu_device::sbca_im,&m6800_cpu_device::subd_im,&m6800_cpu_device::anda_im,&m6800_cpu_device::bita_im,&m6800_cpu_device::lda_im, &m6800_cpu_device::sta_im,
-&m6800_cpu_device::eora_im,&m6800_cpu_device::adca_im,&m6800_cpu_device::ora_im, &m6800_cpu_device::adda_im,&m6800_cpu_device::cpx_im ,&m6800_cpu_device::bsr, &m6800_cpu_device::lds_im, &m6800_cpu_device::sts_im,
-&m6800_cpu_device::suba_di,&m6800_cpu_device::cmpa_di,&m6800_cpu_device::sbca_di,&m6800_cpu_device::subd_di,&m6800_cpu_device::anda_di,&m6800_cpu_device::bita_di,&m6800_cpu_device::lda_di, &m6800_cpu_device::sta_di,
-&m6800_cpu_device::eora_di,&m6800_cpu_device::adca_di,&m6800_cpu_device::ora_di, &m6800_cpu_device::adda_di,&m6800_cpu_device::cpx_di ,&m6800_cpu_device::jsr_di, &m6800_cpu_device::lds_di, &m6800_cpu_device::sts_di,
-&m6800_cpu_device::suba_ix,&m6800_cpu_device::cmpa_ix,&m6800_cpu_device::sbca_ix,&m6800_cpu_device::subd_ix,&m6800_cpu_device::anda_ix,&m6800_cpu_device::bita_ix,&m6800_cpu_device::lda_ix, &m6800_cpu_device::sta_ix,
-&m6800_cpu_device::eora_ix,&m6800_cpu_device::adca_ix,&m6800_cpu_device::ora_ix, &m6800_cpu_device::adda_ix,&m6800_cpu_device::cpx_ix ,&m6800_cpu_device::jsr_ix, &m6800_cpu_device::lds_ix, &m6800_cpu_device::sts_ix,
-&m6800_cpu_device::suba_ex,&m6800_cpu_device::cmpa_ex,&m6800_cpu_device::sbca_ex,&m6800_cpu_device::subd_ex,&m6800_cpu_device::anda_ex,&m6800_cpu_device::bita_ex,&m6800_cpu_device::lda_ex, &m6800_cpu_device::sta_ex,
-&m6800_cpu_device::eora_ex,&m6800_cpu_device::adca_ex,&m6800_cpu_device::ora_ex, &m6800_cpu_device::adda_ex,&m6800_cpu_device::cpx_ex ,&m6800_cpu_device::jsr_ex, &m6800_cpu_device::lds_ex, &m6800_cpu_device::sts_ex,
-&m6800_cpu_device::subb_im,&m6800_cpu_device::cmpb_im,&m6800_cpu_device::sbcb_im,&m6800_cpu_device::addd_im,&m6800_cpu_device::andb_im,&m6800_cpu_device::bitb_im,&m6800_cpu_device::ldb_im, &m6800_cpu_device::stb_im,
-&m6800_cpu_device::eorb_im,&m6800_cpu_device::adcb_im,&m6800_cpu_device::orb_im, &m6800_cpu_device::addb_im,&m6800_cpu_device::ldd_im, &m6800_cpu_device::std_im, &m6800_cpu_device::ldx_im, &m6800_cpu_device::stx_im,
-&m6800_cpu_device::subb_di,&m6800_cpu_device::cmpb_di,&m6800_cpu_device::sbcb_di,&m6800_cpu_device::addd_di,&m6800_cpu_device::andb_di,&m6800_cpu_device::bitb_di,&m6800_cpu_device::ldb_di, &m6800_cpu_device::stb_di,
-&m6800_cpu_device::eorb_di,&m6800_cpu_device::adcb_di,&m6800_cpu_device::orb_di, &m6800_cpu_device::addb_di,&m6800_cpu_device::ldd_di, &m6800_cpu_device::std_di, &m6800_cpu_device::ldx_di, &m6800_cpu_device::stx_di,
-&m6800_cpu_device::subb_ix,&m6800_cpu_device::cmpb_ix,&m6800_cpu_device::sbcb_ix,&m6800_cpu_device::addd_ix,&m6800_cpu_device::andb_ix,&m6800_cpu_device::bitb_ix,&m6800_cpu_device::ldb_ix, &m6800_cpu_device::stb_ix,
-&m6800_cpu_device::eorb_ix,&m6800_cpu_device::adcb_ix,&m6800_cpu_device::orb_ix, &m6800_cpu_device::addb_ix,&m6800_cpu_device::ldd_ix, &m6800_cpu_device::std_ix, &m6800_cpu_device::ldx_ix, &m6800_cpu_device::stx_ix,
-&m6800_cpu_device::subb_ex,&m6800_cpu_device::cmpb_ex,&m6800_cpu_device::sbcb_ex,&m6800_cpu_device::addd_ex,&m6800_cpu_device::andb_ex,&m6800_cpu_device::bitb_ex,&m6800_cpu_device::ldb_ex, &m6800_cpu_device::stb_ex,
-&m6800_cpu_device::eorb_ex,&m6800_cpu_device::adcb_ex,&m6800_cpu_device::orb_ex, &m6800_cpu_device::addb_ex,&m6800_cpu_device::ldd_ex, &m6800_cpu_device::std_ex, &m6800_cpu_device::ldx_ex, &m6800_cpu_device::stx_ex
-};
-
const m6800_cpu_device::op_func m6800_cpu_device::nsc8105_insn[0x100] = {
// 0
&m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,&m6800_cpu_device::nop, &m6800_cpu_device::illegl1,&m6800_cpu_device::illegl1,&m6800_cpu_device::tap, &m6800_cpu_device::illegl1,&m6800_cpu_device::tpa,
diff --git a/src/devices/cpu/m6800/m6800.cpp b/src/devices/cpu/m6800/m6800.cpp
index 5b13a1b5d20..fd7242b0d16 100644
--- a/src/devices/cpu/m6800/m6800.cpp
+++ b/src/devices/cpu/m6800/m6800.cpp
@@ -92,25 +92,6 @@ TODO:
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-#if 0
-/* CPU subtypes, needed for extra insn after TAP/CLI/SEI */
-enum
-{
- SUBTYPE_M6800,
- SUBTYPE_M6801,
- SUBTYPE_M6802,
- SUBTYPE_M6803,
- SUBTYPE_M6808,
- SUBTYPE_HD6301,
- SUBTYPE_HD63701,
- SUBTYPE_NSC8105
-};
-#endif
-
-
-#if 0
-static void hd63701_trap_pc();
-#endif
#define pPPC m_ppc
#define pPC m_pc
@@ -128,21 +109,9 @@ static void hd63701_trap_pc();
#define B m_d.b.l
#define CC m_cc
-#define CT m_counter.w.l
-#define CTH m_counter.w.h
-#define CTD m_counter.d
-#define OC m_output_compare.w.l
-#define OCH m_output_compare.w.h
-#define OCD m_output_compare.d
-#define TOH m_timer_over.w.l
-#define TOD m_timer_over.d
-
#define EAD m_ea.d
#define EA m_ea.w.l
-/* point of next timer event */
-static uint32_t timer_next;
-
/* memory interface */
/****************************************************************************/
@@ -178,110 +147,6 @@ static uint32_t timer_next;
#define PULLBYTE(b) S++; b = RM(SD)
#define PULLWORD(w) S++; w.d = RM(SD)<<8; S++; w.d |= RM(SD)
-#define MODIFIED_tcsr { \
- m_irq2 = (m_tcsr&(m_tcsr<<3))&(TCSR_ICF|TCSR_OCF|TCSR_TOF); \
-}
-
-#define SET_TIMER_EVENT { \
- timer_next = (OCD - CTD < TOD - CTD) ? OCD : TOD; \
-}
-
-/* cleanup high-word of counters */
-#define CLEANUP_COUNTERS() { \
- OCH -= CTH; \
- TOH -= CTH; \
- CTH = 0; \
- SET_TIMER_EVENT; \
-}
-
-/* when change freerunningcounter or outputcapture */
-#define MODIFIED_counters { \
- OCH = (OC >= CT) ? CTH : CTH+1; \
- SET_TIMER_EVENT; \
-}
-
-// I/O registers
-
-enum
-{
- IO_P1DDR = 0,
- IO_P2DDR,
- IO_P1DATA,
- IO_P2DATA,
- IO_P3DDR,
- IO_P4DDR,
- IO_P3DATA,
- IO_P4DATA,
- IO_TCSR,
- IO_CH,
- IO_CL,
- IO_OCRH,
- IO_OCRL,
- IO_ICRH,
- IO_ICRL,
- IO_P3CSR,
- IO_RMCR,
- IO_TRCSR,
- IO_RDR,
- IO_TDR,
- IO_RCR,
- IO_CAAH,
- IO_CAAL,
- IO_TCR1,
- IO_TCR2,
- IO_TSR,
- IO_OCR2H,
- IO_OCR2L,
- IO_OCR3H,
- IO_OCR3L,
- IO_ICR2H,
- IO_ICR2L
-};
-
-// serial I/O
-
-#define M6800_RMCR_SS_MASK 0x03 // Speed Select
-#define M6800_RMCR_SS_4096 0x03 // E / 4096
-#define M6800_RMCR_SS_1024 0x02 // E / 1024
-#define M6800_RMCR_SS_128 0x01 // E / 128
-#define M6800_RMCR_SS_16 0x00 // E / 16
-#define M6800_RMCR_CC_MASK 0x0c // Clock Control/Format Select
-
-#define M6800_TRCSR_RDRF 0x80 // Receive Data Register Full
-#define M6800_TRCSR_ORFE 0x40 // Over Run Framing Error
-#define M6800_TRCSR_TDRE 0x20 // Transmit Data Register Empty
-#define M6800_TRCSR_RIE 0x10 // Receive Interrupt Enable
-#define M6800_TRCSR_RE 0x08 // Receive Enable
-#define M6800_TRCSR_TIE 0x04 // Transmit Interrupt Enable
-#define M6800_TRCSR_TE 0x02 // Transmit Enable
-#define M6800_TRCSR_WU 0x01 // Wake Up
-
-#define M6800_PORT2_IO4 0x10
-#define M6800_PORT2_IO3 0x08
-
-#define M6801_P3CSR_LE 0x08
-#define M6801_P3CSR_OSS 0x10
-#define M6801_P3CSR_IS3_ENABLE 0x40
-#define M6801_P3CSR_IS3_FLAG 0x80
-
-static const int M6800_RMCR_SS[] = { 16, 128, 1024, 4096 };
-
-#define M6800_SERIAL_START 0
-#define M6800_SERIAL_STOP 9
-
-enum
-{
- M6800_TX_STATE_INIT = 0,
- M6800_TX_STATE_READY
-};
-
-/* take interrupt */
-#define TAKE_ICI enter_interrupt("M6800 '%s' take ICI\n",0xfff6)
-#define TAKE_OCI enter_interrupt("M6800 '%s' take OCI\n",0xfff4)
-#define TAKE_TOI enter_interrupt("M6800 '%s' take TOI\n",0xfff2)
-#define TAKE_SCI enter_interrupt("M6800 '%s' take SCI\n",0xfff0)
-#define TAKE_TRAP enter_interrupt("M6800 '%s' take TRAP\n",0xffee)
-
/* operate one instruction for */
#define ONE_MORE_INSN() { \
uint8_t ireg; \
@@ -393,16 +258,6 @@ const uint8_t m6800_cpu_device::flags8d[256]= /* decrement */
#define SEI CC|=0x10
#define CLI CC&=~0x10
-/* mnemonicos for the Timer Control and Status Register bits */
-#define TCSR_OLVL 0x01
-#define TCSR_IEDG 0x02
-#define TCSR_ETOI 0x04
-#define TCSR_EOCI 0x08
-#define TCSR_EICI 0x10
-#define TCSR_TOF 0x20
-#define TCSR_OCF 0x40
-#define TCSR_ICF 0x80
-
/* macros for convenience */
#define DIRBYTE(b) {DIRECT;b=RM(EAD);}
#define DIRWORD(w) {DIRECT;w.d=RM16(EAD);}
@@ -416,9 +271,6 @@ const uint8_t m6800_cpu_device::flags8d[256]= /* decrement */
#define BRANCH(f) {IMMBYTE(t);if(f){PC+=SIGNED(t);}}
#define NXORV ((CC&0x08)^((CC&0x02)<<2))
-#define M6800_WAI 8 /* set when WAI is waiting for an interrupt */
-#define M6800_SLP 0x10 /* HD63701 only */
-
/* Note: don't use 0 cycles here for invalid opcodes so that we don't */
/* hang in an infinite loop if we hit one */
#define XX 5 // invalid opcode unknown cc
@@ -443,48 +295,6 @@ const uint8_t m6800_cpu_device::cycles_6800[256] =
/*F*/ 4, 4, 4,XX, 4, 4, 4, 5, 4, 4, 4, 4,XX,XX, 5, 6
};
-const uint8_t m6800_cpu_device::cycles_6803[256] =
-{
- /* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
- /*0*/ XX, 2,XX,XX, 3, 3, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2,
- /*1*/ 2, 2,XX,XX,XX,XX, 2, 2,XX, 2,XX, 2,XX,XX,XX,XX,
- /*2*/ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
- /*3*/ 3, 3, 4, 4, 3, 3, 3, 3, 5, 5, 3,10, 4,10, 9,12,
- /*4*/ 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
- /*5*/ 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
- /*6*/ 6,XX,XX, 6, 6,XX, 6, 6, 6, 6, 6,XX, 6, 6, 3, 6,
- /*7*/ 6,XX,XX, 6, 6,XX, 6, 6, 6, 6, 6,XX, 6, 6, 3, 6,
- /*8*/ 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 4, 6, 3, 3,
- /*9*/ 3, 3, 3, 5, 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 4, 4,
- /*A*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 5, 5,
- /*B*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 5, 5,
- /*C*/ 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 3,XX, 3, 3,
- /*D*/ 3, 3, 3, 5, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4,
- /*E*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
- /*F*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5
-};
-
-const uint8_t m6800_cpu_device::cycles_63701[256] =
-{
- /* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
- /*0*/ XX, 1,XX,XX, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- /*1*/ 1, 1,XX,XX,XX,XX, 1, 1, 2, 2, 4, 1,XX,XX,XX,XX,
- /*2*/ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
- /*3*/ 1, 1, 3, 3, 1, 1, 4, 4, 4, 5, 1,10, 5, 7, 9,12,
- /*4*/ 1,XX,XX, 1, 1,XX, 1, 1, 1, 1, 1,XX, 1, 1,XX, 1,
- /*5*/ 1,XX,XX, 1, 1,XX, 1, 1, 1, 1, 1,XX, 1, 1,XX, 1,
- /*6*/ 6, 7, 7, 6, 6, 7, 6, 6, 6, 6, 6, 5, 6, 4, 3, 5,
- /*7*/ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 4, 6, 4, 3, 5,
- /*8*/ 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 2, 3, 5, 3, 3,
- /*9*/ 3, 3, 3, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 5, 4, 4,
- /*A*/ 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
- /*B*/ 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 6, 5, 5,
- /*C*/ 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 2, 3,XX, 3, 3,
- /*D*/ 3, 3, 3, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4,
- /*E*/ 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
- /*F*/ 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5
-};
-
const uint8_t m6800_cpu_device::cycles_nsc8105[256] =
{
/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
@@ -507,58 +317,25 @@ const uint8_t m6800_cpu_device::cycles_nsc8105[256] =
};
#undef XX // /invalid opcode unknown cc
-#define EAT_CYCLES \
-{ \
- int cycles_to_eat; \
- \
- cycles_to_eat = timer_next - CTD; \
- if( cycles_to_eat > m_icount) cycles_to_eat = m_icount; \
- if (cycles_to_eat > 0) \
- { \
- increment_counter(cycles_to_eat); \
- } \
-}
-
DEFINE_DEVICE_TYPE(M6800, m6800_cpu_device, "m6800", "M6800")
-DEFINE_DEVICE_TYPE(M6801, m6801_cpu_device, "m6801", "M6801")
DEFINE_DEVICE_TYPE(M6802, m6802_cpu_device, "m6802", "M6802")
-DEFINE_DEVICE_TYPE(M6803, m6803_cpu_device, "m6803", "M6803")
DEFINE_DEVICE_TYPE(M6808, m6808_cpu_device, "m6808", "M6808")
-DEFINE_DEVICE_TYPE(HD6301, hd6301_cpu_device, "hd6301", "HD6301")
-DEFINE_DEVICE_TYPE(HD63701, hd63701_cpu_device, "hd63701", "HD63701")
DEFINE_DEVICE_TYPE(NSC8105, nsc8105_cpu_device, "nsc8105", "NSC8105")
-DEFINE_DEVICE_TYPE(HD6303R, hd6303r_cpu_device, "hd6304r", "HD6304R")
-DEFINE_DEVICE_TYPE(HD6303Y, hd6303y_cpu_device, "hd6303y", "HD6303Y")
m6800_cpu_device::m6800_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : m6800_cpu_device(mconfig, M6800, tag, owner, clock, false, 1, m6800_insn, cycles_6800, nullptr)
+ : m6800_cpu_device(mconfig, M6800, tag, owner, clock, m6800_insn, cycles_6800, nullptr)
{
}
-m6800_cpu_device::m6800_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, bool has_io, int clock_divider, const op_func *insn, const uint8_t *cycles, address_map_constructor internal)
+m6800_cpu_device::m6800_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, const op_func *insn, const uint8_t *cycles, address_map_constructor internal)
: cpu_device(mconfig, type, tag, owner, clock)
, m_program_config("program", ENDIANNESS_BIG, 8, 16, 0, internal)
, m_decrypted_opcodes_config("program", ENDIANNESS_BIG, 8, 16, 0)
- , m_io_config("io", ENDIANNESS_BIG, 8, 9, 0)
- , m_has_io(has_io)
- , m_out_sc2_func(*this)
- , m_out_sertx_func(*this)
, m_insn(insn)
, m_cycles(cycles)
{
- m_clock_divider = clock_divider;
-}
-
-m6801_cpu_device::m6801_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : m6801_cpu_device(mconfig, M6801, tag, owner, clock, m6803_insn, cycles_6803, nullptr)
-{
-}
-
-m6801_cpu_device::m6801_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, const op_func *insn, const uint8_t *cycles, address_map_constructor internal)
- : m6800_cpu_device(mconfig, type, tag, owner, clock, true, 4, insn, cycles, internal)
-{
}
m6802_cpu_device::m6802_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
@@ -567,19 +344,7 @@ m6802_cpu_device::m6802_cpu_device(const machine_config &mconfig, const char *ta
}
m6802_cpu_device::m6802_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, const op_func *insn, const uint8_t *cycles)
- : m6800_cpu_device(mconfig, type, tag, owner, clock, false, 4, insn, cycles, nullptr)
-{
-}
-
-static ADDRESS_MAP_START(m6803_mem, AS_PROGRAM, 8, m6800_cpu_device)
- AM_RANGE(0x0000, 0x001f) AM_READWRITE(m6801_io_r, m6801_io_w)
- AM_RANGE(0x0020, 0x007f) AM_NOP /* unused */
- AM_RANGE(0x0080, 0x00ff) AM_RAM /* 6803 internal RAM */
-ADDRESS_MAP_END
-
-
-m6803_cpu_device::m6803_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : m6801_cpu_device(mconfig, M6803, tag, owner, clock, m6803_insn, cycles_6803, ADDRESS_MAP_NAME(m6803_mem))
+ : m6800_cpu_device(mconfig, type, tag, owner, clock, insn, cycles, nullptr)
{
}
@@ -588,42 +353,16 @@ m6808_cpu_device::m6808_cpu_device(const machine_config &mconfig, const char *ta
{
}
-hd6301_cpu_device::hd6301_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : hd6301_cpu_device(mconfig, HD6301, tag, owner, clock)
-{
-}
-
-hd6301_cpu_device::hd6301_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
- : m6801_cpu_device(mconfig, type, tag, owner, clock, hd63701_insn, cycles_63701)
-{
-}
-
-hd63701_cpu_device::hd63701_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : m6801_cpu_device(mconfig, HD63701, tag, owner, clock, hd63701_insn, cycles_63701)
-{
-}
-
nsc8105_cpu_device::nsc8105_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: m6802_cpu_device(mconfig, NSC8105, tag, owner, clock, nsc8105_insn, cycles_nsc8105)
{
}
-hd6303r_cpu_device::hd6303r_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : hd6301_cpu_device(mconfig, HD6303R, tag, owner, clock)
-{
-}
-
-hd6303y_cpu_device::hd6303y_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : hd6301_cpu_device(mconfig, HD6303Y, tag, owner, clock)
-{
-}
-
const address_space_config *m6800_cpu_device::memory_space_config(address_spacenum spacenum) const
{
switch(spacenum)
{
case AS_PROGRAM: return &m_program_config;
- case AS_IO: return m_has_io ? &m_io_config : nullptr;
case AS_DECRYPTED_OPCODES: return has_configured_map(AS_DECRYPTED_OPCODES) ? &m_decrypted_opcodes_config : nullptr;
default: return nullptr;
}
@@ -667,31 +406,6 @@ void m6800_cpu_device::enter_interrupt(const char *message,uint16_t irq_vector)
-void m6800_cpu_device::m6800_check_irq2()
-{
- if ((m_tcsr & (TCSR_EICI|TCSR_ICF)) == (TCSR_EICI|TCSR_ICF))
- {
- TAKE_ICI;
- standard_irq_callback(M6801_TIN_LINE);
- }
- else if ((m_tcsr & (TCSR_EOCI|TCSR_OCF)) == (TCSR_EOCI|TCSR_OCF))
- {
- TAKE_OCI;
- }
- else if ((m_tcsr & (TCSR_ETOI|TCSR_TOF)) == (TCSR_ETOI|TCSR_TOF))
- {
- TAKE_TOI;
- }
- else if (((m_trcsr & (M6800_TRCSR_RIE|M6800_TRCSR_RDRF)) == (M6800_TRCSR_RIE|M6800_TRCSR_RDRF)) ||
- ((m_trcsr & (M6800_TRCSR_RIE|M6800_TRCSR_ORFE)) == (M6800_TRCSR_RIE|M6800_TRCSR_ORFE)) ||
- ((m_trcsr & (M6800_TRCSR_TIE|M6800_TRCSR_TDRE)) == (M6800_TRCSR_TIE|M6800_TRCSR_TDRE)))
- {
- //logerror("M6800 '%s' SCI interrupt\n", tag());
- TAKE_SCI;
- }
-}
-
-
/* check the IRQ lines for pending interrupts */
void m6800_cpu_device::CHECK_IRQ_LINES()
{
@@ -724,108 +438,14 @@ void m6800_cpu_device::CHECK_IRQ_LINES()
}
}
-/* check OCI or TOI */
-void m6800_cpu_device::check_timer_event()
-{
- /* OCI */
- if( CTD >= OCD)
- {
- OCH++; // next IRQ point
- m_tcsr |= TCSR_OCF;
- m_pending_tcsr |= TCSR_OCF;
- MODIFIED_tcsr;
- if((m_tcsr & TCSR_EOCI) && m_wai_state & M6800_SLP)
- m_wai_state &= ~M6800_SLP;
- if ( !(CC & 0x10) && (m_tcsr & TCSR_EOCI))
- TAKE_OCI;
-
- // if output on P21 is enabled, let's do it
- if (m_port2_ddr & 2)
- {
- m_port2_data &= ~2;
- m_port2_data |= (m_tcsr & TCSR_OLVL) << 1;
- m_port2_written = 1;
- write_port2();
- }
- }
- /* TOI */
- if( CTD >= TOD)
- {
- TOH++; // next IRQ point
-#if 0
- CLEANUP_COUNTERS();
-#endif
- m_tcsr |= TCSR_TOF;
- m_pending_tcsr |= TCSR_TOF;
- MODIFIED_tcsr;
- if((m_tcsr & TCSR_ETOI) && m_wai_state & M6800_SLP)
- m_wai_state &= ~M6800_SLP;
- if ( !(CC & 0x10) && (m_tcsr & TCSR_ETOI))
- TAKE_TOI;
- }
- /* set next event */
- SET_TIMER_EVENT;
-}
-
void m6800_cpu_device::increment_counter(int amount)
{
m_icount -= amount;
- CTD += amount;
- if( CTD >= timer_next)
- check_timer_event();
-}
-
-void m6800_cpu_device::set_rmcr(uint8_t data)
-{
- if (m_rmcr == data) return;
-
- m_rmcr = data;
-
- switch ((m_rmcr & M6800_RMCR_CC_MASK) >> 2)
- {
- case 0:
- m_sci_timer->enable(false);
- m_use_ext_serclock = false;
- break;
-
- case 3: // external clock
- m_use_ext_serclock = true;
- m_sci_timer->enable(false);
- break;
-
- case 1:
- case 2:
- {
- int divisor = M6800_RMCR_SS[m_rmcr & M6800_RMCR_SS_MASK];
- int clock = m_clock / m_clock_divider;
-
- m_sci_timer->adjust(attotime::from_hz(clock / divisor), 0, attotime::from_hz(clock / divisor));
- m_use_ext_serclock = false;
- }
- break;
- }
}
-void m6800_cpu_device::write_port2()
+void m6800_cpu_device::EAT_CYCLES()
{
- if (!m_port2_written) return;
-
- uint8_t data = m_port2_data;
- uint8_t ddr = m_port2_ddr & 0x1f;
-
- if ((ddr != 0x1f) && ddr)
- {
- data = (m_port2_data & ddr) | (ddr ^ 0xff);
- }
-
- if (m_trcsr & M6800_TRCSR_TE)
- {
- data = (data & 0xef) | (m_tx << 4);
- }
-
- data &= 0x1f;
-
- m_io->write_byte(M6801_PORT2, data);
+ increment_counter(m_icount);
}
/* include the opcode prototypes and function pointer tables */
@@ -834,210 +454,6 @@ void m6800_cpu_device::write_port2()
/* include the opcode functions */
#include "6800ops.hxx"
-int m6800_cpu_device::m6800_rx()
-{
- return (m_io->read_byte(M6801_PORT2) & M6800_PORT2_IO3) >> 3;
-}
-
-void m6800_cpu_device::serial_transmit()
-{
- //logerror("M6800 '%s' Tx Tick\n", tag());
-
- if (m_trcsr & M6800_TRCSR_TE)
- {
- // force Port 2 bit 4 as output
- m_port2_ddr |= M6800_PORT2_IO4;
-
- switch (m_txstate)
- {
- case M6800_TX_STATE_INIT:
- m_tx = 1;
- m_txbits++;
-
- if (m_txbits == 10)
- {
- m_txstate = M6800_TX_STATE_READY;
- m_txbits = M6800_SERIAL_START;
- }
- break;
-
- case M6800_TX_STATE_READY:
- switch (m_txbits)
- {
- case M6800_SERIAL_START:
- if (m_trcsr & M6800_TRCSR_TDRE)
- {
- // transmit buffer is empty, send nothing
- return;
- }
- else
- {
- // transmit buffer is full, send data
-
- // load TDR to shift register
- m_tsr = m_tdr;
-
- // transmit buffer is empty, set TDRE flag
- m_trcsr |= M6800_TRCSR_TDRE;
-
- // send start bit '0'
- m_tx = 0;
-
- m_txbits++;
-
- //logerror("M6800 '%s' Transmit START Data %02x\n", tag(), m_tsr);
- }
- break;
-
- case M6800_SERIAL_STOP:
- // send stop bit '1'
- m_tx = 1;
-
- CHECK_IRQ_LINES();
-
- m_txbits = M6800_SERIAL_START;
-
- //logerror("M6800 '%s' Transmit STOP\n", tag());
- break;
-
- default:
- // send data bit '0' or '1'
- m_tx = m_tsr & 0x01;
-
- // shift transmit register
- m_tsr >>= 1;
-
- //logerror("M6800 '%s' Transmit Bit %u: %u\n", tag(), m_txbits, m_tx);
-
- m_txbits++;
- break;
- }
- break;
- }
-
- m_out_sertx_func((m_tx == 1) ? ASSERT_LINE : CLEAR_LINE);
- m_port2_written = 1;
- write_port2();
- }
-}
-
-void m6800_cpu_device::serial_receive()
-{
- //logerror("M6800 '%s' Rx Tick TRCSR %02x bits %u check %02x\n", tag(), m_trcsr, m_rxbits, m_trcsr & M6800_TRCSR_RE);
-
- if (m_trcsr & M6800_TRCSR_RE)
- {
- if (m_trcsr & M6800_TRCSR_WU)
- {
- // wait for 10 bits of '1'
- if (m6800_rx() == 1)
- {
- m_rxbits++;
-
- //logerror("M6800 '%s' Received WAKE UP bit %u\n", tag(), m_rxbits);
-
- if (m_rxbits == 10)
- {
- //logerror("M6800 '%s' Receiver Wake Up\n", tag());
-
- m_trcsr &= ~M6800_TRCSR_WU;
- m_rxbits = M6800_SERIAL_START;
- }
- }
- else
- {
- //logerror("M6800 '%s' Receiver Wake Up interrupted\n", tag());
-
- m_rxbits = M6800_SERIAL_START;
- }
- }
- else
- {
- // receive data
- switch (m_rxbits)
- {
- case M6800_SERIAL_START:
- if (m6800_rx() == 0)
- {
- // start bit found
- m_rxbits++;
-
- //logerror("M6800 '%s' Received START bit\n", tag());
- }
- break;
-
- case M6800_SERIAL_STOP:
- if (m6800_rx() == 1)
- {
- //logerror("M6800 '%s' Received STOP bit\n", tag());
-
- if (m_trcsr & M6800_TRCSR_RDRF)
- {
- // overrun error
- m_trcsr |= M6800_TRCSR_ORFE;
-
- //logerror("M6800 '%s' Receive Overrun Error\n", tag());
-
- CHECK_IRQ_LINES();
- }
- else
- {
- if (!(m_trcsr & M6800_TRCSR_ORFE))
- {
- // transfer data into receive register
- m_rdr = m_rsr;
-
- //logerror("M6800 '%s' Receive Data Register: %02x\n", tag(), m_rdr);
-
- // set RDRF flag
- m_trcsr |= M6800_TRCSR_RDRF;
-
- CHECK_IRQ_LINES();
- }
- }
- }
- else
- {
- // framing error
- if (!(m_trcsr & M6800_TRCSR_ORFE))
- {
- // transfer unframed data into receive register
- m_rdr = m_rsr;
- }
-
- m_trcsr |= M6800_TRCSR_ORFE;
- m_trcsr &= ~M6800_TRCSR_RDRF;
-
- //logerror("M6800 '%s' Receive Framing Error\n", tag());
-
- CHECK_IRQ_LINES();
- }
-
- m_rxbits = M6800_SERIAL_START;
- break;
-
- default:
- // shift receive register
- m_rsr >>= 1;
-
- // receive bit into register
- m_rsr |= (m6800_rx() << 7);
-
- //logerror("M6800 '%s' Received DATA bit %u: %u\n", tag(), m_rxbits, BIT(m_rsr, 7));
-
- m_rxbits++;
- break;
- }
- }
- }
-}
-
-TIMER_CALLBACK_MEMBER( m6800_cpu_device::sci_tick )
-{
- serial_transmit();
- serial_receive();
-}
-
void m6800_cpu_device::device_start()
{
@@ -1045,20 +461,6 @@ void m6800_cpu_device::device_start()
m_direct = &m_program->direct();
m_decrypted_opcodes = has_space(AS_DECRYPTED_OPCODES) ? &space(AS_DECRYPTED_OPCODES) : m_program;
m_decrypted_opcodes_direct = &m_decrypted_opcodes->direct();
- if ( m_has_io )
- m_io = &space(AS_IO);
-
- m_out_sc2_func.resolve_safe();
- m_out_sertx_func.resolve_safe();
- m_sci_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(m6800_cpu_device::sci_tick),this));
-
- m_port4_ddr = 0;
- m_port4_data = 0;
- m_input_capture = 0;
- m_rdr = 0;
- m_tdr = 0;
- m_rmcr = 0;
- m_ram_ctrl = 0;
m_pc.d = 0;
m_s.d = 0;
@@ -1078,44 +480,6 @@ void m6800_cpu_device::device_start()
save_item(NAME(m_nmi_state));
save_item(NAME(m_nmi_pending));
save_item(NAME(m_irq_state));
- save_item(NAME(m_ic_eddge));
-
- save_item(NAME(m_port1_ddr));
- save_item(NAME(m_port2_ddr));
- save_item(NAME(m_port3_ddr));
- save_item(NAME(m_port4_ddr));
- save_item(NAME(m_port1_data));
- save_item(NAME(m_port2_data));
- save_item(NAME(m_port3_data));
- save_item(NAME(m_port4_data));
- save_item(NAME(m_port2_written));
- save_item(NAME(m_port3_latched));
- save_item(NAME(m_p3csr));
- save_item(NAME(m_p3csr_is3_flag_read));
- save_item(NAME(m_tcsr));
- save_item(NAME(m_pending_tcsr));
- save_item(NAME(m_irq2));
- save_item(NAME(m_ram_ctrl));
-
- save_item(NAME(m_counter.d));
- save_item(NAME(m_output_compare.d));
- save_item(NAME(m_input_capture));
- save_item(NAME(m_timer_over.d));
-
- save_item(NAME(m_clock_divider));
- save_item(NAME(m_trcsr));
- save_item(NAME(m_rmcr));
- save_item(NAME(m_rdr));
- save_item(NAME(m_tdr));
- save_item(NAME(m_rsr));
- save_item(NAME(m_tsr));
- save_item(NAME(m_rxbits));
- save_item(NAME(m_txbits));
- save_item(NAME(m_txstate));
- save_item(NAME(m_trcsr_read_tdre));
- save_item(NAME(m_trcsr_read_orfe));
- save_item(NAME(m_trcsr_read_rdrf));
- save_item(NAME(m_tx));
state_add( M6800_A, "A", m_d.b.h).formatstr("%02X");
state_add( M6800_B, "B", m_d.b.l).formatstr("%02X");
@@ -1159,41 +523,7 @@ void m6800_cpu_device::device_reset()
m_wai_state = 0;
m_nmi_state = 0;
m_nmi_pending = 0;
- m_sc1_state = 0;
m_irq_state[M6800_IRQ_LINE] = 0;
- m_irq_state[M6801_TIN_LINE] = 0;
- m_ic_eddge = 0;
-
- m_port1_ddr = 0x00;
- m_port2_ddr = 0x00;
- m_port3_ddr = 0x00;
- m_port1_data = 0;
- m_p3csr = 0x00;
- m_p3csr_is3_flag_read = 0;
- m_port2_written = 0;
- m_port3_latched = 0;
- /* TODO: on reset port 2 should be read to determine the operating mode (bits 0-2) */
- m_tcsr = 0x00;
- m_pending_tcsr = 0x00;
- m_irq2 = 0;
- CTD = 0x0000;
- OCD = 0xffff;
- TOD = 0xffff;
- m_ram_ctrl |= 0x40;
- m_latch09 = 0;
-
- m_trcsr = M6800_TRCSR_TDRE;
-
- m_txstate = M6800_TX_STATE_INIT;
- m_txbits = m_rxbits = 0;
- m_tx = 1;
- m_trcsr_read_tdre = 0;
- m_trcsr_read_orfe = 0;
- m_trcsr_read_rdrf = 0;
- m_ext_serclock = 0;
- m_use_ext_serclock = false;
-
- set_rmcr(0);
}
@@ -1207,38 +537,10 @@ void m6800_cpu_device::execute_set_input(int irqline, int state)
m_nmi_state = state;
break;
- case M6801_SC1_LINE:
- if (!m_port3_latched && (m_p3csr & M6801_P3CSR_LE))
- {
- if (!m_sc1_state && state)
- {
- // latch input data to port 3
- m_port3_data = (m_io->read_byte(M6801_PORT3) & (m_port3_ddr ^ 0xff)) | (m_port3_data & m_port3_ddr);
- m_port3_latched = 1;
- //logerror("M6801 '%s' Latched Port 3 Data: %02x\n", tag(), m_port3_data);
-
- // set IS3 flag bit
- m_p3csr |= M6801_P3CSR_IS3_FLAG;
- }
- }
- m_sc1_state = state;
- break;
-
default:
LOG(("M6800 '%s' set_irq_line %d,%d\n", tag(), irqline, state));
m_irq_state[irqline] = state;
-
- if (irqline == M6801_TIN_LINE && state != m_irq_state[irqline])
- {
- //eddge = (state == CLEAR_LINE ) ? 2 : 0;
- if( ((m_tcsr&TCSR_IEDG) ^ (state==CLEAR_LINE ? TCSR_IEDG : 0))==0 )
- return;
- /* active edge in */
- m_tcsr |= TCSR_ICF;
- m_pending_tcsr |= TCSR_ICF;
- m_input_capture = CT;
- MODIFIED_tcsr;
- }
+ break;
}
}
@@ -1257,7 +559,7 @@ void m6800_cpu_device::execute_run()
{
if( m_wai_state & (M6800_WAI|M6800_SLP) )
{
- EAT_CYCLES;
+ EAT_CYCLES();
}
else
{
@@ -1272,477 +574,6 @@ void m6800_cpu_device::execute_run()
}
-/*
- if change_pc() direccted these areas ,Call hd63701_trap_pc().
- 'mode' is selected by the sense of p2.0,p2.1,and p2.3 at reset timming.
- mode 0,1,2,4,6 : $0000-$001f
- mode 5 : $0000-$001f,$0200-$efff
- mode 7 : $0000-$001f,$0100-$efff
-*/
-#if 0
-void m6800_cpu_device::hd63701_trap_pc()
-{
- TAKE_TRAP;
-}
-#endif
-
-void m6800_cpu_device::set_os3(int state)
-{
- //logerror("M6801 '%s' OS3: %u\n", tag(), state);
-
- m_out_sc2_func(state);
-}
-
-READ8_MEMBER( m6800_cpu_device::m6801_io_r )
-{
- uint8_t data = 0;
-
- switch (offset)
- {
- case IO_P1DDR:
- data = m_port1_ddr;
- break;
-
- case IO_P2DDR:
- data = m_port2_ddr;
- break;
-
- case IO_P1DATA:
- if(m_port1_ddr == 0xff)
- data = m_port1_data;
- else
- data = (m_io->read_byte(M6801_PORT1) & (m_port1_ddr ^ 0xff))
- | (m_port1_data & m_port1_ddr);
- break;
-
- case IO_P2DATA:
- if(m_port2_ddr == 0xff)
- data = m_port2_data;
- else
- data = (m_io->read_byte(M6801_PORT2) & (m_port2_ddr ^ 0xff))
- | (m_port2_data & m_port2_ddr);
- break;
-
- case IO_P3DDR:
- logerror("M6801 '%s' Port 3 DDR is a write-only register\n", space.device().tag());
- break;
-
- case IO_P4DDR:
- data = m_port4_ddr;
- break;
-
- case IO_P3DATA:
- if (!machine().side_effect_disabled())
- {
- if (m_p3csr_is3_flag_read)
- {
- //logerror("M6801 '%s' Cleared IS3\n", space.device().tag());
- m_p3csr &= ~M6801_P3CSR_IS3_FLAG;
- m_p3csr_is3_flag_read = 0;
- }
-
- if (!(m_p3csr & M6801_P3CSR_OSS))
- {
- set_os3(ASSERT_LINE);
- }
- }
-
- if ((m_p3csr & M6801_P3CSR_LE) || (m_port3_ddr == 0xff))
- data = m_port3_data;
- else
- data = (m_io->read_byte(M6801_PORT3) & (m_port3_ddr ^ 0xff))
- | (m_port3_data & m_port3_ddr);
-
- if (!machine().side_effect_disabled())
- {
- m_port3_latched = 0;
-
- if (!(m_p3csr & M6801_P3CSR_OSS))
- {
- set_os3(CLEAR_LINE);
- }
- }
- break;
-
- case IO_P4DATA:
- if(m_port4_ddr == 0xff)
- data = m_port4_data;
- else
- data = (m_io->read_byte(M6801_PORT4) & (m_port4_ddr ^ 0xff))
- | (m_port4_data & m_port4_ddr);
- break;
-
- case IO_TCSR:
- m_pending_tcsr = 0;
- data = m_tcsr;
- break;
-
- case IO_CH:
- if(!(m_pending_tcsr&TCSR_TOF) && !machine().side_effect_disabled())
- {
- m_tcsr &= ~TCSR_TOF;
- MODIFIED_tcsr;
- }
- data = m_counter.b.h;
- break;
-
- case IO_CL:
- data = m_counter.b.l;
- // HACK there should be a break here, but Coleco Adam won't boot with it present, proper fix required to the free-running counter
-
- case IO_OCRH:
- if(!(m_pending_tcsr&TCSR_OCF) && !machine().side_effect_disabled())
- {
- m_tcsr &= ~TCSR_OCF;
- MODIFIED_tcsr;
- }
- data = m_output_compare.b.h;
- break;
-
- case IO_OCRL:
- if(!(m_pending_tcsr&TCSR_OCF) && !machine().side_effect_disabled())
- {
- m_tcsr &= ~TCSR_OCF;
- MODIFIED_tcsr;
- }
- data = m_output_compare.b.l;
- break;
-
- case IO_ICRH:
- if(!(m_pending_tcsr&TCSR_ICF) && !machine().side_effect_disabled())
- {
- m_tcsr &= ~TCSR_ICF;
- MODIFIED_tcsr;
- }
- data = (m_input_capture >> 0) & 0xff;
- break;
-
- case IO_ICRL:
- data = (m_input_capture >> 8) & 0xff;
- break;
-
- case IO_P3CSR:
- if ((m_p3csr & M6801_P3CSR_IS3_FLAG) && !machine().side_effect_disabled())
- {
- m_p3csr_is3_flag_read = 1;
- }
-
- data = m_p3csr;
- break;
-
- case IO_RMCR:
- data = m_rmcr;
- break;
-
- case IO_TRCSR:
- if (!machine().side_effect_disabled())
- {
- if (m_trcsr & M6800_TRCSR_TDRE)
- {
- m_trcsr_read_tdre = 1;
- }
-
- if (m_trcsr & M6800_TRCSR_ORFE)
- {
- m_trcsr_read_orfe = 1;
- }
-
- if (m_trcsr & M6800_TRCSR_RDRF)
- {
- m_trcsr_read_rdrf = 1;
- }
- }
-
- data = m_trcsr;
- break;
-
- case IO_RDR:
- if (!machine().side_effect_disabled())
- {
- if (m_trcsr_read_orfe)
- {
- //logerror("M6801 '%s' Cleared ORFE\n", space.device().tag());
- m_trcsr_read_orfe = 0;
- m_trcsr &= ~M6800_TRCSR_ORFE;
- }
-
- if (m_trcsr_read_rdrf)
- {
- //logerror("M6801 '%s' Cleared RDRF\n", space.device().tag());
- m_trcsr_read_rdrf = 0;
- m_trcsr &= ~M6800_TRCSR_RDRF;
- }
- }
-
- data = m_rdr;
- break;
-
- case IO_TDR:
- data = m_tdr;
- break;
-
- case IO_RCR:
- data = m_ram_ctrl;
- break;
-
- case IO_CAAH:
- case IO_CAAL:
- case IO_TCR1:
- case IO_TCR2:
- case IO_TSR:
- case IO_OCR2H:
- case IO_OCR2L:
- case IO_OCR3H:
- case IO_OCR3L:
- case IO_ICR2H:
- case IO_ICR2L:
- default:
- logerror("M6801 '%s' PC %04x: warning - read from reserved internal register %02x\n",space.device().tag(),space.device().safe_pc(),offset);
- }
-
- return data;
-}
-
-WRITE8_MEMBER( m6800_cpu_device::m6801_io_w )
-{
- switch (offset)
- {
- case IO_P1DDR:
- //logerror("M6801 '%s' Port 1 Data Direction Register: %02x\n", space.device().tag(), data);
-
- if (m_port1_ddr != data)
- {
- m_port1_ddr = data;
- if(m_port1_ddr == 0xff)
- m_io->write_byte(M6801_PORT1,m_port1_data);
- else
- m_io->write_byte(M6801_PORT1,(m_port1_data & m_port1_ddr) | (m_port1_ddr ^ 0xff));
- }
- break;
-
- case IO_P2DDR:
- //logerror("M6801 '%s' Port 2 Data Direction Register: %02x\n", space.device().tag(), data);
-
- if (m_port2_ddr != data)
- {
- m_port2_ddr = data;
- write_port2();
- }
- break;
-
- case IO_P1DATA:
- //logerror("M6801 '%s' Port 1 Data Register: %02x\n", space.device().tag(), data);
-
- m_port1_data = data;
- if(m_port1_ddr == 0xff)
- m_io->write_byte(M6801_PORT1,m_port1_data);
- else
- m_io->write_byte(M6801_PORT1,(m_port1_data & m_port1_ddr) | (m_port1_ddr ^ 0xff));
- break;
-
- case IO_P2DATA:
- //logerror("M6801 '%s' Port 2 Data Register: %02x\n", space.device().tag(), data);
-
- m_port2_data = data;
- m_port2_written = 1;
- write_port2();
- break;
-
- case IO_P3DDR:
- //logerror("M6801 '%s' Port 3 Data Direction Register: %02x\n", space.device().tag(), data);
-
- if (m_port3_ddr != data)
- {
- m_port3_ddr = data;
- if(m_port3_ddr == 0xff)
- m_io->write_byte(M6801_PORT3,m_port3_data);
- else
- m_io->write_byte(M6801_PORT3,(m_port3_data & m_port3_ddr) | (m_port3_ddr ^ 0xff));
- }
- break;
-
- case IO_P4DDR:
- //logerror("M6801 '%s' Port 4 Data Direction Register: %02x\n", space.device().tag(), data);
-
- if (m_port4_ddr != data)
- {
- m_port4_ddr = data;
- if(m_port4_ddr == 0xff)
- m_io->write_byte(M6801_PORT4,m_port4_data);
- else
- m_io->write_byte(M6801_PORT4,(m_port4_data & m_port4_ddr) | (m_port4_ddr ^ 0xff));
- }
- break;
-
- case IO_P3DATA:
- //logerror("M6801 '%s' Port 3 Data Register: %02x\n", space.device().tag(), data);
-
- if (m_p3csr_is3_flag_read)
- {
- //logerror("M6801 '%s' Cleared IS3\n", space.device().tag());
- m_p3csr &= ~M6801_P3CSR_IS3_FLAG;
- m_p3csr_is3_flag_read = 0;
- }
-
- if (m_p3csr & M6801_P3CSR_OSS)
- {
- set_os3(ASSERT_LINE);
- }
-
- m_port3_data = data;
- if(m_port3_ddr == 0xff)
- m_io->write_byte(M6801_PORT3,m_port3_data);
- else
- m_io->write_byte(M6801_PORT3,(m_port3_data & m_port3_ddr) | (m_port3_ddr ^ 0xff));
-
- if (m_p3csr & M6801_P3CSR_OSS)
- {
- set_os3(CLEAR_LINE);
- }
- break;
-
- case IO_P4DATA:
- //logerror("M6801 '%s' Port 4 Data Register: %02x\n", space.device().tag(), data);
-
- m_port4_data = data;
- if(m_port4_ddr == 0xff)
- m_io->write_byte(M6801_PORT4,m_port4_data);
- else
- m_io->write_byte(M6801_PORT4,(m_port4_data & m_port4_ddr) | (m_port4_ddr ^ 0xff));
- break;
-
- case IO_TCSR:
- //logerror("M6801 '%s' Timer Control and Status Register: %02x\n", space.device().tag(), data);
-
- m_tcsr = data;
- m_pending_tcsr &= m_tcsr;
- MODIFIED_tcsr;
- if( !(CC & 0x10) )
- m6800_check_irq2();
- break;
-
- case IO_CH:
- //logerror("M6801 '%s' Counter High Register: %02x\n", space.device().tag(), data);
-
- m_latch09 = data & 0xff; /* 6301 only */
- CT = 0xfff8;
- TOH = CTH;
- MODIFIED_counters;
- break;
-
- case IO_CL: /* 6301 only */
- //logerror("M6801 '%s' Counter Low Register: %02x\n", space.device().tag(), data);
-
- CT = (m_latch09 << 8) | (data & 0xff);
- TOH = CTH;
- MODIFIED_counters;
- break;
-
- case IO_OCRH:
- //logerror("M6801 '%s' Output Compare High Register: %02x\n", space.device().tag(), data);
-
- if( m_output_compare.b.h != data)
- {
- m_output_compare.b.h = data;
- MODIFIED_counters;
- }
- break;
-
- case IO_OCRL:
- //logerror("M6801 '%s' Output Compare Low Register: %02x\n", space.device().tag(), data);
-
- if( m_output_compare.b.l != data)
- {
- m_output_compare.b.l = data;
- MODIFIED_counters;
- }
- break;
-
- case IO_ICRH:
- case IO_ICRL:
- case IO_RDR:
- //logerror("CPU '%s' PC %04x: warning - write %02x to read only internal register %02x\n",space.device().tag(),space.device().safe_pc(),data,offset);
- break;
-
- case IO_P3CSR:
- //logerror("M6801 '%s' Port 3 Control and Status Register: %02x\n", space.device().tag(), data);
-
- m_p3csr = data;
- break;
-
- case IO_RMCR:
- //logerror("M6801 '%s' Rate and Mode Control Register: %02x\n", space.device().tag(), data);
-
- set_rmcr(data);
- break;
-
- case IO_TRCSR:
- //logerror("M6801 '%s' Transmit/Receive Control and Status Register: %02x\n", space.device().tag(), data);
-
- if ((data & M6800_TRCSR_TE) && !(m_trcsr & M6800_TRCSR_TE))
- {
- m_txstate = M6800_TX_STATE_INIT;
- m_txbits = 0;
- m_tx = 1;
- }
-
- if ((data & M6800_TRCSR_RE) && !(m_trcsr & M6800_TRCSR_RE))
- {
- m_rxbits = 0;
- }
-
- m_trcsr = (m_trcsr & 0xe0) | (data & 0x1f);
- break;
-
- case IO_TDR:
- //logerror("M6800 '%s' Transmit Data Register: %02x\n", space.device().tag(), data);
-
- if (m_trcsr_read_tdre)
- {
- m_trcsr_read_tdre = 0;
- m_trcsr &= ~M6800_TRCSR_TDRE;
- }
- m_tdr = data;
- break;
-
- case IO_RCR:
- //logerror("M6801 '%s' RAM Control Register: %02x\n", space.device().tag(), data);
-
- m_ram_ctrl = data;
- break;
-
- case IO_CAAH:
- case IO_CAAL:
- case IO_TCR1:
- case IO_TCR2:
- case IO_TSR:
- case IO_OCR2H:
- case IO_OCR2L:
- case IO_OCR3H:
- case IO_OCR3L:
- case IO_ICR2H:
- case IO_ICR2L:
- default:
- logerror("M6801 '%s' PC %04x: warning - write %02x to reserved internal register %02x\n",space.device().tag(),space.device().safe_pc(),data,offset);
- break;
- }
-}
-
-void m6801_cpu_device::m6801_clock_serial()
-{
- if (m_use_ext_serclock)
- {
- m_ext_serclock++;
-
- if (m_ext_serclock >= 8)
- {
- m_ext_serclock = 0;
- serial_transmit();
- serial_receive();
- }
- }
-}
-
offs_t m6800_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
{
extern CPU_DISASSEMBLE( m6800 );
@@ -1750,13 +581,6 @@ offs_t m6800_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, con
}
-offs_t m6801_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
-{
- extern CPU_DISASSEMBLE( m6801 );
- return CPU_DISASSEMBLE_NAME(m6801)(this, stream, pc, oprom, opram, options);
-}
-
-
offs_t m6802_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
{
extern CPU_DISASSEMBLE( m6802 );
@@ -1764,13 +588,6 @@ offs_t m6802_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, con
}
-offs_t m6803_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
-{
- extern CPU_DISASSEMBLE( m6803 );
- return CPU_DISASSEMBLE_NAME(m6803)(this, stream, pc, oprom, opram, options);
-}
-
-
offs_t m6808_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
{
extern CPU_DISASSEMBLE( m6808 );
@@ -1778,20 +595,6 @@ offs_t m6808_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, con
}
-offs_t hd6301_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
-{
- extern CPU_DISASSEMBLE( hd6301 );
- return CPU_DISASSEMBLE_NAME(hd6301)(this, stream, pc, oprom, opram, options);
-}
-
-
-offs_t hd63701_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
-{
- extern CPU_DISASSEMBLE( hd63701 );
- return CPU_DISASSEMBLE_NAME(hd63701)(this, stream, pc, oprom, opram, options);
-}
-
-
offs_t nsc8105_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
{
extern CPU_DISASSEMBLE( nsc8105 );
diff --git a/src/devices/cpu/m6800/m6800.h b/src/devices/cpu/m6800/m6800.h
index e4dee70b822..902f6bc2932 100644
--- a/src/devices/cpu/m6800/m6800.h
+++ b/src/devices/cpu/m6800/m6800.h
@@ -16,13 +16,7 @@ enum
enum
{
- M6800_IRQ_LINE = 0, /* IRQ line number */
- M6801_TIN_LINE, /* P20/Tin Input Capture line (eddge sense) */
- /* Active eddge is selecrable by internal reg. */
- /* raise eddge : CLEAR_LINE -> ASSERT_LINE */
- /* fall eddge : ASSERT_LINE -> CLEAR_LINE */
- /* it is usuali to use PULSE_LINE state */
- M6801_SC1_LINE
+ M6800_IRQ_LINE = 0 /* IRQ line number */
};
enum
@@ -32,45 +26,9 @@ enum
enum
{
- M6803_IRQ_LINE = M6800_IRQ_LINE
-};
-
-enum
-{
M6808_IRQ_LINE = M6800_IRQ_LINE
};
-enum
-{
- HD6301_IRQ_LINE = M6800_IRQ_LINE
-};
-
-enum
-{
- M6801_MODE_0 = 0,
- M6801_MODE_1,
- M6801_MODE_2,
- M6801_MODE_3,
- M6801_MODE_4,
- M6801_MODE_5,
- M6801_MODE_6,
- M6801_MODE_7
-};
-
-enum
-{
- M6801_PORT1 = 0x100,
- M6801_PORT2,
- M6801_PORT3,
- M6801_PORT4
-};
-
-
-#define MCFG_M6801_SC2(_devcb) \
- devcb = &m6800_cpu_device::set_out_sc2_func(*device, DEVCB_##_devcb);
-#define MCFG_M6801_SER_TX(_devcb) \
- devcb = &m6800_cpu_device::set_out_sertx_func(*device, DEVCB_##_devcb);
-
class m6800_cpu_device : public cpu_device
{
public:
@@ -79,15 +37,14 @@ public:
// construction/destruction
m6800_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- // static configuration helpers
- template<class _Object> static devcb_base &set_out_sc2_func(device_t &device, _Object object) { return downcast<m6800_cpu_device &>(device).m_out_sc2_func.set_callback(object); }
- template<class _Object> static devcb_base &set_out_sertx_func(device_t &device, _Object object) { return downcast<m6800_cpu_device &>(device).m_out_sertx_func.set_callback(object); }
-
- DECLARE_READ8_MEMBER( m6801_io_r );
- DECLARE_WRITE8_MEMBER( m6801_io_w );
-
protected:
- m6800_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, bool has_io, int clock_divider, const m6800_cpu_device::op_func *insn, const uint8_t *cycles, address_map_constructor internal);
+ enum
+ {
+ M6800_WAI = 8, /* set when WAI is waiting for an interrupt */
+ M6800_SLP = 0x10 /* HD63701 only */
+ };
+
+ m6800_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, const m6800_cpu_device::op_func *insn, const uint8_t *cycles, address_map_constructor internal);
// device-level overrides
virtual void device_start() override;
@@ -115,10 +72,6 @@ protected:
address_space_config m_program_config;
address_space_config m_decrypted_opcodes_config;
address_space_config m_io_config;
- bool m_has_io;
-
- devcb_write_line m_out_sc2_func;
- devcb_write_line m_out_sertx_func;
PAIR m_ppc; /* Previous program counter */
PAIR m_pc; /* Program counter */
@@ -130,74 +83,34 @@ protected:
uint8_t m_nmi_state; /* NMI line state */
uint8_t m_nmi_pending; /* NMI pending */
uint8_t m_irq_state[3]; /* IRQ line state [IRQ1,TIN,SC1] */
- uint8_t m_ic_eddge; /* InputCapture eddge , b.0=fall,b.1=raise */
- int m_sc1_state;
/* Memory spaces */
address_space *m_program, *m_decrypted_opcodes;
direct_read_data *m_direct, *m_decrypted_opcodes_direct;
- address_space *m_io;
const op_func *m_insn;
const uint8_t *m_cycles; /* clock cycle of instruction table */
- /* internal registers */
- uint8_t m_port1_ddr;
- uint8_t m_port2_ddr;
- uint8_t m_port3_ddr;
- uint8_t m_port4_ddr;
- uint8_t m_port1_data;
- uint8_t m_port2_data;
- uint8_t m_port3_data;
- uint8_t m_port4_data;
- uint8_t m_p3csr; // Port 3 Control/Status Register
- uint8_t m_tcsr; /* Timer Control and Status Register */
- uint8_t m_pending_tcsr; /* pending IRQ flag for clear IRQflag process */
- uint8_t m_irq2; /* IRQ2 flags */
- uint8_t m_ram_ctrl;
- PAIR m_counter; /* free running counter */
- PAIR m_output_compare; /* output compare */
- uint16_t m_input_capture; /* input capture */
- int m_p3csr_is3_flag_read;
- int m_port3_latched;
-
- int m_clock_divider;
- uint8_t m_trcsr, m_rmcr, m_rdr, m_tdr, m_rsr, m_tsr;
- int m_rxbits, m_txbits, m_txstate, m_trcsr_read_tdre, m_trcsr_read_orfe, m_trcsr_read_rdrf, m_tx, m_ext_serclock;
- bool m_use_ext_serclock;
- int m_port2_written;
int m_icount;
- int m_latch09;
- PAIR m_timer_over;
- emu_timer *m_sci_timer;
PAIR m_ea; /* effective address */
static const uint8_t flags8i[256];
static const uint8_t flags8d[256];
static const uint8_t cycles_6800[256];
- static const uint8_t cycles_6803[256];
- static const uint8_t cycles_63701[256];
static const uint8_t cycles_nsc8105[256];
static const op_func m6800_insn[256];
- static const op_func m6803_insn[256];
- static const op_func hd63701_insn[256];
static const op_func nsc8105_insn[256];
uint32_t RM16(uint32_t Addr );
void WM16(uint32_t Addr, PAIR *p );
void enter_interrupt(const char *message,uint16_t irq_vector);
- void m6800_check_irq2();
+ virtual void m6800_check_irq2() { }
void CHECK_IRQ_LINES();
- void check_timer_event();
- void increment_counter(int amount);
- void set_rmcr(uint8_t data);
- void write_port2();
- int m6800_rx();
- void serial_transmit();
- void serial_receive();
- TIMER_CALLBACK_MEMBER( sci_tick );
- void set_os3(int state);
+ virtual void increment_counter(int amount);
+ virtual void EAT_CYCLES();
+ virtual void CLEANUP_COUNTERS() { }
+ virtual void TAKE_TRAP() { }
void aba();
void abx();
@@ -451,22 +364,6 @@ protected:
};
-class m6801_cpu_device : public m6800_cpu_device
-{
-public:
- m6801_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-
- void m6801_clock_serial();
-
-protected:
- m6801_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, const m6800_cpu_device::op_func *insn, const uint8_t *cycles, address_map_constructor internal = nullptr);
-
- virtual uint64_t execute_clocks_to_cycles(uint64_t clocks) const override { return (clocks + 4 - 1) / 4; }
- virtual uint64_t execute_cycles_to_clocks(uint64_t cycles) const override { return (cycles * 4); }
- virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override;
-};
-
-
class m6802_cpu_device : public m6800_cpu_device
{
public:
@@ -481,16 +378,6 @@ protected:
};
-class m6803_cpu_device : public m6801_cpu_device
-{
-public:
- m6803_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-
-protected:
- virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override;
-};
-
-
class m6808_cpu_device : public m6802_cpu_device
{
public:
@@ -501,28 +388,6 @@ protected:
};
-class hd6301_cpu_device : public m6801_cpu_device
-{
-public:
- hd6301_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-
-protected:
- hd6301_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
-
- virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override;
-};
-
-
-class hd63701_cpu_device : public m6801_cpu_device
-{
-public:
- hd63701_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-
-protected:
- virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override;
-};
-
-
class nsc8105_cpu_device : public m6802_cpu_device
{
public:
@@ -533,38 +398,9 @@ protected:
};
-// DP-40 package: HD6303RP, HD63A03RP, HD63B03RP,
-// FP-54 package: HD6303RF, HD63A03RF, HD63B03RF,
-// CG-40 package: HD6303RCG, HD63A03RCG, HD63B03RCG,
-// Not fully emulated yet
-class hd6303r_cpu_device : public hd6301_cpu_device
-{
-public:
- hd6303r_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-};
-
-
-// DP-64S package: HD6303YP, HD63A03YP, HD63B03YP, HD63C03YP
-// FP-64 package: HD6303YF, HD63A03YF, HD63B03YF, HD63C03YF
-// FP-64A package: HD6303YH, HD63A03YH, HD63B03YH, HD63C03YH
-// CP-68 package: HD6303YCP, HD63A03YCP, HD63B03YCP, HD63C03YCP
-// Not fully emulated yet
-class hd6303y_cpu_device : public hd6301_cpu_device
-{
-public:
- hd6303y_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-};
-
-
DECLARE_DEVICE_TYPE(M6800, m6800_cpu_device)
-DECLARE_DEVICE_TYPE(M6801, m6801_cpu_device)
DECLARE_DEVICE_TYPE(M6802, m6802_cpu_device)
-DECLARE_DEVICE_TYPE(M6803, m6803_cpu_device)
DECLARE_DEVICE_TYPE(M6808, m6808_cpu_device)
-DECLARE_DEVICE_TYPE(HD6301, hd6301_cpu_device)
-DECLARE_DEVICE_TYPE(HD63701, hd63701_cpu_device)
DECLARE_DEVICE_TYPE(NSC8105, nsc8105_cpu_device)
-DECLARE_DEVICE_TYPE(HD6303R, hd6303r_cpu_device)
-DECLARE_DEVICE_TYPE(HD6303Y, hd6303y_cpu_device)
#endif // MAME_CPU_M6800_M6800_H
diff --git a/src/devices/cpu/m6800/m6801.cpp b/src/devices/cpu/m6800/m6801.cpp
new file mode 100644
index 00000000000..0ef6439cb83
--- /dev/null
+++ b/src/devices/cpu/m6800/m6801.cpp
@@ -0,0 +1,1296 @@
+// license:BSD-3-Clause
+// copyright-holders:Aaron Giles
+
+#include "emu.h"
+#include "cpu/m6800/m6801.h"
+
+
+#define CT m_counter.w.l
+#define CTH m_counter.w.h
+#define CTD m_counter.d
+#define OC m_output_compare.w.l
+#define OCH m_output_compare.w.h
+#define OCD m_output_compare.d
+#define TOH m_timer_over.w.l
+#define TOD m_timer_over.d
+
+#define MODIFIED_tcsr { \
+ m_irq2 = (m_tcsr&(m_tcsr<<3))&(TCSR_ICF|TCSR_OCF|TCSR_TOF); \
+}
+
+#define SET_TIMER_EVENT { \
+ m_timer_next = (OCD - CTD < TOD - CTD) ? OCD : TOD; \
+}
+
+/* when change freerunningcounter or outputcapture */
+#define MODIFIED_counters { \
+ OCH = (OC >= CT) ? CTH : CTH+1; \
+ SET_TIMER_EVENT; \
+}
+
+// I/O registers
+
+enum
+{
+ IO_P1DDR = 0,
+ IO_P2DDR,
+ IO_P1DATA,
+ IO_P2DATA,
+ IO_P3DDR,
+ IO_P4DDR,
+ IO_P3DATA,
+ IO_P4DATA,
+ IO_TCSR,
+ IO_CH,
+ IO_CL,
+ IO_OCRH,
+ IO_OCRL,
+ IO_ICRH,
+ IO_ICRL,
+ IO_P3CSR,
+ IO_RMCR,
+ IO_TRCSR,
+ IO_RDR,
+ IO_TDR,
+ IO_RCR,
+ IO_CAAH,
+ IO_CAAL,
+ IO_TCR1,
+ IO_TCR2,
+ IO_TSR,
+ IO_OCR2H,
+ IO_OCR2L,
+ IO_OCR3H,
+ IO_OCR3L,
+ IO_ICR2H,
+ IO_ICR2L
+};
+
+// serial I/O
+
+#define M6801_RMCR_SS_MASK 0x03 // Speed Select
+#define M6801_RMCR_SS_4096 0x03 // E / 4096
+#define M6801_RMCR_SS_1024 0x02 // E / 1024
+#define M6801_RMCR_SS_128 0x01 // E / 128
+#define M6801_RMCR_SS_16 0x00 // E / 16
+#define M6801_RMCR_CC_MASK 0x0c // Clock Control/Format Select
+
+#define M6801_TRCSR_RDRF 0x80 // Receive Data Register Full
+#define M6801_TRCSR_ORFE 0x40 // Over Run Framing Error
+#define M6801_TRCSR_TDRE 0x20 // Transmit Data Register Empty
+#define M6801_TRCSR_RIE 0x10 // Receive Interrupt Enable
+#define M6801_TRCSR_RE 0x08 // Receive Enable
+#define M6801_TRCSR_TIE 0x04 // Transmit Interrupt Enable
+#define M6801_TRCSR_TE 0x02 // Transmit Enable
+#define M6801_TRCSR_WU 0x01 // Wake Up
+
+#define M6801_PORT2_IO4 0x10
+#define M6801_PORT2_IO3 0x08
+
+#define M6801_P3CSR_LE 0x08
+#define M6801_P3CSR_OSS 0x10
+#define M6801_P3CSR_IS3_ENABLE 0x40
+#define M6801_P3CSR_IS3_FLAG 0x80
+
+static const int M6801_RMCR_SS[] = { 16, 128, 1024, 4096 };
+
+#define M6801_SERIAL_START 0
+#define M6801_SERIAL_STOP 9
+
+enum
+{
+ M6801_TX_STATE_INIT = 0,
+ M6801_TX_STATE_READY
+};
+
+/* take interrupt */
+#define TAKE_ICI enter_interrupt("M6800 '%s' take ICI\n",0xfff6)
+#define TAKE_OCI enter_interrupt("M6800 '%s' take OCI\n",0xfff4)
+#define TAKE_TOI enter_interrupt("M6800 '%s' take TOI\n",0xfff2)
+#define TAKE_SCI enter_interrupt("M6800 '%s' take SCI\n",0xfff0)
+
+/* mnemonicos for the Timer Control and Status Register bits */
+#define TCSR_OLVL 0x01
+#define TCSR_IEDG 0x02
+#define TCSR_ETOI 0x04
+#define TCSR_EOCI 0x08
+#define TCSR_EICI 0x10
+#define TCSR_TOF 0x20
+#define TCSR_OCF 0x40
+#define TCSR_ICF 0x80
+
+/* Note: don't use 0 cycles here for invalid opcodes so that we don't */
+/* hang in an infinite loop if we hit one */
+#define XX 5 // invalid opcode unknown cc
+const uint8_t m6801_cpu_device::cycles_6803[256] =
+{
+ /* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
+ /*0*/ XX, 2,XX,XX, 3, 3, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2,
+ /*1*/ 2, 2,XX,XX,XX,XX, 2, 2,XX, 2,XX, 2,XX,XX,XX,XX,
+ /*2*/ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ /*3*/ 3, 3, 4, 4, 3, 3, 3, 3, 5, 5, 3,10, 4,10, 9,12,
+ /*4*/ 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
+ /*5*/ 2,XX,XX, 2, 2,XX, 2, 2, 2, 2, 2,XX, 2, 2,XX, 2,
+ /*6*/ 6,XX,XX, 6, 6,XX, 6, 6, 6, 6, 6,XX, 6, 6, 3, 6,
+ /*7*/ 6,XX,XX, 6, 6,XX, 6, 6, 6, 6, 6,XX, 6, 6, 3, 6,
+ /*8*/ 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 4, 6, 3, 3,
+ /*9*/ 3, 3, 3, 5, 3, 3, 3, 3, 3, 3, 3, 3, 5, 5, 4, 4,
+ /*A*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 5, 5,
+ /*B*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 6, 5, 5,
+ /*C*/ 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 3,XX, 3, 3,
+ /*D*/ 3, 3, 3, 5, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4,
+ /*E*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
+ /*F*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5
+};
+
+const uint8_t m6801_cpu_device::cycles_63701[256] =
+{
+ /* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
+ /*0*/ XX, 1,XX,XX, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ /*1*/ 1, 1,XX,XX,XX,XX, 1, 1, 2, 2, 4, 1,XX,XX,XX,XX,
+ /*2*/ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+ /*3*/ 1, 1, 3, 3, 1, 1, 4, 4, 4, 5, 1,10, 5, 7, 9,12,
+ /*4*/ 1,XX,XX, 1, 1,XX, 1, 1, 1, 1, 1,XX, 1, 1,XX, 1,
+ /*5*/ 1,XX,XX, 1, 1,XX, 1, 1, 1, 1, 1,XX, 1, 1,XX, 1,
+ /*6*/ 6, 7, 7, 6, 6, 7, 6, 6, 6, 6, 6, 5, 6, 4, 3, 5,
+ /*7*/ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 4, 6, 4, 3, 5,
+ /*8*/ 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 2, 3, 5, 3, 3,
+ /*9*/ 3, 3, 3, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 5, 4, 4,
+ /*A*/ 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
+ /*B*/ 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 6, 5, 5,
+ /*C*/ 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 2, 3,XX, 3, 3,
+ /*D*/ 3, 3, 3, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4,
+ /*E*/ 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
+ /*F*/ 4, 4, 4, 5, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5
+};
+#undef XX // /invalid opcode unknown cc
+
+
+const m6800_cpu_device::op_func m6801_cpu_device::m6803_insn[0x100] = {
+&m6801_cpu_device::illegl1,&m6801_cpu_device::nop, &m6801_cpu_device::illegl1,&m6801_cpu_device::illegl1,&m6801_cpu_device::lsrd, &m6801_cpu_device::asld, &m6801_cpu_device::tap, &m6801_cpu_device::tpa,
+&m6801_cpu_device::inx, &m6801_cpu_device::dex, &m6801_cpu_device::clv, &m6801_cpu_device::sev, &m6801_cpu_device::clc, &m6801_cpu_device::sec, &m6801_cpu_device::cli, &m6801_cpu_device::sei,
+&m6801_cpu_device::sba, &m6801_cpu_device::cba, &m6801_cpu_device::illegl1,&m6801_cpu_device::illegl1,&m6801_cpu_device::illegl1,&m6801_cpu_device::illegl1,&m6801_cpu_device::tab, &m6801_cpu_device::tba,
+&m6801_cpu_device::illegl1,&m6801_cpu_device::daa, &m6801_cpu_device::illegl1,&m6801_cpu_device::aba, &m6801_cpu_device::illegl1,&m6801_cpu_device::illegl1,&m6801_cpu_device::illegl1,&m6801_cpu_device::illegl1,
+&m6801_cpu_device::bra, &m6801_cpu_device::brn, &m6801_cpu_device::bhi, &m6801_cpu_device::bls, &m6801_cpu_device::bcc, &m6801_cpu_device::bcs, &m6801_cpu_device::bne, &m6801_cpu_device::beq,
+&m6801_cpu_device::bvc, &m6801_cpu_device::bvs, &m6801_cpu_device::bpl, &m6801_cpu_device::bmi, &m6801_cpu_device::bge, &m6801_cpu_device::blt, &m6801_cpu_device::bgt, &m6801_cpu_device::ble,
+&m6801_cpu_device::tsx, &m6801_cpu_device::ins, &m6801_cpu_device::pula, &m6801_cpu_device::pulb, &m6801_cpu_device::des, &m6801_cpu_device::txs, &m6801_cpu_device::psha, &m6801_cpu_device::pshb,
+&m6801_cpu_device::pulx, &m6801_cpu_device::rts, &m6801_cpu_device::abx, &m6801_cpu_device::rti, &m6801_cpu_device::pshx, &m6801_cpu_device::mul, &m6801_cpu_device::wai, &m6801_cpu_device::swi,
+&m6801_cpu_device::nega, &m6801_cpu_device::illegl1,&m6801_cpu_device::illegl1,&m6801_cpu_device::coma, &m6801_cpu_device::lsra, &m6801_cpu_device::illegl1,&m6801_cpu_device::rora, &m6801_cpu_device::asra,
+&m6801_cpu_device::asla, &m6801_cpu_device::rola, &m6801_cpu_device::deca, &m6801_cpu_device::illegl1,&m6801_cpu_device::inca, &m6801_cpu_device::tsta, &m6801_cpu_device::illegl1,&m6801_cpu_device::clra,
+&m6801_cpu_device::negb, &m6801_cpu_device::illegl1,&m6801_cpu_device::illegl1,&m6801_cpu_device::comb, &m6801_cpu_device::lsrb, &m6801_cpu_device::illegl1,&m6801_cpu_device::rorb, &m6801_cpu_device::asrb,
+&m6801_cpu_device::aslb, &m6801_cpu_device::rolb, &m6801_cpu_device::decb, &m6801_cpu_device::illegl1,&m6801_cpu_device::incb, &m6801_cpu_device::tstb, &m6801_cpu_device::illegl1,&m6801_cpu_device::clrb,
+&m6801_cpu_device::neg_ix, &m6801_cpu_device::illegl1,&m6801_cpu_device::illegl1,&m6801_cpu_device::com_ix, &m6801_cpu_device::lsr_ix, &m6801_cpu_device::illegl1,&m6801_cpu_device::ror_ix, &m6801_cpu_device::asr_ix,
+&m6801_cpu_device::asl_ix, &m6801_cpu_device::rol_ix, &m6801_cpu_device::dec_ix, &m6801_cpu_device::illegl1,&m6801_cpu_device::inc_ix, &m6801_cpu_device::tst_ix, &m6801_cpu_device::jmp_ix, &m6801_cpu_device::clr_ix,
+&m6801_cpu_device::neg_ex, &m6801_cpu_device::illegl1,&m6801_cpu_device::illegl1,&m6801_cpu_device::com_ex, &m6801_cpu_device::lsr_ex, &m6801_cpu_device::illegl1,&m6801_cpu_device::ror_ex, &m6801_cpu_device::asr_ex,
+&m6801_cpu_device::asl_ex, &m6801_cpu_device::rol_ex, &m6801_cpu_device::dec_ex, &m6801_cpu_device::illegl1,&m6801_cpu_device::inc_ex, &m6801_cpu_device::tst_ex, &m6801_cpu_device::jmp_ex, &m6801_cpu_device::clr_ex,
+&m6801_cpu_device::suba_im,&m6801_cpu_device::cmpa_im,&m6801_cpu_device::sbca_im,&m6801_cpu_device::subd_im,&m6801_cpu_device::anda_im,&m6801_cpu_device::bita_im,&m6801_cpu_device::lda_im, &m6801_cpu_device::sta_im,
+&m6801_cpu_device::eora_im,&m6801_cpu_device::adca_im,&m6801_cpu_device::ora_im, &m6801_cpu_device::adda_im,&m6801_cpu_device::cpx_im ,&m6801_cpu_device::bsr, &m6801_cpu_device::lds_im, &m6801_cpu_device::sts_im,
+&m6801_cpu_device::suba_di,&m6801_cpu_device::cmpa_di,&m6801_cpu_device::sbca_di,&m6801_cpu_device::subd_di,&m6801_cpu_device::anda_di,&m6801_cpu_device::bita_di,&m6801_cpu_device::lda_di, &m6801_cpu_device::sta_di,
+&m6801_cpu_device::eora_di,&m6801_cpu_device::adca_di,&m6801_cpu_device::ora_di, &m6801_cpu_device::adda_di,&m6801_cpu_device::cpx_di ,&m6801_cpu_device::jsr_di, &m6801_cpu_device::lds_di, &m6801_cpu_device::sts_di,
+&m6801_cpu_device::suba_ix,&m6801_cpu_device::cmpa_ix,&m6801_cpu_device::sbca_ix,&m6801_cpu_device::subd_ix,&m6801_cpu_device::anda_ix,&m6801_cpu_device::bita_ix,&m6801_cpu_device::lda_ix, &m6801_cpu_device::sta_ix,
+&m6801_cpu_device::eora_ix,&m6801_cpu_device::adca_ix,&m6801_cpu_device::ora_ix, &m6801_cpu_device::adda_ix,&m6801_cpu_device::cpx_ix ,&m6801_cpu_device::jsr_ix, &m6801_cpu_device::lds_ix, &m6801_cpu_device::sts_ix,
+&m6801_cpu_device::suba_ex,&m6801_cpu_device::cmpa_ex,&m6801_cpu_device::sbca_ex,&m6801_cpu_device::subd_ex,&m6801_cpu_device::anda_ex,&m6801_cpu_device::bita_ex,&m6801_cpu_device::lda_ex, &m6801_cpu_device::sta_ex,
+&m6801_cpu_device::eora_ex,&m6801_cpu_device::adca_ex,&m6801_cpu_device::ora_ex, &m6801_cpu_device::adda_ex,&m6801_cpu_device::cpx_ex ,&m6801_cpu_device::jsr_ex, &m6801_cpu_device::lds_ex, &m6801_cpu_device::sts_ex,
+&m6801_cpu_device::subb_im,&m6801_cpu_device::cmpb_im,&m6801_cpu_device::sbcb_im,&m6801_cpu_device::addd_im,&m6801_cpu_device::andb_im,&m6801_cpu_device::bitb_im,&m6801_cpu_device::ldb_im, &m6801_cpu_device::stb_im,
+&m6801_cpu_device::eorb_im,&m6801_cpu_device::adcb_im,&m6801_cpu_device::orb_im, &m6801_cpu_device::addb_im,&m6801_cpu_device::ldd_im, &m6801_cpu_device::std_im, &m6801_cpu_device::ldx_im, &m6801_cpu_device::stx_im,
+&m6801_cpu_device::subb_di,&m6801_cpu_device::cmpb_di,&m6801_cpu_device::sbcb_di,&m6801_cpu_device::addd_di,&m6801_cpu_device::andb_di,&m6801_cpu_device::bitb_di,&m6801_cpu_device::ldb_di, &m6801_cpu_device::stb_di,
+&m6801_cpu_device::eorb_di,&m6801_cpu_device::adcb_di,&m6801_cpu_device::orb_di, &m6801_cpu_device::addb_di,&m6801_cpu_device::ldd_di, &m6801_cpu_device::std_di, &m6801_cpu_device::ldx_di, &m6801_cpu_device::stx_di,
+&m6801_cpu_device::subb_ix,&m6801_cpu_device::cmpb_ix,&m6801_cpu_device::sbcb_ix,&m6801_cpu_device::addd_ix,&m6801_cpu_device::andb_ix,&m6801_cpu_device::bitb_ix,&m6801_cpu_device::ldb_ix, &m6801_cpu_device::stb_ix,
+&m6801_cpu_device::eorb_ix,&m6801_cpu_device::adcb_ix,&m6801_cpu_device::orb_ix, &m6801_cpu_device::addb_ix,&m6801_cpu_device::ldd_ix, &m6801_cpu_device::std_ix, &m6801_cpu_device::ldx_ix, &m6801_cpu_device::stx_ix,
+&m6801_cpu_device::subb_ex,&m6801_cpu_device::cmpb_ex,&m6801_cpu_device::sbcb_ex,&m6801_cpu_device::addd_ex,&m6801_cpu_device::andb_ex,&m6801_cpu_device::bitb_ex,&m6801_cpu_device::ldb_ex, &m6801_cpu_device::stb_ex,
+&m6801_cpu_device::eorb_ex,&m6801_cpu_device::adcb_ex,&m6801_cpu_device::orb_ex, &m6801_cpu_device::addb_ex,&m6801_cpu_device::ldd_ex, &m6801_cpu_device::std_ex, &m6801_cpu_device::ldx_ex, &m6801_cpu_device::stx_ex
+};
+
+const m6800_cpu_device::op_func m6801_cpu_device::hd63701_insn[0x100] = {
+&m6801_cpu_device::trap, &m6801_cpu_device::nop, &m6801_cpu_device::trap, &m6801_cpu_device::trap, &m6801_cpu_device::lsrd, &m6801_cpu_device::asld, &m6801_cpu_device::tap, &m6801_cpu_device::tpa,
+&m6801_cpu_device::inx, &m6801_cpu_device::dex, &m6801_cpu_device::clv, &m6801_cpu_device::sev, &m6801_cpu_device::clc, &m6801_cpu_device::sec, &m6801_cpu_device::cli, &m6801_cpu_device::sei,
+&m6801_cpu_device::sba, &m6801_cpu_device::cba, &m6801_cpu_device::undoc1, &m6801_cpu_device::undoc2, &m6801_cpu_device::trap, &m6801_cpu_device::trap, &m6801_cpu_device::tab, &m6801_cpu_device::tba,
+&m6801_cpu_device::xgdx, &m6801_cpu_device::daa, &m6801_cpu_device::slp, &m6801_cpu_device::aba, &m6801_cpu_device::trap, &m6801_cpu_device::trap, &m6801_cpu_device::trap, &m6801_cpu_device::trap,
+&m6801_cpu_device::bra, &m6801_cpu_device::brn, &m6801_cpu_device::bhi, &m6801_cpu_device::bls, &m6801_cpu_device::bcc, &m6801_cpu_device::bcs, &m6801_cpu_device::bne, &m6801_cpu_device::beq,
+&m6801_cpu_device::bvc, &m6801_cpu_device::bvs, &m6801_cpu_device::bpl, &m6801_cpu_device::bmi, &m6801_cpu_device::bge, &m6801_cpu_device::blt, &m6801_cpu_device::bgt, &m6801_cpu_device::ble,
+&m6801_cpu_device::tsx, &m6801_cpu_device::ins, &m6801_cpu_device::pula, &m6801_cpu_device::pulb, &m6801_cpu_device::des, &m6801_cpu_device::txs, &m6801_cpu_device::psha, &m6801_cpu_device::pshb,
+&m6801_cpu_device::pulx, &m6801_cpu_device::rts, &m6801_cpu_device::abx, &m6801_cpu_device::rti, &m6801_cpu_device::pshx, &m6801_cpu_device::mul, &m6801_cpu_device::wai, &m6801_cpu_device::swi,
+&m6801_cpu_device::nega, &m6801_cpu_device::trap, &m6801_cpu_device::trap, &m6801_cpu_device::coma, &m6801_cpu_device::lsra, &m6801_cpu_device::trap, &m6801_cpu_device::rora, &m6801_cpu_device::asra,
+&m6801_cpu_device::asla, &m6801_cpu_device::rola, &m6801_cpu_device::deca, &m6801_cpu_device::trap, &m6801_cpu_device::inca, &m6801_cpu_device::tsta, &m6801_cpu_device::trap, &m6801_cpu_device::clra,
+&m6801_cpu_device::negb, &m6801_cpu_device::trap, &m6801_cpu_device::trap, &m6801_cpu_device::comb, &m6801_cpu_device::lsrb, &m6801_cpu_device::trap, &m6801_cpu_device::rorb, &m6801_cpu_device::asrb,
+&m6801_cpu_device::aslb, &m6801_cpu_device::rolb, &m6801_cpu_device::decb, &m6801_cpu_device::trap, &m6801_cpu_device::incb, &m6801_cpu_device::tstb, &m6801_cpu_device::trap, &m6801_cpu_device::clrb,
+&m6801_cpu_device::neg_ix, &m6801_cpu_device::aim_ix, &m6801_cpu_device::oim_ix, &m6801_cpu_device::com_ix, &m6801_cpu_device::lsr_ix, &m6801_cpu_device::eim_ix, &m6801_cpu_device::ror_ix, &m6801_cpu_device::asr_ix,
+&m6801_cpu_device::asl_ix, &m6801_cpu_device::rol_ix, &m6801_cpu_device::dec_ix, &m6801_cpu_device::tim_ix, &m6801_cpu_device::inc_ix, &m6801_cpu_device::tst_ix, &m6801_cpu_device::jmp_ix, &m6801_cpu_device::clr_ix,
+&m6801_cpu_device::neg_ex, &m6801_cpu_device::aim_di, &m6801_cpu_device::oim_di, &m6801_cpu_device::com_ex, &m6801_cpu_device::lsr_ex, &m6801_cpu_device::eim_di, &m6801_cpu_device::ror_ex, &m6801_cpu_device::asr_ex,
+&m6801_cpu_device::asl_ex, &m6801_cpu_device::rol_ex, &m6801_cpu_device::dec_ex, &m6801_cpu_device::tim_di, &m6801_cpu_device::inc_ex, &m6801_cpu_device::tst_ex, &m6801_cpu_device::jmp_ex, &m6801_cpu_device::clr_ex,
+&m6801_cpu_device::suba_im,&m6801_cpu_device::cmpa_im,&m6801_cpu_device::sbca_im,&m6801_cpu_device::subd_im,&m6801_cpu_device::anda_im,&m6801_cpu_device::bita_im,&m6801_cpu_device::lda_im, &m6801_cpu_device::sta_im,
+&m6801_cpu_device::eora_im,&m6801_cpu_device::adca_im,&m6801_cpu_device::ora_im, &m6801_cpu_device::adda_im,&m6801_cpu_device::cpx_im ,&m6801_cpu_device::bsr, &m6801_cpu_device::lds_im, &m6801_cpu_device::sts_im,
+&m6801_cpu_device::suba_di,&m6801_cpu_device::cmpa_di,&m6801_cpu_device::sbca_di,&m6801_cpu_device::subd_di,&m6801_cpu_device::anda_di,&m6801_cpu_device::bita_di,&m6801_cpu_device::lda_di, &m6801_cpu_device::sta_di,
+&m6801_cpu_device::eora_di,&m6801_cpu_device::adca_di,&m6801_cpu_device::ora_di, &m6801_cpu_device::adda_di,&m6801_cpu_device::cpx_di ,&m6801_cpu_device::jsr_di, &m6801_cpu_device::lds_di, &m6801_cpu_device::sts_di,
+&m6801_cpu_device::suba_ix,&m6801_cpu_device::cmpa_ix,&m6801_cpu_device::sbca_ix,&m6801_cpu_device::subd_ix,&m6801_cpu_device::anda_ix,&m6801_cpu_device::bita_ix,&m6801_cpu_device::lda_ix, &m6801_cpu_device::sta_ix,
+&m6801_cpu_device::eora_ix,&m6801_cpu_device::adca_ix,&m6801_cpu_device::ora_ix, &m6801_cpu_device::adda_ix,&m6801_cpu_device::cpx_ix ,&m6801_cpu_device::jsr_ix, &m6801_cpu_device::lds_ix, &m6801_cpu_device::sts_ix,
+&m6801_cpu_device::suba_ex,&m6801_cpu_device::cmpa_ex,&m6801_cpu_device::sbca_ex,&m6801_cpu_device::subd_ex,&m6801_cpu_device::anda_ex,&m6801_cpu_device::bita_ex,&m6801_cpu_device::lda_ex, &m6801_cpu_device::sta_ex,
+&m6801_cpu_device::eora_ex,&m6801_cpu_device::adca_ex,&m6801_cpu_device::ora_ex, &m6801_cpu_device::adda_ex,&m6801_cpu_device::cpx_ex ,&m6801_cpu_device::jsr_ex, &m6801_cpu_device::lds_ex, &m6801_cpu_device::sts_ex,
+&m6801_cpu_device::subb_im,&m6801_cpu_device::cmpb_im,&m6801_cpu_device::sbcb_im,&m6801_cpu_device::addd_im,&m6801_cpu_device::andb_im,&m6801_cpu_device::bitb_im,&m6801_cpu_device::ldb_im, &m6801_cpu_device::stb_im,
+&m6801_cpu_device::eorb_im,&m6801_cpu_device::adcb_im,&m6801_cpu_device::orb_im, &m6801_cpu_device::addb_im,&m6801_cpu_device::ldd_im, &m6801_cpu_device::std_im, &m6801_cpu_device::ldx_im, &m6801_cpu_device::stx_im,
+&m6801_cpu_device::subb_di,&m6801_cpu_device::cmpb_di,&m6801_cpu_device::sbcb_di,&m6801_cpu_device::addd_di,&m6801_cpu_device::andb_di,&m6801_cpu_device::bitb_di,&m6801_cpu_device::ldb_di, &m6801_cpu_device::stb_di,
+&m6801_cpu_device::eorb_di,&m6801_cpu_device::adcb_di,&m6801_cpu_device::orb_di, &m6801_cpu_device::addb_di,&m6801_cpu_device::ldd_di, &m6801_cpu_device::std_di, &m6801_cpu_device::ldx_di, &m6801_cpu_device::stx_di,
+&m6801_cpu_device::subb_ix,&m6801_cpu_device::cmpb_ix,&m6801_cpu_device::sbcb_ix,&m6801_cpu_device::addd_ix,&m6801_cpu_device::andb_ix,&m6801_cpu_device::bitb_ix,&m6801_cpu_device::ldb_ix, &m6801_cpu_device::stb_ix,
+&m6801_cpu_device::eorb_ix,&m6801_cpu_device::adcb_ix,&m6801_cpu_device::orb_ix, &m6801_cpu_device::addb_ix,&m6801_cpu_device::ldd_ix, &m6801_cpu_device::std_ix, &m6801_cpu_device::ldx_ix, &m6801_cpu_device::stx_ix,
+&m6801_cpu_device::subb_ex,&m6801_cpu_device::cmpb_ex,&m6801_cpu_device::sbcb_ex,&m6801_cpu_device::addd_ex,&m6801_cpu_device::andb_ex,&m6801_cpu_device::bitb_ex,&m6801_cpu_device::ldb_ex, &m6801_cpu_device::stb_ex,
+&m6801_cpu_device::eorb_ex,&m6801_cpu_device::adcb_ex,&m6801_cpu_device::orb_ex, &m6801_cpu_device::addb_ex,&m6801_cpu_device::ldd_ex, &m6801_cpu_device::std_ex, &m6801_cpu_device::ldx_ex, &m6801_cpu_device::stx_ex
+};
+
+
+static ADDRESS_MAP_START(m6803_mem, AS_PROGRAM, 8, m6801_cpu_device)
+ AM_RANGE(0x0000, 0x001f) AM_READWRITE(m6801_io_r, m6801_io_w)
+ AM_RANGE(0x0020, 0x007f) AM_NOP /* unused */
+ AM_RANGE(0x0080, 0x00ff) AM_RAM /* 6803 internal RAM */
+ADDRESS_MAP_END
+
+
+DEFINE_DEVICE_TYPE(M6801, m6801_cpu_device, "m6801", "M6801")
+DEFINE_DEVICE_TYPE(M6803, m6803_cpu_device, "m6803", "M6803")
+DEFINE_DEVICE_TYPE(HD6301, hd6301_cpu_device, "hd6301", "HD6301")
+DEFINE_DEVICE_TYPE(HD63701, hd63701_cpu_device, "hd63701", "HD63701")
+DEFINE_DEVICE_TYPE(HD6303R, hd6303r_cpu_device, "hd6304r", "HD6304R")
+DEFINE_DEVICE_TYPE(HD6303Y, hd6303y_cpu_device, "hd6303y", "HD6303Y")
+
+m6801_cpu_device::m6801_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : m6801_cpu_device(mconfig, M6801, tag, owner, clock, m6803_insn, cycles_6803, nullptr)
+{
+}
+
+m6801_cpu_device::m6801_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, const op_func *insn, const uint8_t *cycles, address_map_constructor internal)
+ : m6800_cpu_device(mconfig, type, tag, owner, clock, insn, cycles, internal)
+ , m_io_config("io", ENDIANNESS_BIG, 8, 9, 0)
+ , m_out_sc2_func(*this)
+ , m_out_sertx_func(*this)
+{
+}
+
+m6803_cpu_device::m6803_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : m6801_cpu_device(mconfig, M6803, tag, owner, clock, m6803_insn, cycles_6803, ADDRESS_MAP_NAME(m6803_mem))
+{
+}
+
+hd6301_cpu_device::hd6301_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : hd6301_cpu_device(mconfig, HD6301, tag, owner, clock)
+{
+}
+
+hd6301_cpu_device::hd6301_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+ : m6801_cpu_device(mconfig, type, tag, owner, clock, hd63701_insn, cycles_63701)
+{
+}
+
+hd63701_cpu_device::hd63701_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : m6801_cpu_device(mconfig, HD63701, tag, owner, clock, hd63701_insn, cycles_63701)
+{
+}
+
+hd6303r_cpu_device::hd6303r_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : hd6301_cpu_device(mconfig, HD6303R, tag, owner, clock)
+{
+}
+
+hd6303y_cpu_device::hd6303y_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : hd6301_cpu_device(mconfig, HD6303Y, tag, owner, clock)
+{
+}
+
+const address_space_config *m6801_cpu_device::memory_space_config(address_spacenum spacenum) const
+{
+ switch (spacenum)
+ {
+ case AS_IO: return &m_io_config;
+ default: return m6800_cpu_device::memory_space_config(spacenum);
+ }
+}
+
+
+void m6801_cpu_device::m6800_check_irq2()
+{
+ if ((m_tcsr & (TCSR_EICI|TCSR_ICF)) == (TCSR_EICI|TCSR_ICF))
+ {
+ TAKE_ICI;
+ standard_irq_callback(M6801_TIN_LINE);
+ }
+ else if ((m_tcsr & (TCSR_EOCI|TCSR_OCF)) == (TCSR_EOCI|TCSR_OCF))
+ {
+ TAKE_OCI;
+ }
+ else if ((m_tcsr & (TCSR_ETOI|TCSR_TOF)) == (TCSR_ETOI|TCSR_TOF))
+ {
+ TAKE_TOI;
+ }
+ else if (((m_trcsr & (M6801_TRCSR_RIE|M6801_TRCSR_RDRF)) == (M6801_TRCSR_RIE|M6801_TRCSR_RDRF)) ||
+ ((m_trcsr & (M6801_TRCSR_RIE|M6801_TRCSR_ORFE)) == (M6801_TRCSR_RIE|M6801_TRCSR_ORFE)) ||
+ ((m_trcsr & (M6801_TRCSR_TIE|M6801_TRCSR_TDRE)) == (M6801_TRCSR_TIE|M6801_TRCSR_TDRE)))
+ {
+ //logerror("M6800 '%s' SCI interrupt\n", tag());
+ TAKE_SCI;
+ }
+}
+
+/* check OCI or TOI */
+void m6801_cpu_device::check_timer_event()
+{
+ /* OCI */
+ if (CTD >= OCD)
+ {
+ OCH++; // next IRQ point
+ m_tcsr |= TCSR_OCF;
+ m_pending_tcsr |= TCSR_OCF;
+ MODIFIED_tcsr;
+ if((m_tcsr & TCSR_EOCI) && m_wai_state & M6800_SLP)
+ m_wai_state &= ~M6800_SLP;
+ if ( !(m_cc & 0x10) && (m_tcsr & TCSR_EOCI))
+ TAKE_OCI;
+
+ // if output on P21 is enabled, let's do it
+ if (m_port2_ddr & 2)
+ {
+ m_port2_data &= ~2;
+ m_port2_data |= (m_tcsr & TCSR_OLVL) << 1;
+ m_port2_written = 1;
+ write_port2();
+ }
+ }
+ /* TOI */
+ if (CTD >= TOD)
+ {
+ TOH++; // next IRQ point
+#if 0
+ CLEANUP_COUNTERS();
+#endif
+ m_tcsr |= TCSR_TOF;
+ m_pending_tcsr |= TCSR_TOF;
+ MODIFIED_tcsr;
+ if((m_tcsr & TCSR_ETOI) && m_wai_state & M6800_SLP)
+ m_wai_state &= ~M6800_SLP;
+ if ( !(m_cc & 0x10) && (m_tcsr & TCSR_ETOI))
+ TAKE_TOI;
+ }
+ /* set next event */
+ SET_TIMER_EVENT;
+}
+
+void m6801_cpu_device::increment_counter(int amount)
+{
+ m6800_cpu_device::increment_counter(amount);
+ CTD += amount;
+ if (CTD >= m_timer_next)
+ check_timer_event();
+}
+
+void m6801_cpu_device::EAT_CYCLES()
+{
+ int cycles_to_eat = std::min(int(m_timer_next - CTD), m_icount);
+ if (cycles_to_eat > 0)
+ increment_counter(cycles_to_eat);
+}
+
+/* cleanup high-word of counters */
+void m6801_cpu_device::CLEANUP_COUNTERS()
+{
+ OCH -= CTH;
+ TOH -= CTH;
+ CTH = 0;
+ SET_TIMER_EVENT;
+}
+
+void m6801_cpu_device::set_rmcr(uint8_t data)
+{
+ if (m_rmcr == data) return;
+
+ m_rmcr = data;
+
+ switch ((m_rmcr & M6801_RMCR_CC_MASK) >> 2)
+ {
+ case 0:
+ m_sci_timer->enable(false);
+ m_use_ext_serclock = false;
+ break;
+
+ case 3: // external clock
+ m_use_ext_serclock = true;
+ m_sci_timer->enable(false);
+ break;
+
+ case 1:
+ case 2:
+ {
+ int divisor = M6801_RMCR_SS[m_rmcr & M6801_RMCR_SS_MASK];
+ attotime period = cycles_to_attotime(divisor);
+
+ m_sci_timer->adjust(period, 0, period);
+ m_use_ext_serclock = false;
+ }
+ break;
+ }
+}
+
+int m6801_cpu_device::m6800_rx()
+{
+ return (m_io->read_byte(M6801_PORT2) & M6801_PORT2_IO3) >> 3;
+}
+
+void m6801_cpu_device::serial_transmit()
+{
+ //logerror("M6800 '%s' Tx Tick\n", tag());
+
+ if (m_trcsr & M6801_TRCSR_TE)
+ {
+ // force Port 2 bit 4 as output
+ m_port2_ddr |= M6801_PORT2_IO4;
+
+ switch (m_txstate)
+ {
+ case M6801_TX_STATE_INIT:
+ m_tx = 1;
+ m_txbits++;
+
+ if (m_txbits == 10)
+ {
+ m_txstate = M6801_TX_STATE_READY;
+ m_txbits = M6801_SERIAL_START;
+ }
+ break;
+
+ case M6801_TX_STATE_READY:
+ switch (m_txbits)
+ {
+ case M6801_SERIAL_START:
+ if (m_trcsr & M6801_TRCSR_TDRE)
+ {
+ // transmit buffer is empty, send nothing
+ return;
+ }
+ else
+ {
+ // transmit buffer is full, send data
+
+ // load TDR to shift register
+ m_tsr = m_tdr;
+
+ // transmit buffer is empty, set TDRE flag
+ m_trcsr |= M6801_TRCSR_TDRE;
+
+ // send start bit '0'
+ m_tx = 0;
+
+ m_txbits++;
+
+ //logerror("M6800 '%s' Transmit START Data %02x\n", tag(), m_tsr);
+ }
+ break;
+
+ case M6801_SERIAL_STOP:
+ // send stop bit '1'
+ m_tx = 1;
+
+ CHECK_IRQ_LINES();
+
+ m_txbits = M6801_SERIAL_START;
+
+ //logerror("M6800 '%s' Transmit STOP\n", tag());
+ break;
+
+ default:
+ // send data bit '0' or '1'
+ m_tx = m_tsr & 0x01;
+
+ // shift transmit register
+ m_tsr >>= 1;
+
+ //logerror("M6800 '%s' Transmit Bit %u: %u\n", tag(), m_txbits, m_tx);
+
+ m_txbits++;
+ break;
+ }
+ break;
+ }
+
+ m_out_sertx_func((m_tx == 1) ? ASSERT_LINE : CLEAR_LINE);
+ m_port2_written = 1;
+ write_port2();
+ }
+}
+
+void m6801_cpu_device::serial_receive()
+{
+ //logerror("M6800 '%s' Rx Tick TRCSR %02x bits %u check %02x\n", tag(), m_trcsr, m_rxbits, m_trcsr & M6801_TRCSR_RE);
+
+ if (m_trcsr & M6801_TRCSR_RE)
+ {
+ if (m_trcsr & M6801_TRCSR_WU)
+ {
+ // wait for 10 bits of '1'
+ if (m6800_rx() == 1)
+ {
+ m_rxbits++;
+
+ //logerror("M6800 '%s' Received WAKE UP bit %u\n", tag(), m_rxbits);
+
+ if (m_rxbits == 10)
+ {
+ //logerror("M6800 '%s' Receiver Wake Up\n", tag());
+
+ m_trcsr &= ~M6801_TRCSR_WU;
+ m_rxbits = M6801_SERIAL_START;
+ }
+ }
+ else
+ {
+ //logerror("M6800 '%s' Receiver Wake Up interrupted\n", tag());
+
+ m_rxbits = M6801_SERIAL_START;
+ }
+ }
+ else
+ {
+ // receive data
+ switch (m_rxbits)
+ {
+ case M6801_SERIAL_START:
+ if (m6800_rx() == 0)
+ {
+ // start bit found
+ m_rxbits++;
+
+ //logerror("M6800 '%s' Received START bit\n", tag());
+ }
+ break;
+
+ case M6801_SERIAL_STOP:
+ if (m6800_rx() == 1)
+ {
+ //logerror("M6800 '%s' Received STOP bit\n", tag());
+
+ if (m_trcsr & M6801_TRCSR_RDRF)
+ {
+ // overrun error
+ m_trcsr |= M6801_TRCSR_ORFE;
+
+ //logerror("M6800 '%s' Receive Overrun Error\n", tag());
+
+ CHECK_IRQ_LINES();
+ }
+ else
+ {
+ if (!(m_trcsr & M6801_TRCSR_ORFE))
+ {
+ // transfer data into receive register
+ m_rdr = m_rsr;
+
+ //logerror("M6800 '%s' Receive Data Register: %02x\n", tag(), m_rdr);
+
+ // set RDRF flag
+ m_trcsr |= M6801_TRCSR_RDRF;
+
+ CHECK_IRQ_LINES();
+ }
+ }
+ }
+ else
+ {
+ // framing error
+ if (!(m_trcsr & M6801_TRCSR_ORFE))
+ {
+ // transfer unframed data into receive register
+ m_rdr = m_rsr;
+ }
+
+ m_trcsr |= M6801_TRCSR_ORFE;
+ m_trcsr &= ~M6801_TRCSR_RDRF;
+
+ //logerror("M6800 '%s' Receive Framing Error\n", tag());
+
+ CHECK_IRQ_LINES();
+ }
+
+ m_rxbits = M6801_SERIAL_START;
+ break;
+
+ default:
+ // shift receive register
+ m_rsr >>= 1;
+
+ // receive bit into register
+ m_rsr |= (m6800_rx() << 7);
+
+ //logerror("M6800 '%s' Received DATA bit %u: %u\n", tag(), m_rxbits, BIT(m_rsr, 7));
+
+ m_rxbits++;
+ break;
+ }
+ }
+ }
+}
+
+TIMER_CALLBACK_MEMBER( m6801_cpu_device::sci_tick )
+{
+ serial_transmit();
+ serial_receive();
+}
+
+
+void m6801_cpu_device::execute_set_input(int irqline, int state)
+{
+ switch (irqline)
+ {
+ case M6801_SC1_LINE:
+ if (!m_port3_latched && (m_p3csr & M6801_P3CSR_LE))
+ {
+ if (!m_sc1_state && state)
+ {
+ // latch input data to port 3
+ m_port3_data = (m_io->read_byte(M6801_PORT3) & (m_port3_ddr ^ 0xff)) | (m_port3_data & m_port3_ddr);
+ m_port3_latched = 1;
+ //logerror("M6801 '%s' Latched Port 3 Data: %02x\n", tag(), m_port3_data);
+
+ // set IS3 flag bit
+ m_p3csr |= M6801_P3CSR_IS3_FLAG;
+ }
+ }
+ m_sc1_state = state;
+ break;
+
+ case M6801_TIN_LINE:
+ m_irq_state[M6801_TIN_LINE] = state;
+
+ if (state != m_irq_state[M6801_TIN_LINE])
+ {
+ //eddge = (state == CLEAR_LINE ) ? 2 : 0;
+ if( ((m_tcsr&TCSR_IEDG) ^ (state==CLEAR_LINE ? TCSR_IEDG : 0))==0 )
+ return;
+ /* active edge in */
+ m_tcsr |= TCSR_ICF;
+ m_pending_tcsr |= TCSR_ICF;
+ m_input_capture = CT;
+ MODIFIED_tcsr;
+ }
+ break;
+
+ default:
+ m6800_cpu_device::execute_set_input(irqline, state);
+ break;
+ }
+}
+
+
+void m6801_cpu_device::device_start()
+{
+ m6800_cpu_device::device_start();
+
+ m_io = &space(AS_IO);
+
+ m_out_sc2_func.resolve_safe();
+ m_out_sertx_func.resolve_safe();
+ m_sci_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(m6801_cpu_device::sci_tick),this));
+
+ m_port4_ddr = 0;
+ m_port4_data = 0;
+ m_input_capture = 0;
+ m_rdr = 0;
+ m_tdr = 0;
+ m_rmcr = 0;
+ m_ram_ctrl = 0;
+
+ save_item(NAME(m_port1_ddr));
+ save_item(NAME(m_port2_ddr));
+ save_item(NAME(m_port3_ddr));
+ save_item(NAME(m_port4_ddr));
+ save_item(NAME(m_port1_data));
+ save_item(NAME(m_port2_data));
+ save_item(NAME(m_port3_data));
+ save_item(NAME(m_port4_data));
+ save_item(NAME(m_port2_written));
+ save_item(NAME(m_port3_latched));
+ save_item(NAME(m_p3csr));
+ save_item(NAME(m_p3csr_is3_flag_read));
+ save_item(NAME(m_tcsr));
+ save_item(NAME(m_pending_tcsr));
+ save_item(NAME(m_irq2));
+ save_item(NAME(m_ram_ctrl));
+
+ save_item(NAME(m_counter.d));
+ save_item(NAME(m_output_compare.d));
+ save_item(NAME(m_input_capture));
+ save_item(NAME(m_timer_over.d));
+ save_item(NAME(m_timer_next));
+
+ save_item(NAME(m_trcsr));
+ save_item(NAME(m_rmcr));
+ save_item(NAME(m_rdr));
+ save_item(NAME(m_tdr));
+ save_item(NAME(m_rsr));
+ save_item(NAME(m_tsr));
+ save_item(NAME(m_rxbits));
+ save_item(NAME(m_txbits));
+ save_item(NAME(m_txstate));
+ save_item(NAME(m_trcsr_read_tdre));
+ save_item(NAME(m_trcsr_read_orfe));
+ save_item(NAME(m_trcsr_read_rdrf));
+ save_item(NAME(m_tx));
+
+ save_item(NAME(m_sc1_state));
+}
+
+void m6801_cpu_device::device_reset()
+{
+ m6800_cpu_device::device_reset();
+
+ m_irq_state[M6801_TIN_LINE] = 0;
+ m_sc1_state = 0;
+
+ m_port1_ddr = 0x00;
+ m_port2_ddr = 0x00;
+ m_port3_ddr = 0x00;
+ m_port1_data = 0;
+ m_p3csr = 0x00;
+ m_p3csr_is3_flag_read = 0;
+ m_port2_written = 0;
+ m_port3_latched = 0;
+ /* TODO: on reset port 2 should be read to determine the operating mode (bits 0-2) */
+ m_tcsr = 0x00;
+ m_pending_tcsr = 0x00;
+ m_irq2 = 0;
+ CTD = 0x0000;
+ OCD = 0xffff;
+ TOD = 0xffff;
+ m_timer_next = 0xffff;
+ m_ram_ctrl |= 0x40;
+ m_latch09 = 0;
+
+ m_trcsr = M6801_TRCSR_TDRE;
+
+ m_txstate = M6801_TX_STATE_INIT;
+ m_txbits = m_rxbits = 0;
+ m_tx = 1;
+ m_trcsr_read_tdre = 0;
+ m_trcsr_read_orfe = 0;
+ m_trcsr_read_rdrf = 0;
+ m_ext_serclock = 0;
+ m_use_ext_serclock = false;
+
+ set_rmcr(0);
+}
+
+
+void m6801_cpu_device::write_port2()
+{
+ if (!m_port2_written) return;
+
+ uint8_t data = m_port2_data;
+ uint8_t ddr = m_port2_ddr & 0x1f;
+
+ if ((ddr != 0x1f) && ddr)
+ {
+ data = (m_port2_data & ddr) | (ddr ^ 0xff);
+ }
+
+ if (m_trcsr & M6801_TRCSR_TE)
+ {
+ data = (data & 0xef) | (m_tx << 4);
+ }
+
+ data &= 0x1f;
+
+ m_io->write_byte(M6801_PORT2, data);
+}
+
+/*
+ if change_pc() direccted these areas ,Call hd63701_trap_pc().
+ 'mode' is selected by the sense of p2.0,p2.1,and p2.3 at reset timming.
+ mode 0,1,2,4,6 : $0000-$001f
+ mode 5 : $0000-$001f,$0200-$efff
+ mode 7 : $0000-$001f,$0100-$efff
+*/
+
+void m6801_cpu_device::set_os3(int state)
+{
+ //logerror("M6801 '%s' OS3: %u\n", tag(), state);
+
+ m_out_sc2_func(state);
+}
+
+READ8_MEMBER( m6801_cpu_device::m6801_io_r )
+{
+ uint8_t data = 0;
+
+ switch (offset)
+ {
+ case IO_P1DDR:
+ data = m_port1_ddr;
+ break;
+
+ case IO_P2DDR:
+ data = m_port2_ddr;
+ break;
+
+ case IO_P1DATA:
+ if(m_port1_ddr == 0xff)
+ data = m_port1_data;
+ else
+ data = (m_io->read_byte(M6801_PORT1) & (m_port1_ddr ^ 0xff))
+ | (m_port1_data & m_port1_ddr);
+ break;
+
+ case IO_P2DATA:
+ if(m_port2_ddr == 0xff)
+ data = m_port2_data;
+ else
+ data = (m_io->read_byte(M6801_PORT2) & (m_port2_ddr ^ 0xff))
+ | (m_port2_data & m_port2_ddr);
+ break;
+
+ case IO_P3DDR:
+ logerror("M6801 '%s' Port 3 DDR is a write-only register\n", space.device().tag());
+ break;
+
+ case IO_P4DDR:
+ data = m_port4_ddr;
+ break;
+
+ case IO_P3DATA:
+ if (!machine().side_effect_disabled())
+ {
+ if (m_p3csr_is3_flag_read)
+ {
+ //logerror("M6801 '%s' Cleared IS3\n", space.device().tag());
+ m_p3csr &= ~M6801_P3CSR_IS3_FLAG;
+ m_p3csr_is3_flag_read = 0;
+ }
+
+ if (!(m_p3csr & M6801_P3CSR_OSS))
+ {
+ set_os3(ASSERT_LINE);
+ }
+ }
+
+ if ((m_p3csr & M6801_P3CSR_LE) || (m_port3_ddr == 0xff))
+ data = m_port3_data;
+ else
+ data = (m_io->read_byte(M6801_PORT3) & (m_port3_ddr ^ 0xff))
+ | (m_port3_data & m_port3_ddr);
+
+ if (!machine().side_effect_disabled())
+ {
+ m_port3_latched = 0;
+
+ if (!(m_p3csr & M6801_P3CSR_OSS))
+ {
+ set_os3(CLEAR_LINE);
+ }
+ }
+ break;
+
+ case IO_P4DATA:
+ if(m_port4_ddr == 0xff)
+ data = m_port4_data;
+ else
+ data = (m_io->read_byte(M6801_PORT4) & (m_port4_ddr ^ 0xff))
+ | (m_port4_data & m_port4_ddr);
+ break;
+
+ case IO_TCSR:
+ m_pending_tcsr = 0;
+ data = m_tcsr;
+ break;
+
+ case IO_CH:
+ if(!(m_pending_tcsr&TCSR_TOF) && !machine().side_effect_disabled())
+ {
+ m_tcsr &= ~TCSR_TOF;
+ MODIFIED_tcsr;
+ }
+ data = m_counter.b.h;
+ break;
+
+ case IO_CL:
+ data = m_counter.b.l;
+ // HACK there should be a break here, but Coleco Adam won't boot with it present, proper fix required to the free-running counter
+
+ case IO_OCRH:
+ if(!(m_pending_tcsr&TCSR_OCF) && !machine().side_effect_disabled())
+ {
+ m_tcsr &= ~TCSR_OCF;
+ MODIFIED_tcsr;
+ }
+ data = m_output_compare.b.h;
+ break;
+
+ case IO_OCRL:
+ if(!(m_pending_tcsr&TCSR_OCF) && !machine().side_effect_disabled())
+ {
+ m_tcsr &= ~TCSR_OCF;
+ MODIFIED_tcsr;
+ }
+ data = m_output_compare.b.l;
+ break;
+
+ case IO_ICRH:
+ if(!(m_pending_tcsr&TCSR_ICF) && !machine().side_effect_disabled())
+ {
+ m_tcsr &= ~TCSR_ICF;
+ MODIFIED_tcsr;
+ }
+ data = (m_input_capture >> 0) & 0xff;
+ break;
+
+ case IO_ICRL:
+ data = (m_input_capture >> 8) & 0xff;
+ break;
+
+ case IO_P3CSR:
+ if ((m_p3csr & M6801_P3CSR_IS3_FLAG) && !machine().side_effect_disabled())
+ {
+ m_p3csr_is3_flag_read = 1;
+ }
+
+ data = m_p3csr;
+ break;
+
+ case IO_RMCR:
+ data = m_rmcr;
+ break;
+
+ case IO_TRCSR:
+ if (!machine().side_effect_disabled())
+ {
+ if (m_trcsr & M6801_TRCSR_TDRE)
+ {
+ m_trcsr_read_tdre = 1;
+ }
+
+ if (m_trcsr & M6801_TRCSR_ORFE)
+ {
+ m_trcsr_read_orfe = 1;
+ }
+
+ if (m_trcsr & M6801_TRCSR_RDRF)
+ {
+ m_trcsr_read_rdrf = 1;
+ }
+ }
+
+ data = m_trcsr;
+ break;
+
+ case IO_RDR:
+ if (!machine().side_effect_disabled())
+ {
+ if (m_trcsr_read_orfe)
+ {
+ //logerror("M6801 '%s' Cleared ORFE\n", space.device().tag());
+ m_trcsr_read_orfe = 0;
+ m_trcsr &= ~M6801_TRCSR_ORFE;
+ }
+
+ if (m_trcsr_read_rdrf)
+ {
+ //logerror("M6801 '%s' Cleared RDRF\n", space.device().tag());
+ m_trcsr_read_rdrf = 0;
+ m_trcsr &= ~M6801_TRCSR_RDRF;
+ }
+ }
+
+ data = m_rdr;
+ break;
+
+ case IO_TDR:
+ data = m_tdr;
+ break;
+
+ case IO_RCR:
+ data = m_ram_ctrl;
+ break;
+
+ case IO_CAAH:
+ case IO_CAAL:
+ case IO_TCR1:
+ case IO_TCR2:
+ case IO_TSR:
+ case IO_OCR2H:
+ case IO_OCR2L:
+ case IO_OCR3H:
+ case IO_OCR3L:
+ case IO_ICR2H:
+ case IO_ICR2L:
+ default:
+ logerror("M6801 '%s' PC %04x: warning - read from reserved internal register %02x\n",space.device().tag(),space.device().safe_pc(),offset);
+ }
+
+ return data;
+}
+
+WRITE8_MEMBER( m6801_cpu_device::m6801_io_w )
+{
+ switch (offset)
+ {
+ case IO_P1DDR:
+ //logerror("M6801 '%s' Port 1 Data Direction Register: %02x\n", space.device().tag(), data);
+
+ if (m_port1_ddr != data)
+ {
+ m_port1_ddr = data;
+ if(m_port1_ddr == 0xff)
+ m_io->write_byte(M6801_PORT1,m_port1_data);
+ else
+ m_io->write_byte(M6801_PORT1,(m_port1_data & m_port1_ddr) | (m_port1_ddr ^ 0xff));
+ }
+ break;
+
+ case IO_P2DDR:
+ //logerror("M6801 '%s' Port 2 Data Direction Register: %02x\n", space.device().tag(), data);
+
+ if (m_port2_ddr != data)
+ {
+ m_port2_ddr = data;
+ write_port2();
+ }
+ break;
+
+ case IO_P1DATA:
+ //logerror("M6801 '%s' Port 1 Data Register: %02x\n", space.device().tag(), data);
+
+ m_port1_data = data;
+ if(m_port1_ddr == 0xff)
+ m_io->write_byte(M6801_PORT1,m_port1_data);
+ else
+ m_io->write_byte(M6801_PORT1,(m_port1_data & m_port1_ddr) | (m_port1_ddr ^ 0xff));
+ break;
+
+ case IO_P2DATA:
+ //logerror("M6801 '%s' Port 2 Data Register: %02x\n", space.device().tag(), data);
+
+ m_port2_data = data;
+ m_port2_written = 1;
+ write_port2();
+ break;
+
+ case IO_P3DDR:
+ //logerror("M6801 '%s' Port 3 Data Direction Register: %02x\n", space.device().tag(), data);
+
+ if (m_port3_ddr != data)
+ {
+ m_port3_ddr = data;
+ if(m_port3_ddr == 0xff)
+ m_io->write_byte(M6801_PORT3,m_port3_data);
+ else
+ m_io->write_byte(M6801_PORT3,(m_port3_data & m_port3_ddr) | (m_port3_ddr ^ 0xff));
+ }
+ break;
+
+ case IO_P4DDR:
+ //logerror("M6801 '%s' Port 4 Data Direction Register: %02x\n", space.device().tag(), data);
+
+ if (m_port4_ddr != data)
+ {
+ m_port4_ddr = data;
+ if(m_port4_ddr == 0xff)
+ m_io->write_byte(M6801_PORT4,m_port4_data);
+ else
+ m_io->write_byte(M6801_PORT4,(m_port4_data & m_port4_ddr) | (m_port4_ddr ^ 0xff));
+ }
+ break;
+
+ case IO_P3DATA:
+ //logerror("M6801 '%s' Port 3 Data Register: %02x\n", space.device().tag(), data);
+
+ if (m_p3csr_is3_flag_read)
+ {
+ //logerror("M6801 '%s' Cleared IS3\n", space.device().tag());
+ m_p3csr &= ~M6801_P3CSR_IS3_FLAG;
+ m_p3csr_is3_flag_read = 0;
+ }
+
+ if (m_p3csr & M6801_P3CSR_OSS)
+ {
+ set_os3(ASSERT_LINE);
+ }
+
+ m_port3_data = data;
+ if(m_port3_ddr == 0xff)
+ m_io->write_byte(M6801_PORT3,m_port3_data);
+ else
+ m_io->write_byte(M6801_PORT3,(m_port3_data & m_port3_ddr) | (m_port3_ddr ^ 0xff));
+
+ if (m_p3csr & M6801_P3CSR_OSS)
+ {
+ set_os3(CLEAR_LINE);
+ }
+ break;
+
+ case IO_P4DATA:
+ //logerror("M6801 '%s' Port 4 Data Register: %02x\n", space.device().tag(), data);
+
+ m_port4_data = data;
+ if(m_port4_ddr == 0xff)
+ m_io->write_byte(M6801_PORT4,m_port4_data);
+ else
+ m_io->write_byte(M6801_PORT4,(m_port4_data & m_port4_ddr) | (m_port4_ddr ^ 0xff));
+ break;
+
+ case IO_TCSR:
+ //logerror("M6801 '%s' Timer Control and Status Register: %02x\n", space.device().tag(), data);
+
+ m_tcsr = data;
+ m_pending_tcsr &= m_tcsr;
+ MODIFIED_tcsr;
+ if( !(m_cc & 0x10) )
+ m6800_check_irq2();
+ break;
+
+ case IO_CH:
+ //logerror("M6801 '%s' Counter High Register: %02x\n", space.device().tag(), data);
+
+ m_latch09 = data & 0xff; /* 6301 only */
+ CT = 0xfff8;
+ TOH = CTH;
+ MODIFIED_counters;
+ break;
+
+ case IO_CL: /* 6301 only */
+ //logerror("M6801 '%s' Counter Low Register: %02x\n", space.device().tag(), data);
+
+ CT = (m_latch09 << 8) | (data & 0xff);
+ TOH = CTH;
+ MODIFIED_counters;
+ break;
+
+ case IO_OCRH:
+ //logerror("M6801 '%s' Output Compare High Register: %02x\n", space.device().tag(), data);
+
+ if( m_output_compare.b.h != data)
+ {
+ m_output_compare.b.h = data;
+ MODIFIED_counters;
+ }
+ break;
+
+ case IO_OCRL:
+ //logerror("M6801 '%s' Output Compare Low Register: %02x\n", space.device().tag(), data);
+
+ if( m_output_compare.b.l != data)
+ {
+ m_output_compare.b.l = data;
+ MODIFIED_counters;
+ }
+ break;
+
+ case IO_ICRH:
+ case IO_ICRL:
+ case IO_RDR:
+ //logerror("CPU '%s' PC %04x: warning - write %02x to read only internal register %02x\n",space.device().tag(),space.device().safe_pc(),data,offset);
+ break;
+
+ case IO_P3CSR:
+ //logerror("M6801 '%s' Port 3 Control and Status Register: %02x\n", space.device().tag(), data);
+
+ m_p3csr = data;
+ break;
+
+ case IO_RMCR:
+ //logerror("M6801 '%s' Rate and Mode Control Register: %02x\n", space.device().tag(), data);
+
+ set_rmcr(data);
+ break;
+
+ case IO_TRCSR:
+ //logerror("M6801 '%s' Transmit/Receive Control and Status Register: %02x\n", space.device().tag(), data);
+
+ if ((data & M6801_TRCSR_TE) && !(m_trcsr & M6801_TRCSR_TE))
+ {
+ m_txstate = M6801_TX_STATE_INIT;
+ m_txbits = 0;
+ m_tx = 1;
+ }
+
+ if ((data & M6801_TRCSR_RE) && !(m_trcsr & M6801_TRCSR_RE))
+ {
+ m_rxbits = 0;
+ }
+
+ m_trcsr = (m_trcsr & 0xe0) | (data & 0x1f);
+ break;
+
+ case IO_TDR:
+ //logerror("M6800 '%s' Transmit Data Register: %02x\n", space.device().tag(), data);
+
+ if (m_trcsr_read_tdre)
+ {
+ m_trcsr_read_tdre = 0;
+ m_trcsr &= ~M6801_TRCSR_TDRE;
+ }
+ m_tdr = data;
+ break;
+
+ case IO_RCR:
+ //logerror("M6801 '%s' RAM Control Register: %02x\n", space.device().tag(), data);
+
+ m_ram_ctrl = data;
+ break;
+
+ case IO_CAAH:
+ case IO_CAAL:
+ case IO_TCR1:
+ case IO_TCR2:
+ case IO_TSR:
+ case IO_OCR2H:
+ case IO_OCR2L:
+ case IO_OCR3H:
+ case IO_OCR3L:
+ case IO_ICR2H:
+ case IO_ICR2L:
+ default:
+ logerror("M6801 '%s' PC %04x: warning - write %02x to reserved internal register %02x\n",space.device().tag(),space.device().safe_pc(),data,offset);
+ break;
+ }
+}
+
+
+void m6801_cpu_device::m6801_clock_serial()
+{
+ if (m_use_ext_serclock)
+ {
+ m_ext_serclock++;
+
+ if (m_ext_serclock >= 8)
+ {
+ m_ext_serclock = 0;
+ serial_transmit();
+ serial_receive();
+ }
+ }
+}
+
+
+offs_t m6801_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
+{
+ extern CPU_DISASSEMBLE( m6801 );
+ return CPU_DISASSEMBLE_NAME(m6801)(this, stream, pc, oprom, opram, options);
+}
+
+
+offs_t m6803_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
+{
+ extern CPU_DISASSEMBLE( m6803 );
+ return CPU_DISASSEMBLE_NAME(m6803)(this, stream, pc, oprom, opram, options);
+}
+
+
+offs_t hd6301_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
+{
+ extern CPU_DISASSEMBLE( hd6301 );
+ return CPU_DISASSEMBLE_NAME(hd6301)(this, stream, pc, oprom, opram, options);
+}
+
+
+offs_t hd63701_cpu_device::disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options)
+{
+ extern CPU_DISASSEMBLE( hd63701 );
+ return CPU_DISASSEMBLE_NAME(hd63701)(this, stream, pc, oprom, opram, options);
+}
+
+void hd63701_cpu_device::TAKE_TRAP()
+{
+ enter_interrupt("M6800 '%s' take TRAP\n",0xffee);
+}
diff --git a/src/devices/cpu/m6800/m6801.h b/src/devices/cpu/m6800/m6801.h
new file mode 100644
index 00000000000..23bc7b4a28a
--- /dev/null
+++ b/src/devices/cpu/m6800/m6801.h
@@ -0,0 +1,219 @@
+// license:BSD-3-Clause
+// copyright-holders:Aaron Giles
+
+#ifndef MAME_CPU_M6800_M6801_H
+#define MAME_CPU_M6800_M6801_H
+
+#pragma once
+
+#include "cpu/m6800/m6800.h"
+
+
+enum
+{
+ M6801_IRQ_LINE = M6800_IRQ_LINE,
+ M6801_TIN_LINE, /* P20/Tin Input Capture line (eddge sense) */
+ /* Active eddge is selecrable by internal reg. */
+ /* raise eddge : CLEAR_LINE -> ASSERT_LINE */
+ /* fall eddge : ASSERT_LINE -> CLEAR_LINE */
+ /* it is usuali to use PULSE_LINE state */
+ M6801_SC1_LINE
+};
+
+enum
+{
+ M6803_IRQ_LINE = M6800_IRQ_LINE
+};
+
+enum
+{
+ HD6301_IRQ_LINE = M6800_IRQ_LINE
+};
+
+enum
+{
+ M6801_MODE_0 = 0,
+ M6801_MODE_1,
+ M6801_MODE_2,
+ M6801_MODE_3,
+ M6801_MODE_4,
+ M6801_MODE_5,
+ M6801_MODE_6,
+ M6801_MODE_7
+};
+
+enum
+{
+ M6801_PORT1 = 0x100,
+ M6801_PORT2,
+ M6801_PORT3,
+ M6801_PORT4
+};
+
+
+#define MCFG_M6801_SC2(_devcb) \
+ devcb = &m6801_cpu_device::set_out_sc2_func(*device, DEVCB_##_devcb);
+#define MCFG_M6801_SER_TX(_devcb) \
+ devcb = &m6801_cpu_device::set_out_sertx_func(*device, DEVCB_##_devcb);
+
+
+class m6801_cpu_device : public m6800_cpu_device
+{
+public:
+ m6801_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+ // static configuration helpers
+ template<class _Object> static devcb_base &set_out_sc2_func(device_t &device, _Object object) { return downcast<m6801_cpu_device &>(device).m_out_sc2_func.set_callback(object); }
+ template<class _Object> static devcb_base &set_out_sertx_func(device_t &device, _Object object) { return downcast<m6801_cpu_device &>(device).m_out_sertx_func.set_callback(object); }
+
+ DECLARE_READ8_MEMBER( m6801_io_r );
+ DECLARE_WRITE8_MEMBER( m6801_io_w );
+
+ void m6801_clock_serial();
+
+protected:
+ m6801_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, const m6800_cpu_device::op_func *insn, const uint8_t *cycles, address_map_constructor internal = nullptr);
+
+ // device-level overrides
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ // device_execute_interface overrides
+ virtual uint64_t execute_clocks_to_cycles(uint64_t clocks) const override { return (clocks + 4 - 1) / 4; }
+ virtual uint64_t execute_cycles_to_clocks(uint64_t cycles) const override { return (cycles * 4); }
+ virtual void execute_set_input(int inputnum, int state) override;
+
+ // device_memory_interface overrides
+ virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const override;
+
+ // device_disasm_interface overrides
+ virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override;
+
+ address_space_config m_io_config;
+
+ devcb_write_line m_out_sc2_func;
+ devcb_write_line m_out_sertx_func;
+
+ address_space *m_io;
+
+ /* internal registers */
+ uint8_t m_port1_ddr;
+ uint8_t m_port2_ddr;
+ uint8_t m_port3_ddr;
+ uint8_t m_port4_ddr;
+ uint8_t m_port1_data;
+ uint8_t m_port2_data;
+ uint8_t m_port3_data;
+ uint8_t m_port4_data;
+ uint8_t m_p3csr; // Port 3 Control/Status Register
+ uint8_t m_tcsr; /* Timer Control and Status Register */
+ uint8_t m_pending_tcsr; /* pending IRQ flag for clear IRQflag process */
+ uint8_t m_irq2; /* IRQ2 flags */
+ uint8_t m_ram_ctrl;
+ PAIR m_counter; /* free running counter */
+ PAIR m_output_compare; /* output compare */
+ uint16_t m_input_capture; /* input capture */
+ int m_p3csr_is3_flag_read;
+ int m_port3_latched;
+
+ uint8_t m_trcsr, m_rmcr, m_rdr, m_tdr, m_rsr, m_tsr;
+ int m_rxbits, m_txbits, m_txstate, m_trcsr_read_tdre, m_trcsr_read_orfe, m_trcsr_read_rdrf, m_tx, m_ext_serclock;
+ bool m_use_ext_serclock;
+ int m_port2_written;
+
+ int m_latch09;
+
+ PAIR m_timer_over;
+ emu_timer *m_sci_timer;
+
+ /* point of next timer event */
+ uint32_t m_timer_next;
+
+ int m_sc1_state;
+
+ static const uint8_t cycles_6803[256];
+ static const uint8_t cycles_63701[256];
+ static const op_func m6803_insn[256];
+ static const op_func hd63701_insn[256];
+
+ virtual void m6800_check_irq2() override;
+ virtual void increment_counter(int amount) override;
+ virtual void EAT_CYCLES() override;
+ virtual void CLEANUP_COUNTERS() override;
+
+ void check_timer_event();
+ void set_rmcr(uint8_t data);
+ void write_port2();
+ int m6800_rx();
+ void serial_transmit();
+ void serial_receive();
+ TIMER_CALLBACK_MEMBER( sci_tick );
+ void set_os3(int state);
+};
+
+
+class m6803_cpu_device : public m6801_cpu_device
+{
+public:
+ m6803_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+protected:
+ virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override;
+};
+
+
+class hd6301_cpu_device : public m6801_cpu_device
+{
+public:
+ hd6301_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+protected:
+ hd6301_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+ virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override;
+};
+
+
+class hd63701_cpu_device : public m6801_cpu_device
+{
+public:
+ hd63701_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+protected:
+ virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, uint32_t options) override;
+
+ virtual void TAKE_TRAP() override;
+};
+
+
+// DP-40 package: HD6303RP, HD63A03RP, HD63B03RP,
+// FP-54 package: HD6303RF, HD63A03RF, HD63B03RF,
+// CG-40 package: HD6303RCG, HD63A03RCG, HD63B03RCG,
+// Not fully emulated yet
+class hd6303r_cpu_device : public hd6301_cpu_device
+{
+public:
+ hd6303r_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+};
+
+
+// DP-64S package: HD6303YP, HD63A03YP, HD63B03YP, HD63C03YP
+// FP-64 package: HD6303YF, HD63A03YF, HD63B03YF, HD63C03YF
+// FP-64A package: HD6303YH, HD63A03YH, HD63B03YH, HD63C03YH
+// CP-68 package: HD6303YCP, HD63A03YCP, HD63B03YCP, HD63C03YCP
+// Not fully emulated yet
+class hd6303y_cpu_device : public hd6301_cpu_device
+{
+public:
+ hd6303y_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+};
+
+
+DECLARE_DEVICE_TYPE(M6801, m6801_cpu_device)
+DECLARE_DEVICE_TYPE(M6803, m6803_cpu_device)
+DECLARE_DEVICE_TYPE(HD6301, hd6301_cpu_device)
+DECLARE_DEVICE_TYPE(HD63701, hd63701_cpu_device)
+DECLARE_DEVICE_TYPE(HD6303R, hd6303r_cpu_device)
+DECLARE_DEVICE_TYPE(HD6303Y, hd6303y_cpu_device)
+
+#endif // MAME_CPU_M6800_M6801_H
diff --git a/src/devices/machine/mpu401.h b/src/devices/machine/mpu401.h
index c73256b5273..3dc68b657ae 100644
--- a/src/devices/machine/mpu401.h
+++ b/src/devices/machine/mpu401.h
@@ -5,7 +5,7 @@
#pragma once
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#define MCFG_MPU401_ADD(tag, irqf) \
MCFG_DEVICE_ADD((tag), MPU401, 0) \
diff --git a/src/mame/audio/irem.cpp b/src/mame/audio/irem.cpp
index f0ca370a494..7a9a0987e91 100644
--- a/src/mame/audio/irem.cpp
+++ b/src/mame/audio/irem.cpp
@@ -9,7 +9,7 @@
#include "emu.h"
#include "audio/irem.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "sound/discrete.h"
#include "speaker.h"
diff --git a/src/mame/drivers/acesp.cpp b/src/mame/drivers/acesp.cpp
index 43ad6558617..c74324aea51 100644
--- a/src/mame/drivers/acesp.cpp
+++ b/src/mame/drivers/acesp.cpp
@@ -17,7 +17,7 @@
#include "emu.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "machine/6821pia.h"
class ace_sp_state : public driver_device
diff --git a/src/mame/drivers/apricotp.cpp b/src/mame/drivers/apricotp.cpp
index 07e4fed6dcb..ee378250daf 100644
--- a/src/mame/drivers/apricotp.cpp
+++ b/src/mame/drivers/apricotp.cpp
@@ -27,7 +27,7 @@
#include "emu.h"
#include "bus/centronics/ctronics.h"
#include "cpu/i86/i86.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "formats/apridisk.h"
#include "machine/am9517a.h"
#include "machine/apricotkb.h"
diff --git a/src/mame/drivers/banctec.cpp b/src/mame/drivers/banctec.cpp
index d98b0d8897c..7854fcef5eb 100644
--- a/src/mame/drivers/banctec.cpp
+++ b/src/mame/drivers/banctec.cpp
@@ -17,7 +17,7 @@
#include "emu.h"
#include "cpu/mcs51/mcs51.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "video/mc6845.h"
#include "screen.h"
diff --git a/src/mame/drivers/baraduke.cpp b/src/mame/drivers/baraduke.cpp
index 831d408aa11..b09899c44b6 100644
--- a/src/mame/drivers/baraduke.cpp
+++ b/src/mame/drivers/baraduke.cpp
@@ -111,7 +111,7 @@ DIP locations verified for:
#include "includes/baraduke.h"
#include "cpu/m6809/m6809.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "machine/watchdog.h"
#include "screen.h"
#include "speaker.h"
diff --git a/src/mame/drivers/bublbobl.cpp b/src/mame/drivers/bublbobl.cpp
index 11b139b0557..dfbc9c2b384 100644
--- a/src/mame/drivers/bublbobl.cpp
+++ b/src/mame/drivers/bublbobl.cpp
@@ -275,7 +275,7 @@ TODO:
#include "emu.h"
#include "includes/bublbobl.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "cpu/z80/z80.h"
#include "machine/watchdog.h"
#include "sound/2203intf.h"
diff --git a/src/mame/drivers/by6803.cpp b/src/mame/drivers/by6803.cpp
index 645a7bbe7eb..da7ea996334 100644
--- a/src/mame/drivers/by6803.cpp
+++ b/src/mame/drivers/by6803.cpp
@@ -22,7 +22,7 @@ ToDo:
#include "emu.h"
#include "machine/genpin.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
//#include "cpu/m6809/m6809.h"
#include "machine/6821pia.h"
//#include "audio/midway.h"
diff --git a/src/mame/drivers/by68701.cpp b/src/mame/drivers/by68701.cpp
index 9c74567ceab..7b0442593ae 100644
--- a/src/mame/drivers/by68701.cpp
+++ b/src/mame/drivers/by68701.cpp
@@ -2,7 +2,7 @@
// copyright-holders:Miodrag Milanovic
#include "emu.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
class by68701_state : public driver_device
{
diff --git a/src/mame/drivers/byvid.cpp b/src/mame/drivers/byvid.cpp
index 76828c7e2eb..6b90e380640 100644
--- a/src/mame/drivers/byvid.cpp
+++ b/src/mame/drivers/byvid.cpp
@@ -38,7 +38,7 @@ ToDo (granny):
#include "emu.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "cpu/m6809/m6809.h"
#include "machine/6821pia.h"
#include "machine/nvram.h"
diff --git a/src/mame/drivers/canon_s80.cpp b/src/mame/drivers/canon_s80.cpp
index 3038a5b630a..47c74c7aa6a 100644
--- a/src/mame/drivers/canon_s80.cpp
+++ b/src/mame/drivers/canon_s80.cpp
@@ -17,7 +17,7 @@
*/
#include "emu.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
//#include "video/hd44780.h"
class canons80_state : public driver_device
diff --git a/src/mame/drivers/castle.cpp b/src/mame/drivers/castle.cpp
index 0ec73496165..d82c8c2cf9d 100644
--- a/src/mame/drivers/castle.cpp
+++ b/src/mame/drivers/castle.cpp
@@ -45,7 +45,7 @@
#include "emu.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
class castle_state : public driver_device
{
diff --git a/src/mame/drivers/ddragon.cpp b/src/mame/drivers/ddragon.cpp
index e49ecba2734..39f15cc31b6 100644
--- a/src/mame/drivers/ddragon.cpp
+++ b/src/mame/drivers/ddragon.cpp
@@ -56,7 +56,7 @@ Dip locations verified with manual for ddragon & ddragon2
#include "includes/ddragon.h"
#include "cpu/m6809/hd6309.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "cpu/m6809/m6809.h"
#include "cpu/z80/z80.h"
#include "sound/okim6295.h"
diff --git a/src/mame/drivers/itech32.cpp b/src/mame/drivers/itech32.cpp
index eaffb85ebbb..1f112db5396 100644
--- a/src/mame/drivers/itech32.cpp
+++ b/src/mame/drivers/itech32.cpp
@@ -353,7 +353,7 @@ Notes:
#include "emu.h"
#include "includes/itech32.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "cpu/m68000/m68000.h"
#include "cpu/m6809/m6809.h"
#include "cpu/tms32031/tms32031.h"
diff --git a/src/mame/drivers/kncljoe.cpp b/src/mame/drivers/kncljoe.cpp
index 2f07c4a98fe..2fb515f9c1a 100644
--- a/src/mame/drivers/kncljoe.cpp
+++ b/src/mame/drivers/kncljoe.cpp
@@ -31,7 +31,7 @@ Updates:
#include "includes/kncljoe.h"
#include "cpu/z80/z80.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "sound/sn76496.h"
#include "speaker.h"
diff --git a/src/mame/drivers/ltd.cpp b/src/mame/drivers/ltd.cpp
index 9d270503ab1..dcac94ea14c 100644
--- a/src/mame/drivers/ltd.cpp
+++ b/src/mame/drivers/ltd.cpp
@@ -43,7 +43,7 @@ ToDo:
#include "emu.h"
#include "machine/genpin.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "sound/ay8910.h"
#include "speaker.h"
diff --git a/src/mame/drivers/mc10.cpp b/src/mame/drivers/mc10.cpp
index ad84fdaaf4d..70649853210 100644
--- a/src/mame/drivers/mc10.cpp
+++ b/src/mame/drivers/mc10.cpp
@@ -9,7 +9,7 @@
#include "emu.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "imagedev/cassette.h"
#include "imagedev/printer.h"
#include "machine/ram.h"
diff --git a/src/mame/drivers/namcos1.cpp b/src/mame/drivers/namcos1.cpp
index d137b515132..36d128f6def 100644
--- a/src/mame/drivers/namcos1.cpp
+++ b/src/mame/drivers/namcos1.cpp
@@ -339,7 +339,7 @@ C - uses sub board with support for player 3 and 4 controls
#include "includes/namcos1.h"
#include "cpu/m6809/m6809.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "machine/nvram.h"
#include "sound/volt_reg.h"
#include "sound/ym2151.h"
diff --git a/src/mame/drivers/namcos86.cpp b/src/mame/drivers/namcos86.cpp
index 8fc4bb8a0c5..0f2f82b1b7d 100644
--- a/src/mame/drivers/namcos86.cpp
+++ b/src/mame/drivers/namcos86.cpp
@@ -178,7 +178,7 @@ TODO:
#include "includes/namcos86.h"
#include "cpu/m6809/m6809.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "sound/ym2151.h"
#include "sound/n63701x.h"
#include "screen.h"
diff --git a/src/mame/drivers/pacland.cpp b/src/mame/drivers/pacland.cpp
index 487ca655278..acd5b3ed015 100644
--- a/src/mame/drivers/pacland.cpp
+++ b/src/mame/drivers/pacland.cpp
@@ -194,7 +194,7 @@ Notes:
#include "includes/pacland.h"
#include "cpu/m6809/m6809.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "machine/watchdog.h"
#include "speaker.h"
diff --git a/src/mame/drivers/rvoice.cpp b/src/mame/drivers/rvoice.cpp
index 62fdcfeab43..42f5b9a8df9 100644
--- a/src/mame/drivers/rvoice.cpp
+++ b/src/mame/drivers/rvoice.cpp
@@ -11,7 +11,7 @@
/* Core includes */
#include "emu.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "machine/mos6551.h"
//#include "dectalk.lh" // hack to avoid screenless system crash
#include "machine/terminal.h"
diff --git a/src/mame/drivers/skykid.cpp b/src/mame/drivers/skykid.cpp
index fd3af38d83e..65a183e5816 100644
--- a/src/mame/drivers/skykid.cpp
+++ b/src/mame/drivers/skykid.cpp
@@ -19,7 +19,7 @@ Notes:
#include "includes/skykid.h"
#include "cpu/m6809/m6809.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "machine/watchdog.h"
#include "sound/namco.h"
#include "screen.h"
diff --git a/src/mame/drivers/tceptor.cpp b/src/mame/drivers/tceptor.cpp
index 946378cdabe..b49c586f3be 100644
--- a/src/mame/drivers/tceptor.cpp
+++ b/src/mame/drivers/tceptor.cpp
@@ -13,7 +13,7 @@
#include "cpu/m6502/m65c02.h"
#include "cpu/m6809/m6809.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "cpu/m68000/m68000.h"
#include "machine/nvram.h"
#include "sound/dac.h"
diff --git a/src/mame/includes/adam.h b/src/mame/includes/adam.h
index 55bb08f829e..b21166751e4 100644
--- a/src/mame/includes/adam.h
+++ b/src/mame/includes/adam.h
@@ -10,7 +10,7 @@
#include "bus/coleco/ctrl.h"
#include "bus/coleco/exp.h"
#include "cpu/z80/z80.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "machine/coleco.h"
#include "machine/ram.h"
#include "sound/sn76496.h"
diff --git a/src/mame/includes/atarist.h b/src/mame/includes/atarist.h
index 5ed1f0d373f..0efd590c87f 100644
--- a/src/mame/includes/atarist.h
+++ b/src/mame/includes/atarist.h
@@ -7,7 +7,7 @@
#include "bus/rs232/rs232.h"
#include "cpu/m68000/m68000.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "machine/6850acia.h"
#include "machine/8530scc.h"
#include "bus/centronics/ctronics.h"
diff --git a/src/mame/includes/hx20.h b/src/mame/includes/hx20.h
index 5660bb4edf2..1aee0947250 100644
--- a/src/mame/includes/hx20.h
+++ b/src/mame/includes/hx20.h
@@ -5,7 +5,7 @@
#pragma once
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "imagedev/cassette.h"
#include "machine/mc146818.h"
#include "machine/ram.h"
diff --git a/src/mame/includes/psion.h b/src/mame/includes/psion.h
index 3c623b33b0c..f096f46ae1d 100644
--- a/src/mame/includes/psion.h
+++ b/src/mame/includes/psion.h
@@ -11,7 +11,7 @@
#ifndef _PSION_H_
#define _PSION_H_
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "machine/nvram.h"
#include "machine/psion_pack.h"
#include "video/hd44780.h"
diff --git a/src/mame/includes/px8.h b/src/mame/includes/px8.h
index dbda1fbc660..7daaa05ad69 100644
--- a/src/mame/includes/px8.h
+++ b/src/mame/includes/px8.h
@@ -7,7 +7,7 @@
#include "cpu/z80/z80.h"
-#include "cpu/m6800/m6800.h"
+#include "cpu/m6800/m6801.h"
#include "imagedev/cassette.h"
#include "machine/ram.h"
#include "machine/i8251.h"
diff --git a/src/mame/includes/slapstic.h b/src/mame/includes/slapstic.h
index 4e57f5e8d40..7fd6b907299 100644
--- a/src/mame/includes/slapstic.h
+++ b/src/mame/includes/slapstic.h
@@ -16,9 +16,6 @@
#pragma once
-#include "cpu/m6800/m6800.h"
-#include "cpu/m68000/m68000.h"
-
DECLARE_DEVICE_TYPE(SLAPSTIC, atari_slapstic_device)
diff --git a/src/mame/machine/slapstic.cpp b/src/mame/machine/slapstic.cpp
index 45ba5f48312..e312de55313 100644
--- a/src/mame/machine/slapstic.cpp
+++ b/src/mame/machine/slapstic.cpp
@@ -184,6 +184,9 @@
#include "emu.h"
#include "includes/slapstic.h"
+#include "cpu/m6800/m6800.h"
+#include "cpu/m68000/m68000.h"
+
/*************************************
*