diff options
author | hap <happppp@users.noreply.github.com> | 2021-05-14 13:47:46 +0200 |
---|---|---|
committer | hap <happppp@users.noreply.github.com> | 2021-05-14 13:48:01 +0200 |
commit | d175e44c1568802c28e43139c49694c8b440d6c6 (patch) | |
tree | 0782eeb24c684f014326c9a036a65cac6244d104 | |
parent | 381d97ed9d8385058b06ebd2f22dc482e95642a4 (diff) |
hd6301x: add overrides for port 3 data
-rw-r--r-- | src/devices/cpu/m6800/m6800.cpp | 10 | ||||
-rw-r--r-- | src/devices/cpu/m6800/m6801.cpp | 67 | ||||
-rw-r--r-- | src/devices/cpu/m6800/m6801.h | 21 |
3 files changed, 59 insertions, 39 deletions
diff --git a/src/devices/cpu/m6800/m6800.cpp b/src/devices/cpu/m6800/m6800.cpp index 8644c49c87b..aefd8b38cbb 100644 --- a/src/devices/cpu/m6800/m6800.cpp +++ b/src/devices/cpu/m6800/m6800.cpp @@ -21,8 +21,14 @@ System dependencies: uint16_t must be 16 bit unsigned int machine must be twos complement TODO: -- Verify invalid opcodes for the different CPU types. -- A lot more work and cleanups, especially for the 6801 derivatives. +- verify invalid opcodes for the different CPU types +- cleanups (difficult to do maintenance work right now) +- improve 6801 and derivatives: + * make internal I/O map really internal + * RAM control register (eg. nvram) + * IS3 interrupt for 6801 port 3 handshake (already implemented for 6301Y) + * finish 6301Y port 6 handshake, share implementation with p3csr? + * 6301Y sci_trcsr2_r/w *****************************************************************************/ diff --git a/src/devices/cpu/m6800/m6801.cpp b/src/devices/cpu/m6800/m6801.cpp index 26fc17db3fc..b816d9c8710 100644 --- a/src/devices/cpu/m6800/m6801.cpp +++ b/src/devices/cpu/m6800/m6801.cpp @@ -450,10 +450,10 @@ void hd6301x_cpu_device::m6800_check_irq2() void hd6301y_cpu_device::m6800_check_irq2() { - if ((m_p6_csr & 0xc0) == 0xc0) + if ((m_p6csr & 0xc0) == 0xc0) { TAKE_ISI; - standard_irq_callback(HD6301Y_IS_LINE); + standard_irq_callback(M6801_IS_LINE); } else hd6301x_cpu_device::m6800_check_irq2(); @@ -999,15 +999,15 @@ void hd6301y_cpu_device::execute_set_input(int irqline, int state) { switch (irqline) { - case HD6301Y_IS_LINE: + case M6801_IS_LINE: // interrupt at falling edge - if (!state && m_irq_state[HD6301Y_IS_LINE]) + if (!state && m_irq_state[M6801_IS_LINE]) { - m_p6_csr |= 0x80; // IS flag + m_p6csr |= 0x80; // IS flag m_pending_isf_clear = false; } - m_irq_state[HD6301Y_IS_LINE] = state; + m_irq_state[M6801_IS_LINE] = state; break; default: @@ -1043,6 +1043,7 @@ void m6801_cpu_device::device_start() m_sci_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(m6801_cpu_device::sci_tick),this)); + m_irq_state[M6801_IS_LINE] = 0; m_port_ddr[3] = 0; m_port_data[3] = 0; m_input_capture = 0; @@ -1062,7 +1063,7 @@ void m6801_cpu_device::device_start() save_item(NAME(m_counter.d)); save_item(NAME(m_output_compare.d)); save_item(NAME(m_input_capture)); - save_item(NAME(m_p3csr_is3_flag_read)); + save_item(NAME(m_pending_isf_clear)); save_item(NAME(m_port3_latched)); save_item(NAME(m_port2_written)); @@ -1111,10 +1112,7 @@ void hd6301y_cpu_device::device_start() { hd6301x_cpu_device::device_start(); - m_irq_state[HD6301Y_IS_LINE] = 0; - - save_item(NAME(m_p6_csr)); - save_item(NAME(m_pending_isf_clear)); + save_item(NAME(m_p6csr)); } void m6801_cpu_device::device_reset() @@ -1129,7 +1127,7 @@ void m6801_cpu_device::device_reset() m_port_ddr[2] = 0x00; m_port_data[0] = 0; m_p3csr = 0x00; - m_p3csr_is3_flag_read = 0; + m_pending_isf_clear = false; m_port2_written = false; m_port3_latched = 0; /* TODO: on reset port 2 should be read to determine the operating mode (bits 0-2) */ @@ -1173,14 +1171,15 @@ void hd6301x_cpu_device::device_reset() m_tcsr3 = 0x00; m_tout3 = false; m_t2cnt_written = false; + + m_p3csr = 0; // does not have this reg } void hd6301y_cpu_device::device_reset() { hd6301x_cpu_device::device_reset(); - m_p6_csr = 7; - m_pending_isf_clear = false; + m_p6csr = 7; } @@ -1334,11 +1333,11 @@ uint8_t m6801_cpu_device::p3_data_r() if (!machine().side_effects_disabled()) { - if (m_p3csr_is3_flag_read) + if (m_pending_isf_clear) { LOGPORT("Cleared IS3\n"); m_p3csr &= ~M6801_P3CSR_IS3_FLAG; - m_p3csr_is3_flag_read = 0; + m_pending_isf_clear = false; } if (!(m_p3csr & M6801_P3CSR_OSS)) @@ -1350,8 +1349,7 @@ uint8_t m6801_cpu_device::p3_data_r() if ((m_p3csr & M6801_P3CSR_LE) || (m_port_ddr[2] == 0xff)) data = m_port_data[2]; else - data = (m_in_port_func[2]() & (m_port_ddr[2] ^ 0xff)) - | (m_port_data[2] & m_port_ddr[2]); + data = (m_in_port_func[2]() & (m_port_ddr[2] ^ 0xff)) | (m_port_data[2] & m_port_ddr[2]); if (!machine().side_effects_disabled()) { @@ -1369,11 +1367,11 @@ void m6801_cpu_device::p3_data_w(uint8_t data) { LOGPORT("Port 3 Data Register: %02x\n", data); - if (m_p3csr_is3_flag_read) + if (m_pending_isf_clear) { LOGPORT("Cleared IS3\n"); m_p3csr &= ~M6801_P3CSR_IS3_FLAG; - m_p3csr_is3_flag_read = 0; + m_pending_isf_clear = false; } if (m_p3csr & M6801_P3CSR_OSS) @@ -1390,11 +1388,29 @@ void m6801_cpu_device::p3_data_w(uint8_t data) } } +uint8_t hd6301x_cpu_device::p3_data_r() +{ + // no handshaking protocol + if (m_port_ddr[2] == 0xff) + return m_port_data[2]; + else + return (m_in_port_func[2]() & (m_port_ddr[2] ^ 0xff)) | (m_port_data[2] & m_port_ddr[2]); +} + +void hd6301x_cpu_device::p3_data_w(uint8_t data) +{ + // no handshaking protocol + LOGPORT("Port 3 Data Register: %02x\n", data); + + m_port_data[2] = data; + m_out_port_func[2](0, (m_port_data[2] & m_port_ddr[2]) | (m_port_ddr[2] ^ 0xff), m_port_ddr[2]); +} + uint8_t m6801_cpu_device::p3_csr_r() { if ((m_p3csr & M6801_P3CSR_IS3_FLAG) && !machine().side_effects_disabled()) { - m_p3csr_is3_flag_read = 1; + m_pending_isf_clear = true; } return m_p3csr; @@ -1447,6 +1463,7 @@ void hd6301y_cpu_device::p5_ddr_w(uint8_t data) uint8_t hd6301x_cpu_device::p5_data_r() { + // read-only return m_in_portx_func[0](); } @@ -1455,7 +1472,7 @@ uint8_t hd6301y_cpu_device::p5_data_r() if (m_portx_ddr[0] == 0xff) return m_portx_data[0]; else - return ((m_in_portx_func[0]() | ((m_irq_state[HD6301Y_IS_LINE]) ? 0x10 : 0)) & (m_portx_ddr[0] ^ 0xff)) | (m_portx_data[0] & m_portx_ddr[0]); + return ((m_in_portx_func[0]() | ((m_irq_state[M6801_IS_LINE]) ? 0x10 : 0)) & (m_portx_ddr[0] ^ 0xff)) | (m_portx_data[0] & m_portx_ddr[0]); } void hd6301y_cpu_device::p5_data_w(uint8_t data) @@ -1513,7 +1530,7 @@ void hd6301y_cpu_device::clear_pending_isf() // IS flag is cleared when reading/writing P6 after reading P6 CSR if (m_pending_isf_clear) { - m_p6_csr &= 0x7f; + m_p6csr &= 0x7f; m_pending_isf_clear = false; } } @@ -1523,14 +1540,14 @@ uint8_t hd6301y_cpu_device::p6_csr_r() if (!machine().side_effects_disabled()) m_pending_isf_clear = true; - return m_p6_csr | 7; + return m_p6csr | 7; } void hd6301y_cpu_device::p6_csr_w(uint8_t data) { LOGPORT("Port 6 Control/Status Register: %02x\n", data); - m_p6_csr = (m_p6_csr & 0x80) | (data & 0x7f); + m_p6csr = (m_p6csr & 0x80) | (data & 0x7f); if (!(m_cc & 0x10) && data & 0x40) m6800_check_irq2(); } diff --git a/src/devices/cpu/m6800/m6801.h b/src/devices/cpu/m6800/m6801.h index df1d7dbcfc5..de74fed4ff7 100644 --- a/src/devices/cpu/m6800/m6801.h +++ b/src/devices/cpu/m6800/m6801.h @@ -13,7 +13,8 @@ enum { M6801_IRQ_LINE = M6800_IRQ_LINE, M6801_TIN_LINE, // P20/Tin Input Capture line (edge sense). Active edge is selectable by internal reg. - M6801_SC1_LINE + M6801_SC1_LINE, + M6801_IS_LINE // IS3(6801) or ISF(6301Y) }; enum @@ -28,11 +29,6 @@ enum enum { - HD6301Y_IS_LINE = M6801_SC1_LINE+1 -}; - -enum -{ M6801_MODE_0 = 0, M6801_MODE_1, M6801_MODE_2, @@ -76,7 +72,7 @@ protected: // device_execute_interface overrides virtual uint64_t execute_clocks_to_cycles(uint64_t clocks) const noexcept override { return (clocks + 4 - 1) / 4; } virtual uint64_t execute_cycles_to_clocks(uint64_t cycles) const noexcept override { return (cycles * 4); } - virtual uint32_t execute_input_lines() const noexcept override { return 4; } + virtual uint32_t execute_input_lines() const noexcept override { return 5; } virtual void execute_set_input(int inputnum, int state) override; // device_disasm_interface overrides @@ -89,8 +85,8 @@ protected: uint8_t p2_data_r(); void p2_data_w(uint8_t data); void p3_ddr_w(uint8_t data); - uint8_t p3_data_r(); - void p3_data_w(uint8_t data); + virtual uint8_t p3_data_r(); + virtual void p3_data_w(uint8_t data); uint8_t p3_csr_r(); void p3_csr_w(uint8_t data); void p4_ddr_w(uint8_t data); @@ -143,7 +139,7 @@ protected: PAIR m_counter; /* free running counter */ PAIR m_output_compare; /* output compare */ uint16_t m_input_capture; /* input capture */ - int m_p3csr_is3_flag_read; + bool m_pending_isf_clear; int m_port3_latched; uint8_t m_trcsr, m_rmcr, m_rdr, m_tdr, m_rsr, m_tsr; @@ -275,6 +271,8 @@ protected: virtual void write_port2() override; void p2_ddr_2bit_w(uint8_t data); + virtual uint8_t p3_data_r() override; + virtual void p3_data_w(uint8_t data) override; virtual uint8_t p5_data_r(); void p6_ddr_w(uint8_t data); virtual uint8_t p6_data_r(); @@ -368,7 +366,6 @@ protected: virtual void device_reset() override; // device_execute_interface overrides - virtual uint32_t execute_input_lines() const noexcept override { return 5; } virtual void execute_set_input(int inputnum, int state) override; void p5_ddr_w(uint8_t data); @@ -382,7 +379,7 @@ protected: virtual void m6800_check_irq2() override; void clear_pending_isf(); - uint8_t m_p6_csr; + uint8_t m_p6csr; bool m_pending_isf_clear; }; |