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author Nigel Barnes <Pernod70@users.noreply.github.com>2017-04-17 13:34:29 +0100
committer Nigel Barnes <Pernod70@users.noreply.github.com>2017-04-17 18:49:42 +0100
commitcfec997fbb1ea8389e5ee257a3ad4cb505ccd84a (patch)
tree70a4817710c48a02dc8babe40a7d114275f4edef
parent0b1220b6b012103b3a6f0134ba56d128ad272029 (diff)
dgnbeta: Added software list with OS-9 system and apps
- Replaced 5.25" floppies with 3.5", and added sounds - Enabled floppy motor - Removed tag lookups
-rw-r--r--hash/dgnbeta_flop.xml50
-rw-r--r--src/mame/drivers/dgn_beta.cpp103
-rw-r--r--src/mame/includes/dgn_beta.h31
-rw-r--r--src/mame/machine/dgn_beta.cpp89
-rw-r--r--src/mame/video/dgn_beta.cpp34
5 files changed, 183 insertions, 124 deletions
diff --git a/hash/dgnbeta_flop.xml b/hash/dgnbeta_flop.xml
new file mode 100644
index 00000000000..7580d47ce3f
--- /dev/null
+++ b/hash/dgnbeta_flop.xml
@@ -0,0 +1,50 @@
+<?xml version="1.0"?>
+<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
+
+<softwarelist name="dgnbeta_flop" description="Dragon Beta diskettes">
+
+ <software name="ccompiler">
+ <description>OS-9 C Compiler</description>
+ <year>198?</year>
+ <publisher>Dragon Data</publisher>
+ <part name="flop1" interface="floppy_3_5">
+ <dataarea name="flop" size="849936">
+ <rom name="Dragon Beta(128) OS-9 C Compiler (198x)(Dragon Data Ltd)[!].dmk" size="849936" crc="98332ce9" sha1="95faa725cb824f0429ca7280e4af53e23f0f106f" offset="0" />
+ </dataarea>
+ </part>
+ </software>
+
+ <software name="graphics">
+ <description>OS-9 Graphics Demo and Source</description>
+ <year>198?</year>
+ <publisher>Dragon Data</publisher>
+ <part name="flop1" interface="floppy_3_5">
+ <dataarea name="flop" size="849936">
+ <rom name="Dragon Beta(128) OS-9 Graphics Demo and Source (198x)(Dragon Data Ltd)[!].dmk" size="849936" crc="28912161" sha1="529f90ed0905d149d76edf56a6ce464a50d38d04" offset="0" />
+ </dataarea>
+ </part>
+ </software>
+
+ <software name="os9l2v11">
+ <description>OS-9 Level 2 v1.1 System Disk</description>
+ <year>198?</year>
+ <publisher>Dragon Data</publisher>
+ <part name="flop1" interface="floppy_3_5">
+ <dataarea name="flop" size="849936">
+ <rom name="Dragon Beta(128) OS-9 Level 2 v1.1 System Disk (198x)(Dragon Data Ltd)[!].dmk" size="849936" crc="5ad1d33c" sha1="08e4868046d648b0a78d3c01955e098a565db682" offset="0" />
+ </dataarea>
+ </part>
+ </software>
+
+ <software name="pascal">
+ <description>OS-9 Pascal Compiler</description>
+ <year>198?</year>
+ <publisher>Dragon Data</publisher>
+ <part name="flop1" interface="floppy_3_5">
+ <dataarea name="flop" size="849936">
+ <rom name="Dragon Beta(128) OS-9 Pascal Compiler (198x)(Dragon Data Ltd)[!].dmk" size="849936" crc="90e51089" sha1="de2088bf18ea6d0e56c36d700ac4d6ebdd995d7b" offset="0" />
+ </dataarea>
+ </part>
+ </software>
+
+</softwarelist>
diff --git a/src/mame/drivers/dgn_beta.cpp b/src/mame/drivers/dgn_beta.cpp
index a1a82b3af9c..56cd9f6ffce 100644
--- a/src/mame/drivers/dgn_beta.cpp
+++ b/src/mame/drivers/dgn_beta.cpp
@@ -56,10 +56,10 @@ documentation still exists.
/*
- Colour codes are as below acording to os-9 headers, however the presise values
- may not be quite correct, also this will need changing as the pallate seems to
- be controled by a 4x4bit register file in the video hardware
- The text video ram seems to be aranged of words of character, attribute
+ Colour codes are as below according to os-9 headers, however the precise values
+ may not be quite correct, also this will need changing as the palette seems to
+ be controlled by a 4x4bit register file in the video hardware
+ The text video ram seems to be arranged of words of character, attribute
The colour codes are stored in the attribute byte along with :
Underline bit $40
Flash bit $80
@@ -94,8 +94,8 @@ static const unsigned char dgnbeta_palette[] =
/*
2005-05-10
- I *THINK* I know how the memory paging works, the 64K memory map is devided
- into 16x 4K pages, what is mapped into each page is controled by the IO at
+ I *THINK* I know how the memory paging works, the 64K memory map is divided
+ into 16x 4K pages, what is mapped into each page is controlled by the IO at
FE00-FE0F like so :-
Location Memory page Initialised to
@@ -117,7 +117,7 @@ static const unsigned char dgnbeta_palette[] =
$FE0F $F000-$FFFF $FF
The value stored at each location maps it's page to a 4K page within a 1M address
- space. Acording to the Beta product descriptions released by Dragon Data, the
+ space. According to the Beta product descriptions released by Dragon Data, the
machine could have up to 768K of RAM, if this where true then pages $00-$BF could
potentially be RAM, and pages $C0-$FF would be ROM. The initialisation code maps in
the memory as described above.
@@ -127,16 +127,16 @@ static const unsigned char dgnbeta_palette[] =
enable the paging hardware.
It appears to be more complicated than this, whilst the above is true, there appear to
- be 16 sets of banking registers, the active set is controled by the bottom 4 bits of
+ be 16 sets of banking registers, the active set is controlled by the bottom 4 bits of
FCC0, bit 6 has something to do with enabling and disabling banking.
2005-11-28
- The value $C0 is guaranteed not to have any memory in it acording to the os9 headers,
+ The value $C0 is guaranteed not to have any memory in it according to the os9 headers,
quite how the MMU deals with this is still unknown to me.
Bit 7 of $FCC0, sets maps in the system task which has fixed values for some pages,
- the presise nature of this is yet to be descovered.
+ the precise nature of this is yet to be discovered.
*/
@@ -164,12 +164,12 @@ static ADDRESS_MAP_START( dgnbeta_map, AS_PROGRAM, 8, dgn_beta_state )
AM_RANGE(0xfc80, 0xfc80) AM_DEVWRITE("crtc", mc6845_device, address_w)
AM_RANGE(0xfc81, 0xfc81) AM_DEVREADWRITE("crtc", mc6845_device, register_r, register_w)
AM_RANGE(0xfc82, 0xfC9F) AM_NOP
- AM_RANGE(0xFCA0, 0xFCA3) AM_READNOP AM_WRITE(dgnbeta_colour_ram_w) /* 4x4bit colour ram for graphics modes */
+ AM_RANGE(0xFCA0, 0xFCA3) AM_READNOP AM_WRITE(dgnbeta_colour_ram_w) /* 4x4bit colour ram for graphics modes */
AM_RANGE(0xFCC0, 0xFCC3) AM_DEVREADWRITE(PIA_2_TAG, pia6821_device, read, write)
AM_RANGE(0xfcC4, 0xfcdf) AM_NOP
- AM_RANGE(0xfce0, 0xfce3) AM_READWRITE(dgnbeta_wd2797_r ,dgnbeta_wd2797_w) /* Onboard disk interface */
+ AM_RANGE(0xfce0, 0xfce3) AM_READWRITE(dgnbeta_wd2797_r, dgnbeta_wd2797_w) /* Onboard disk interface */
AM_RANGE(0xfce4, 0xfdff) AM_NOP
- AM_RANGE(0xFE00, 0xFE0F) AM_READWRITE(dgn_beta_page_r ,dgn_beta_page_w)
+ AM_RANGE(0xFE00, 0xFE0F) AM_READWRITE(dgn_beta_page_r, dgn_beta_page_w)
AM_RANGE(0xfe10, 0xfEff) AM_NOP
AM_RANGE(0xFF00, 0xFFFF) AM_RAMBANK("bank17")
@@ -285,9 +285,7 @@ INPUT_PORTS_END
PALETTE_INIT_MEMBER(dgn_beta_state, dgn)
{
- int i;
-
- for ( i = 0; i < sizeof(dgnbeta_palette) / 3; i++ ) {
+ for ( int i = 0; i < sizeof(dgnbeta_palette) / 3; i++ ) {
palette.set_pen_color(i, dgnbeta_palette[i*3], dgnbeta_palette[i*3+1], dgnbeta_palette[i*3+2]);
}
}
@@ -297,7 +295,7 @@ static const gfx_layout dgnbeta_charlayout =
{
8, 10, /* 8 x 10 characters */
256, /* 256 characters */
- 1, /* 1 bits per pixel */
+ 1, /* 1 bits per pixel */
{ 0 }, /* no bitplanes */
/* x offsets */
{ 0, 1, 2, 3, 4, 5, 6, 7 },
@@ -310,13 +308,13 @@ static GFXDECODE_START( dgnbeta )
GFXDECODE_ENTRY( "gfx1", 0x0000, dgnbeta_charlayout, 0, 8 )
GFXDECODE_END
-FLOPPY_FORMATS_MEMBER( dgn_beta_state::floppy_formats )
+FLOPPY_FORMATS_MEMBER(dgn_beta_state::floppy_formats )
FLOPPY_VDK_FORMAT,
FLOPPY_DMK_FORMAT
FLOPPY_FORMATS_END
-static SLOT_INTERFACE_START( dgn_beta_floppies )
- SLOT_INTERFACE("qd", FLOPPY_525_QD)
+static SLOT_INTERFACE_START( dgnbeta_floppies )
+ SLOT_INTERFACE("dd", FLOPPY_35_DD)
SLOT_INTERFACE_END
static MACHINE_CONFIG_START( dgnbeta, dgn_beta_state )
@@ -325,7 +323,7 @@ static MACHINE_CONFIG_START( dgnbeta, dgn_beta_state )
MCFG_CPU_PROGRAM_MAP(dgnbeta_map)
MCFG_CPU_DISASSEMBLE_OVERRIDE(dgn_beta_state, dgnbeta_dasm_override)
- /* both cpus in the beta share the same address/data busses */
+ /* both cpus in the beta share the same address/data buses */
MCFG_CPU_ADD(DMACPU_TAG, M6809E, DGNBETA_CPU_SPEED_HZ) /* 2 MHz */
MCFG_CPU_PROGRAM_MAP(dgnbeta_map)
@@ -344,42 +342,46 @@ static MACHINE_CONFIG_START( dgnbeta, dgn_beta_state )
/* PIA 0 at $FC20-$FC23 I46 */
MCFG_DEVICE_ADD(PIA_0_TAG, PIA6821, 0)
- MCFG_PIA_READPA_HANDLER(READ8(dgn_beta_state,d_pia0_pa_r))
- MCFG_PIA_READPB_HANDLER(READ8(dgn_beta_state,d_pia0_pb_r))
- MCFG_PIA_WRITEPA_HANDLER(WRITE8(dgn_beta_state,d_pia0_pa_w))
- MCFG_PIA_WRITEPB_HANDLER(WRITE8(dgn_beta_state,d_pia0_pb_w))
- MCFG_PIA_CB2_HANDLER(WRITELINE(dgn_beta_state,d_pia0_cb2_w))
- MCFG_PIA_IRQA_HANDLER(WRITELINE(dgn_beta_state,d_pia0_irq_a))
- MCFG_PIA_IRQB_HANDLER(WRITELINE(dgn_beta_state,d_pia0_irq_b))
+ MCFG_PIA_READPA_HANDLER(READ8(dgn_beta_state, d_pia0_pa_r))
+ MCFG_PIA_READPB_HANDLER(READ8(dgn_beta_state, d_pia0_pb_r))
+ MCFG_PIA_WRITEPA_HANDLER(WRITE8(dgn_beta_state, d_pia0_pa_w))
+ MCFG_PIA_WRITEPB_HANDLER(WRITE8(dgn_beta_state, d_pia0_pb_w))
+ MCFG_PIA_CB2_HANDLER(WRITELINE(dgn_beta_state, d_pia0_cb2_w))
+ MCFG_PIA_IRQA_HANDLER(WRITELINE(dgn_beta_state, d_pia0_irq_a))
+ MCFG_PIA_IRQB_HANDLER(WRITELINE(dgn_beta_state, d_pia0_irq_b))
/* PIA 1 at $FC24-$FC27 I63 */
MCFG_DEVICE_ADD(PIA_1_TAG, PIA6821, 0)
- MCFG_PIA_READPA_HANDLER(READ8(dgn_beta_state,d_pia1_pa_r))
- MCFG_PIA_READPB_HANDLER(READ8(dgn_beta_state,d_pia1_pb_r))
- MCFG_PIA_WRITEPA_HANDLER(WRITE8(dgn_beta_state,d_pia1_pa_w))
- MCFG_PIA_WRITEPB_HANDLER(WRITE8(dgn_beta_state,d_pia1_pb_w))
- MCFG_PIA_IRQA_HANDLER(WRITELINE(dgn_beta_state,d_pia1_irq_a))
- MCFG_PIA_IRQB_HANDLER(WRITELINE(dgn_beta_state,d_pia1_irq_b))
+ MCFG_PIA_READPA_HANDLER(READ8(dgn_beta_state, d_pia1_pa_r))
+ MCFG_PIA_READPB_HANDLER(READ8(dgn_beta_state, d_pia1_pb_r))
+ MCFG_PIA_WRITEPA_HANDLER(WRITE8(dgn_beta_state, d_pia1_pa_w))
+ MCFG_PIA_WRITEPB_HANDLER(WRITE8(dgn_beta_state, d_pia1_pb_w))
+ MCFG_PIA_IRQA_HANDLER(WRITELINE(dgn_beta_state, d_pia1_irq_a))
+ MCFG_PIA_IRQB_HANDLER(WRITELINE(dgn_beta_state, d_pia1_irq_b))
/* PIA 2 at FCC0-FCC3 I28 */
/* This seems to control the RAM paging system, and have the DRQ */
/* from the WD2797 */
MCFG_DEVICE_ADD(PIA_2_TAG, PIA6821, 0)
- MCFG_PIA_READPA_HANDLER(READ8(dgn_beta_state,d_pia2_pa_r))
- MCFG_PIA_READPB_HANDLER(READ8(dgn_beta_state,d_pia2_pb_r))
- MCFG_PIA_WRITEPA_HANDLER(WRITE8(dgn_beta_state,d_pia2_pa_w))
- MCFG_PIA_WRITEPB_HANDLER(WRITE8(dgn_beta_state,d_pia2_pb_w))
- MCFG_PIA_IRQA_HANDLER(WRITELINE(dgn_beta_state,d_pia2_irq_a))
- MCFG_PIA_IRQB_HANDLER(WRITELINE(dgn_beta_state,d_pia2_irq_b))
+ MCFG_PIA_READPA_HANDLER(READ8(dgn_beta_state, d_pia2_pa_r))
+ MCFG_PIA_READPB_HANDLER(READ8(dgn_beta_state, d_pia2_pb_r))
+ MCFG_PIA_WRITEPA_HANDLER(WRITE8(dgn_beta_state, d_pia2_pa_w))
+ MCFG_PIA_WRITEPB_HANDLER(WRITE8(dgn_beta_state, d_pia2_pb_w))
+ MCFG_PIA_IRQA_HANDLER(WRITELINE(dgn_beta_state, d_pia2_irq_a))
+ MCFG_PIA_IRQB_HANDLER(WRITELINE(dgn_beta_state, d_pia2_irq_b))
MCFG_WD2797_ADD(FDC_TAG, XTAL_1MHz)
MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(dgn_beta_state, dgnbeta_fdc_intrq_w))
MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(dgn_beta_state, dgnbeta_fdc_drq_w))
- MCFG_FLOPPY_DRIVE_ADD(FDC_TAG ":0", dgn_beta_floppies, "qd", dgn_beta_state::floppy_formats)
- MCFG_FLOPPY_DRIVE_ADD(FDC_TAG ":1", dgn_beta_floppies, "qd", dgn_beta_state::floppy_formats)
- MCFG_FLOPPY_DRIVE_ADD(FDC_TAG ":2", dgn_beta_floppies, "qd", dgn_beta_state::floppy_formats)
- MCFG_FLOPPY_DRIVE_ADD(FDC_TAG ":3", dgn_beta_floppies, "qd", dgn_beta_state::floppy_formats)
+ MCFG_FLOPPY_DRIVE_ADD(FDC_TAG ":0", dgnbeta_floppies, "dd", dgn_beta_state::floppy_formats)
+ MCFG_FLOPPY_DRIVE_SOUND(true)
+ MCFG_FLOPPY_DRIVE_ADD(FDC_TAG ":1", dgnbeta_floppies, "dd", dgn_beta_state::floppy_formats)
+ MCFG_FLOPPY_DRIVE_SOUND(true)
+ MCFG_FLOPPY_DRIVE_ADD(FDC_TAG ":2", dgnbeta_floppies, nullptr, dgn_beta_state::floppy_formats)
+ MCFG_FLOPPY_DRIVE_SOUND(true)
+ MCFG_FLOPPY_DRIVE_ADD(FDC_TAG ":3", dgnbeta_floppies, nullptr, dgn_beta_state::floppy_formats)
+ MCFG_FLOPPY_DRIVE_SOUND(true)
MCFG_MC6845_ADD("crtc", HD6845, "screen", XTAL_12_288MHz / 16) //XTAL is guessed
MCFG_MC6845_SHOW_BORDER_AREA(false)
@@ -394,15 +396,18 @@ static MACHINE_CONFIG_START( dgnbeta, dgn_beta_state )
/* Ram size can now be configured, since the machine was known as either the Dragon Beta or */
/* the Dragon 128, I have added a config for 128K, however, the only working machine known */
/* to exist was fitted with 256K, so I have made this the default. Also available */
- /* documentation seems to sugest a maximum of 768K, so I have included configs increasing */
+ /* documentation seems to suggest a maximum of 768K, so I have included configs increasing */
/* in blocks of 128K up to this maximum. */
+
+ /* software lists */
+ MCFG_SOFTWARE_LIST_ADD("flop_list", "dgnbeta_flop")
MACHINE_CONFIG_END
ROM_START(dgnbeta)
ROM_REGION(0x4000,MAINCPU_TAG,0)
- ROM_SYSTEM_BIOS( 0, "bootrom", "Dragon beta OS9 boot rom (1984)" )
+ ROM_SYSTEM_BIOS( 0, "bootrom", "Dragon Beta OS-9 Boot ROM (15.6.84)" )
ROMX_LOAD("beta_bt.rom" ,0x0000 ,0x4000 ,CRC(4c54c1de) SHA1(141d9fcd2d187c305dff83fce2902a30072aed76), ROM_BIOS(1))
- ROM_SYSTEM_BIOS( 1, "testrom", "Dragon beta test rom (1984?)" )
+ ROM_SYSTEM_BIOS( 1, "testrom", "Dragon Beta Test ROM (1984?)" )
ROMX_LOAD("beta_tst.rom" ,0x2000 ,0x2000 ,CRC(01d79d00) SHA1(343e08cf7656b5e8970514868df37ea0af1e2362), ROM_BIOS(2))
ROM_SYSTEM_BIOS( 2, "cfiles", "cfiles rom" )
ROMX_LOAD("beta_cfi.rom" ,0x2000 ,0x2000 ,CRC(d312e4c0) SHA1(5c00daac488eaf8d36d66de6ec6c746ab7b78ecf), ROM_BIOS(3))
@@ -413,5 +418,5 @@ ROM_START(dgnbeta)
ROM_LOAD("betachar.rom" ,0x0000 ,0x2000 ,CRC(ca79d66c) SHA1(8e2090d471dd97a53785a7f44a49d3c8c85b41f2))
ROM_END
-/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
-COMP( 1984, dgnbeta, 0, 0, dgnbeta, dgnbeta, driver_device, 0, "Dragon Data Ltd", "Dragon Beta Prototype", MACHINE_NO_SOUND )
+/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
+COMP( 1984, dgnbeta, 0, 0, dgnbeta, dgnbeta, driver_device, 0, "Dragon Data Ltd", "Dragon 128 (Beta)", MACHINE_NO_SOUND )
diff --git a/src/mame/includes/dgn_beta.h b/src/mame/includes/dgn_beta.h
index 2c93ad9f771..497ed180b36 100644
--- a/src/mame/includes/dgn_beta.h
+++ b/src/mame/includes/dgn_beta.h
@@ -53,7 +53,7 @@
/* From Dragon Beta OS9 keyboard driver */
#define KAny 0x04 /* Any key pressed mask PB2 */
-#define KOutClk 0x08 /* Ouput shift register clock */
+#define KOutClk 0x08 /* Output shift register clock */
#define KInClk 0x10 /* Input shift register clock */
#define KOutDat KInClk /* Also used for data into output shifter */
#define KInDat 0x20 /* Keyboard data in from keyboard (serial stream) */
@@ -74,7 +74,7 @@ enum BETA_VID_MODES
struct PageReg
{
int value; /* Value of the page register */
- uint8_t *memory; /* The memory it actually points to */
+ uint8_t *memory; /* The memory it actually points to */
};
@@ -83,10 +83,14 @@ class dgn_beta_state : public driver_device
public:
dgn_beta_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
- m_mc6845(*this, "crtc"),
+ m_mc6845(*this, "crtc"),
m_videoram(*this, "videoram"),
m_maincpu(*this, "maincpu"),
+ m_dmacpu(*this, DMACPU_TAG),
m_ram(*this, RAM_TAG),
+ m_pia_0(*this, PIA_0_TAG),
+ m_pia_1(*this, PIA_1_TAG),
+ m_pia_2(*this, PIA_2_TAG),
m_fdc(*this, FDC_TAG),
m_floppy0(*this, FDC_TAG ":0"),
m_floppy1(*this, FDC_TAG ":1"),
@@ -98,6 +102,18 @@ public:
required_device<mc6845_device> m_mc6845;
required_shared_ptr<uint8_t> m_videoram;
+ required_device<cpu_device> m_maincpu;
+ required_device<cpu_device> m_dmacpu;
+ required_device<ram_device> m_ram;
+ required_device<pia6821_device> m_pia_0;
+ required_device<pia6821_device> m_pia_1;
+ required_device<pia6821_device> m_pia_2;
+ required_device<wd2797_t> m_fdc;
+ required_device<floppy_connector> m_floppy0;
+ required_device<floppy_connector> m_floppy1;
+ required_device<floppy_connector> m_floppy2;
+ required_device<floppy_connector> m_floppy3;
+ required_device<palette_device> m_palette;
uint8_t *m_system_rom;
int m_LogDatWrites;
@@ -201,7 +217,7 @@ public:
/* WD2797 FDC */
DECLARE_READ8_MEMBER(dgnbeta_wd2797_r);
DECLARE_WRITE8_MEMBER(dgnbeta_wd2797_w);
- required_device<cpu_device> m_maincpu;
+
void dgnbeta_vid_set_gctrl(int data);
void UpdateBanks(int first, int last);
void SetDefaultTask();
@@ -213,13 +229,6 @@ public:
void cpu1_recalc_firq(int state);
void ScanInKeyboard(void);
void dgn_beta_frame_interrupt (int data);
- required_device<ram_device> m_ram;
- required_device<wd2797_t> m_fdc;
- required_device<floppy_connector> m_floppy0;
- required_device<floppy_connector> m_floppy1;
- required_device<floppy_connector> m_floppy2;
- required_device<floppy_connector> m_floppy3;
- required_device<palette_device> m_palette;
offs_t dgnbeta_dasm_override(device_t &device, std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, int options);
diff --git a/src/mame/machine/dgn_beta.cpp b/src/mame/machine/dgn_beta.cpp
index 3c75c4c11f9..dab45919b06 100644
--- a/src/mame/machine/dgn_beta.cpp
+++ b/src/mame/machine/dgn_beta.cpp
@@ -35,7 +35,7 @@
2005-11-29
- Major track tracing excersise on scans of bare beta board, reveal where a
+ Major track tracing exercise on scans of bare beta board, reveal where a
whole bunch of the PIA lines go, especially the IRQs, most of them go back
to the IRQ line on the main CPU.
@@ -46,8 +46,8 @@
2005-12-08
Fixed density setting on WD2797, so density of read data is now
- correctlty set as required by OS-9. This was the reason startup
- script was not being executed as Beta disks have a single denisty
+ correctly set as required by OS-9. This was the reason startup
+ script was not being executed as Beta disks have a single density
boot track, however the rest of the disk is double density.
Booted completely to OS-9, including running startup script.
@@ -89,8 +89,8 @@
//static int DMA_NMI; /* DMA cpu has received an NMI */
-#define INVALID_KEYROW -1 /* no ketrow selected */
-#define NO_KEY_PRESSED 0x7F /* retrurned by hardware if no key pressed */
+#define INVALID_KEYROW -1 /* no keyrow selected */
+#define NO_KEY_PRESSED 0x7F /* returned by hardware if no key pressed */
// Info for bank switcher
struct bank_info_entry
@@ -135,15 +135,15 @@ static const struct bank_info_entry bank_info[] =
// For the purpose of this driver any block that is not ram, and is not a known ROM block,
// is mapped to the first page of the boot rom, I do not know what happens in the real
// hardware, however this does allow the boot rom to correctly size the RAM.
-// this should probably be considdered a hack !
+// this should probably be considered a hack !
//
void dgn_beta_state::UpdateBanks(int first, int last)
{
address_space &space_0 = m_maincpu->space(AS_PROGRAM);
- address_space &space_1 = machine().device(DMACPU_TAG)->memory().space(AS_PROGRAM);
+ address_space &space_1 = m_dmacpu->space(AS_PROGRAM);
int Page;
- uint8_t *readbank;
+ uint8_t *readbank;
int bank_start;
int bank_end;
int MapPage;
@@ -575,7 +575,7 @@ WRITE8_MEMBER(dgn_beta_state::d_pia1_pa_w)
HALT_DMA = CLEAR_LINE;
LOG_HALT(("DMA_CPU HALT=%d\n", HALT_DMA));
- machine().device(DMACPU_TAG)->execute().set_input_line(INPUT_LINE_HALT, HALT_DMA);
+ m_dmacpu->set_input_line(INPUT_LINE_HALT, HALT_DMA);
/* CPU un-halted let it run ! */
if (HALT_DMA == CLEAR_LINE)
@@ -597,6 +597,11 @@ WRITE8_MEMBER(dgn_beta_state::d_pia1_pa_w)
m_fdc->set_floppy(floppy);
+ if (m_floppy0->get_device()) m_floppy0->get_device()->mon_w(0);
+ if (m_floppy1->get_device()) m_floppy1->get_device()->mon_w(0);
+ if (m_floppy2->get_device()) m_floppy2->get_device()->mon_w(0);
+ if (m_floppy3->get_device()) m_floppy3->get_device()->mon_w(0);
+
// not connected: bit 5 = ENP
m_fdc->dden_w(BIT(data, 6));
LOG_DISK(("Set density %s\n", BIT(data, 6) ? "low" : "high"));
@@ -627,7 +632,7 @@ WRITE8_MEMBER(dgn_beta_state::d_pia1_pb_w)
/* CPU un-halted let it run ! */
if (HALT_CPU == CLEAR_LINE)
- machine().device(DMACPU_TAG)->execute().yield();
+ m_dmacpu->yield();
}
}
@@ -648,7 +653,7 @@ WRITE_LINE_MEMBER(dgn_beta_state::d_pia1_irq_b)
DMA CPU NMI PA7
Graphics control PB0..PB7 ???
- VSYNC intutrupt CB2
+ VSYNC interrupt CB2
*/
READ8_MEMBER(dgn_beta_state::d_pia2_pa_r)
{
@@ -672,13 +677,13 @@ WRITE8_MEMBER(dgn_beta_state::d_pia2_pa_w)
LOG_INTS(("cpu1 NMI : %d\n", NMI));
if(!NMI)
{
- machine().device(DMACPU_TAG)->execute().set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
+ m_dmacpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
logerror("device_yield()\n");
- machine().device(DMACPU_TAG)->execute().yield(); /* Let DMA CPU run */
+ m_dmacpu->yield(); /* Let DMA CPU run */
}
else
{
- machine().device(DMACPU_TAG)->execute().set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
+ m_dmacpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
}
m_DMA_NMI_LAST = NMI; /* Save it for next time */
@@ -697,7 +702,7 @@ WRITE8_MEMBER(dgn_beta_state::d_pia2_pa_w)
LOG_TASK(("OldTask=$%02X EnableMapRegs=%d OldEnableMap=%d\n", OldTask, m_EnableMapRegs, OldEnableMap));
- // Maping was enabled or disabled, select apropreate task reg
+ // Mapping was enabled or disabled, select appropriate task reg
// and map it in
if (m_EnableMapRegs != OldEnableMap)
{
@@ -741,18 +746,15 @@ WRITE_LINE_MEMBER(dgn_beta_state::d_pia2_irq_b)
cpu0_recalc_irq(state);
}
-/************************************ Recalculate CPU inturrupts ****************************/
+/************************************ Recalculate CPU interrupts ****************************/
/* CPU 0 */
void dgn_beta_state::cpu0_recalc_irq(int state)
{
- pia6821_device *pia_0 = machine().device<pia6821_device>( PIA_0_TAG );
- pia6821_device *pia_1 = machine().device<pia6821_device>( PIA_1_TAG );
- pia6821_device *pia_2 = machine().device<pia6821_device>( PIA_2_TAG );
- uint8_t pia0_irq_a = pia_0->irq_a_state();
- uint8_t pia1_irq_a = pia_1->irq_a_state();
- uint8_t pia1_irq_b = pia_1->irq_b_state();
- uint8_t pia2_irq_a = pia_2->irq_a_state();
- uint8_t pia2_irq_b = pia_2->irq_b_state();
+ uint8_t pia0_irq_a = m_pia_0->irq_a_state();
+ uint8_t pia1_irq_a = m_pia_1->irq_a_state();
+ uint8_t pia1_irq_b = m_pia_1->irq_b_state();
+ uint8_t pia2_irq_a = m_pia_2->irq_a_state();
+ uint8_t pia2_irq_b = m_pia_2->irq_b_state();
uint8_t IRQ;
if (pia0_irq_a || pia1_irq_a || pia1_irq_b || pia2_irq_a || pia2_irq_b)
@@ -766,8 +768,7 @@ void dgn_beta_state::cpu0_recalc_irq(int state)
void dgn_beta_state::cpu0_recalc_firq(int state)
{
- pia6821_device *pia_0 = machine().device<pia6821_device>( PIA_0_TAG );
- uint8_t pia0_irq_b = pia_0->irq_b_state();
+ uint8_t pia0_irq_b = m_pia_0->irq_b_state();
uint8_t FIRQ;
if (pia0_irq_b)
@@ -784,7 +785,7 @@ void dgn_beta_state::cpu0_recalc_firq(int state)
void dgn_beta_state::cpu1_recalc_firq(int state)
{
- machine().device(DMACPU_TAG)->execute().set_input_line(M6809_FIRQ_LINE, state);
+ m_dmacpu->set_input_line(M6809_FIRQ_LINE, state);
LOG_INTS(("cpu1 FIRQ : %d\n",state));
}
@@ -795,13 +796,13 @@ void dgn_beta_state::cpu1_recalc_firq(int state)
/* The INTRQ line goes through pia2 ca1, in exactly the same way as DRQ from DragonDos does */
WRITE_LINE_MEMBER( dgn_beta_state::dgnbeta_fdc_intrq_w )
{
- device_t *device = machine().device(PIA_2_TAG);
LOG_DISK(("dgnbeta_fdc_intrq_w(%d)\n", state));
+
if(m_wd2797_written)
- downcast<pia6821_device *>(device)->ca1_w(state);
+ m_pia_2->ca1_w(state);
}
-/* DRQ is routed through various logic to the FIRQ inturrupt line on *BOTH* CPUs */
+/* DRQ is routed through various logic to the FIRQ interrupt line on *BOTH* CPUs */
WRITE_LINE_MEMBER( dgn_beta_state::dgnbeta_fdc_drq_w )
{
LOG_DISK(("dgnbeta_fdc_drq_w(%d)\n", state));
@@ -853,16 +854,14 @@ void dgn_beta_state::ScanInKeyboard(void)
#endif
}
-/* VBlank inturrupt */
+/* VBlank interrupt */
void dgn_beta_state::dgn_beta_frame_interrupt (int data)
{
- pia6821_device *pia_2 = machine().device<pia6821_device>( PIA_2_TAG );
-
- /* Set PIA line, so it recognises inturrupt */
+ /* Set PIA line, so it recognises interrupt */
if (!data)
- pia_2->cb2_w(ASSERT_LINE);
+ m_pia_2->cb2_w(ASSERT_LINE);
else
- pia_2->cb2_w(CLEAR_LINE);
+ m_pia_2->cb2_w(CLEAR_LINE);
// LOG_VIDEO(("Vblank\n"));
ScanInKeyboard();
@@ -871,14 +870,14 @@ void dgn_beta_state::dgn_beta_frame_interrupt (int data)
#ifdef UNUSED_FUNCTION
void dgn_beta_state::dgn_beta_line_interrupt (int data)
{
-// /* Set PIA line, so it recognises inturrupt */
+// /* Set PIA line, so it recognises interrupt */
// if (data)
// {
-// pia_0_cb1_w(machine, 0,ASSERT_LINE);
+// m_pia_0->cb1_w(ASSERT_LINE);
// }
// else
// {
-// pia_0_cb1_w(machine, 0,CLEAR_LINE);
+// m_pia_0->cb1_w(CLEAR_LINE);
// }
}
#endif
@@ -887,16 +886,12 @@ void dgn_beta_state::dgn_beta_line_interrupt (int data)
/********************************* Machine/Driver Initialization ****************************************/
void dgn_beta_state::machine_reset()
{
- pia6821_device *pia_0 = machine().device<pia6821_device>( PIA_0_TAG );
- pia6821_device *pia_1 = machine().device<pia6821_device>( PIA_1_TAG );
- pia6821_device *pia_2 = machine().device<pia6821_device>( PIA_2_TAG );
-
logerror("dgn_beta_state::machine_reset()\n");
m_system_rom = memregion(MAINCPU_TAG)->base();
/* Make sure CPU 1 is started out halted ! */
- machine().device(DMACPU_TAG)->execute().set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
+ m_dmacpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
/* Reset to task 0, and map banks disabled, so standard memory map */
/* with ram at $0000-$BFFF, ROM at $C000-FBFF, IO at $FC00-$FEFF */
@@ -908,9 +903,9 @@ void dgn_beta_state::machine_reset()
SetDefaultTask();
/* Set pullups on all PIA port A, to match what hardware does */
- pia_0->set_port_a_z_mask(0xFF);
- pia_1->set_port_a_z_mask(0xFF);
- pia_2->set_port_a_z_mask(0xFF);
+ m_pia_0->set_port_a_z_mask(0xFF);
+ m_pia_1->set_port_a_z_mask(0xFF);
+ m_pia_2->set_port_a_z_mask(0xFF);
m_d_pia1_pa_last = 0x00;
m_d_pia1_pb_last = 0x00;
diff --git a/src/mame/video/dgn_beta.cpp b/src/mame/video/dgn_beta.cpp
index a5e7b770ab3..0909a8200af 100644
--- a/src/mame/video/dgn_beta.cpp
+++ b/src/mame/video/dgn_beta.cpp
@@ -4,8 +4,8 @@
video/dgn_beta.c
The Dragon Beta uses a 68B45 for it's display generation, this is used in the
-conventional wat with a character generator ROM in the two text modes, which are
-standard 40x25 and 80x25. In adition to the 6845 there is some TTL logic which
+conventional way with a character generator ROM in the two text modes, which are
+standard 40x25 and 80x25. In addition to the 6845 there is some TTL logic which
provides colour and attributes. In text modes the video ram is organised as pairs
of character and attribute, in alternate bytes.
@@ -18,7 +18,7 @@ The attributes decode as follows :-
u=underline
FFF = foreground colour
- BBB = bakcground colour
+ BBB = background colour
000 black
001 red
@@ -34,16 +34,16 @@ The attributes decode as follows :-
It is interesting to note that the 6845 uses 16 bit wide access to the ram, in contrast
to the 8 bit accesses from the CPUs, this allows each increment of the MA lines to move
2 bytes at a time, and therefore feed both the character rom and the attribute decode
-circuit simultaniously.
+circuit simultaneously.
The RAM addresses are made up of two parts, the MA0..13 from the 6845, plus two output
lines from the 6821 PIA, I28, the lines are BP6 and PB7, with PB7 being the most
-significant. This effectivly allows the 6845 access to the first 128K of memory, as there
+significant. This effectively allows the 6845 access to the first 128K of memory, as there
are 16 address lines, accessing a 16 bit wide memory.
The relationship between how the cpu sees the RAM, and the way the 6845 sees it is simply
CPU addr=2x6845 addr. So for the default video address of $1F000, the CPU sees this as
-being at $1F000 (after DAT trasnlation). The 6845 is programmed to start it's MA lines
+being at $1F000 (after DAT translation). The 6845 is programmed to start it's MA lines
counting at $3800, plus A14 and A15 being supplied by PB6 and PB7 from I28, gives an address
of $F800, which is the same as $1F000 / 2.
@@ -84,13 +84,13 @@ the access to the video memory is unclear to me at the moment.
#include "emu.h"
#include "includes/dgn_beta.h"
-/* GCtrl bitmasks, infered from bits of Beta schematic */
-#define GCtrlWI 0x01
-#define GCtrlSWChar 0x02 /* Character set select */
-#define GCtrlHiLo 0x04 /* Hi/Lo res graphics, Hi=1, Lo=0 */
-#define GCtrlChrGfx 0x08 /* Character=1 / Graphics=0 */
+/* GCtrl bitmasks, inferred from bits of Beta schematic */
+#define GCtrlWI 0x01
+#define GCtrlSWChar 0x02 /* Character set select */
+#define GCtrlHiLo 0x04 /* Hi/Lo res graphics, Hi=1, Lo=0 */
+#define GCtrlChrGfx 0x08 /* Character=1 / Graphics=0 */
#define GCtrlControl 0x10 /* Control bit, sets direct drive mode */
-#define GCtrlFS 0x20 /* labeled F/S, not yet sure of function Fast or Slow scan ? */
+#define GCtrlFS 0x20 /* labeled F/S, not yet sure of function Fast or Slow scan ? */
#define GCtrlAddrLines 0xC0 /* Top two address lines for text mode */
#define IsTextMode (m_GCtrl & GCtrlChrGfx) ? 1 : 0 // Is this text mode ?
@@ -113,7 +113,7 @@ MC6845_UPDATE_ROW( dgn_beta_state::crtc_update_row )
uint8_t chr = videoram[ offset ];
uint8_t attr = videoram[ offset +1 ];
- /* Extract non-colour attributes, in character set 1, undeline is used */
+ /* Extract non-colour attributes, in character set 1, underline is used */
/* We will extract the colours below, when we have decoded inverse */
/* to indicate a double height character */
int UnderLine=(attr & 0x40) >> 6; // Underline active
@@ -122,7 +122,7 @@ MC6845_UPDATE_ROW( dgn_beta_state::crtc_update_row )
// underline is active for character set 0, on character row 9
int ULActive=(UnderLine && (ra==9) && ~SWChar);
- /* Invert forground and background if flashing char and flash acive */
+ /* Invert foreground and background if flashing char and flash active */
int Invert=(FlashChar & m_FlashBit);
/* Underline inverts flash */
@@ -187,7 +187,7 @@ MC6845_UPDATE_ROW( dgn_beta_state::crtc_update_row )
int Colour;
int Dot;
- /* If contol is low then we are plotting 4 bit per pixel, 16 colour mode */
+ /* If control is low then we are plotting 4 bit per pixel, 16 colour mode */
/* This directly drives the colour output lines, from the pixel value */
/* If Control is high, then we lookup the colour from the LS670 4x4 bit */
/* palate register */
@@ -265,7 +265,7 @@ WRITE_LINE_MEMBER(dgn_beta_state::dgnbeta_vsync_changed)
/* 1 Character set select, drives A12 of character rom in text mode */
/* 2 High (1) or Low(0) resolution if in graphics mode. */
/* 3 Text (1) or Graphics(0) mode */
-/* 4 Control bit, Selects between colour palate and drirect drive */
+/* 4 Control bit, Selects between colour palette and direct drive */
/* 5 F/S bit, 1=80 bytes/line, 0=40bytes/line */
/* 6 Effective A14, to ram, in text mode */
/* 7 Effective A15, to ram, in text mode */
@@ -279,7 +279,7 @@ void dgn_beta_state::dgnbeta_vid_set_gctrl(int data)
}
-/* Write handler for colour, pallate ram */
+/* Write handler for colour, palette ram */
WRITE8_MEMBER(dgn_beta_state::dgnbeta_colour_ram_w)
{
m_ColourRAM[offset]=data&0x0f; /* Colour ram 4 bit and write only to CPU */
">CASSETTE_MOTOR_DISABLED, CASSETTE_MASK_MOTOR); } WRITE_LINE_MEMBER( ep64_state::write_centronics_busy ) { m_centronics_busy = state; } //------------------------------------------------- // rd1_r - //------------------------------------------------- READ8_MEMBER( ep64_state::rd1_r ) { /* bit description 0 KBJ 1 KBK 2 KBL 3 PRINTER _RDY 4 SERIAL/NET DATA IN 5 SERIAL/NET STATUS IN 6 CASSETTE IN 7 ? */ uint8_t data = 0; // printer data |= m_centronics_busy << 3; // serial data |= m_rs232->rxd_r() << 4; data |= m_rs232->cts_r() << 5; // cassette data |= ((m_cassette1->input() < 0) || (m_cassette2->input() < 0)) << 6; return data; } //------------------------------------------------- // wr2_w - //------------------------------------------------- WRITE8_MEMBER( ep64_state::wr2_w ) { /* bit description 0 SERIAL/NET DATA OUT 1 SERIAL/NET STATUS OUT 2 3 4 5 6 7 */ // serial m_rs232->write_txd(!BIT(data, 0)); m_rs232->write_rts(!BIT(data, 1)); } //************************************************************************** // ADDRESS MAPS //************************************************************************** //------------------------------------------------- // ADDRESS_MAP( ep64_mem ) //------------------------------------------------- static ADDRESS_MAP_START( ep64_mem, AS_PROGRAM, 8, ep64_state ) AM_RANGE(0x0000, 0xffff) AM_DEVICE(DAVE_TAG, dave_device, z80_program_map) ADDRESS_MAP_END //------------------------------------------------- // ADDRESS_MAP( ep64_io ) //------------------------------------------------- static ADDRESS_MAP_START( ep64_io, AS_IO, 8, ep64_state ) AM_RANGE(0x0000, 0xffff) AM_DEVICE(DAVE_TAG, dave_device, z80_io_map) ADDRESS_MAP_END //------------------------------------------------- // ADDRESS_MAP( dave_64k_mem ) //------------------------------------------------- static ADDRESS_MAP_START( dave_64k_mem, AS_PROGRAM, 8, ep64_state ) AM_RANGE(0x000000, 0x007fff) AM_ROM AM_REGION(Z80_TAG, 0) //AM_RANGE(0x010000, 0x01ffff) // mapped by the cartslot AM_RANGE(0x3f0000, 0x3fffff) AM_DEVICE(NICK_TAG, nick_device, vram_map) ADDRESS_MAP_END //------------------------------------------------- // ADDRESS_MAP( dave_128k_mem ) //------------------------------------------------- static ADDRESS_MAP_START( dave_128k_mem, AS_PROGRAM, 8, ep64_state ) AM_IMPORT_FROM(dave_64k_mem) AM_RANGE(0x3e0000, 0x3effff) AM_RAM ADDRESS_MAP_END //------------------------------------------------- // ADDRESS_MAP( dave_io ) //------------------------------------------------- static ADDRESS_MAP_START( dave_io, AS_IO, 8, ep64_state ) ADDRESS_MAP_GLOBAL_MASK(0xff) AM_RANGE(0x80, 0x8f) AM_DEVICE(NICK_TAG, nick_device, vio_map) AM_RANGE(0xb5, 0xb5) AM_READWRITE(rd0_r, wr0_w) AM_RANGE(0xb6, 0xb6) AM_READ(rd1_r) AM_DEVWRITE("cent_data_out", output_latch_device, write) AM_RANGE(0xb7, 0xb7) AM_WRITE(wr2_w) ADDRESS_MAP_END //************************************************************************** // INPUT PORTS //************************************************************************** //------------------------------------------------- // INPUT_PORTS( ep64 ) //------------------------------------------------- static INPUT_PORTS_START( ep64 ) PORT_START("Y0") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_TILDE) PORT_CHAR('\\') PORT_CHAR('|') PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B') PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C') PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V') PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X') PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Left SHIFT") PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1) PORT_START("Y1") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("LOCK") PORT_CODE(KEYCODE_CAPSLOCK) PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK)) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G') PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D') PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F') PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S') PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL) PORT_START("Y2") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q') PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y') PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R') PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T') PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E') PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("TAB") PORT_CODE(KEYCODE_TAB) PORT_CHAR('\t') PORT_START("Y3") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!') PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&') PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$') PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%') PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("3 \xC2\xA3") PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR(0x00a3) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("ESC") PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC)) PORT_START("Y4") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("FUNCTION 4") PORT_CODE(KEYCODE_F4) PORT_CHAR(UCHAR_MAMEKEY(F4)) PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("FUNCTION 8") PORT_CODE(KEYCODE_F8) PORT_CHAR(UCHAR_MAMEKEY(F8)) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("FUNCTION 3") PORT_CODE(KEYCODE_F3) PORT_CHAR(UCHAR_MAMEKEY(F3)) PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("FUNCTION 6") PORT_CODE(KEYCODE_F6) PORT_CHAR(UCHAR_MAMEKEY(F6)) PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("FUNCTION 5") PORT_CODE(KEYCODE_F5) PORT_CHAR(UCHAR_MAMEKEY(F5)) PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("FUNCTION 7") PORT_CODE(KEYCODE_F7) PORT_CHAR(UCHAR_MAMEKEY(F7)) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("FUNCTION 2") PORT_CODE(KEYCODE_F2) PORT_CHAR(UCHAR_MAMEKEY(F2)) PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("FUNCTION 1") PORT_CODE(KEYCODE_F1) PORT_CHAR(UCHAR_MAMEKEY(F1)) PORT_START("Y5") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')') PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('=') PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_0) PORT_CHAR('0') PORT_CHAR('_') PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('^') PORT_CHAR('~') PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("ERASE") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8) PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_START("Y6") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K') PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+') PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L') PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*') PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR(']') PORT_CHAR('}') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_START("Y7") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("STOP") PORT_CODE(KEYCODE_END) PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("HOLD") PORT_CODE(KEYCODE_HOME) PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("ENTER") PORT_CODE(KEYCODE_ENTER) PORT_CHAR('\r') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("ALT") PORT_CODE(KEYCODE_LALT) PORT_CHAR(UCHAR_MAMEKEY(LALT)) PORT_START("Y8") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("DEL") PORT_CODE(KEYCODE_DEL) PORT_CHAR(UCHAR_MAMEKEY(DEL)) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<') PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?') PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>') PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Right SHIFT") PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("SPACE") PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ') PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("INS") PORT_CODE(KEYCODE_INSERT) PORT_CHAR(UCHAR_MAMEKEY(INSERT)) PORT_START("Y9") PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I') PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O') PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@') PORT_CHAR('`') PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P') PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('[') PORT_CHAR('{') PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED ) INPUT_PORTS_END //************************************************************************** // MACHINE INITIALIZATION //************************************************************************** //------------------------------------------------- // MACHINE_START( ep64 ) //------------------------------------------------- void ep64_state::machine_start() { if (m_cart->exists()) m_dave->space(AS_PROGRAM).install_read_handler(0x010000, 0x01ffff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_cart)); // state saving save_item(NAME(m_key)); save_item(NAME(m_centronics_busy)); } void ep64_state::machine_reset() { m_dave->reset(); m_nick->reset(); address_space &program = m_maincpu->space(AS_PROGRAM); wr0_w(program, 0, 0); machine().device<output_latch_device>("cent_data_out")->write(program, 0, 0); wr2_w(program, 0, 0); } //************************************************************************** // MACHINE CONFIGURATION //************************************************************************** //------------------------------------------------- // MACHINE_CONFIG( ep64 ) //------------------------------------------------- static MACHINE_CONFIG_START( ep64, ep64_state ) // basic machine hardware MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_8MHz/2) MCFG_CPU_PROGRAM_MAP(ep64_mem) MCFG_CPU_IO_MAP(ep64_io) // video hardware MCFG_NICK_ADD(NICK_TAG, SCREEN_TAG, XTAL_8MHz) MCFG_NICK_VIRQ_CALLBACK(DEVWRITELINE(DAVE_TAG, dave_device, int1_w)) // sound hardware MCFG_DAVE_ADD(DAVE_TAG, XTAL_8MHz, dave_64k_mem, dave_io) MCFG_DAVE_IRQ_CALLBACK(INPUTLINE(Z80_TAG, INPUT_LINE_IRQ0)) // devices MCFG_EP64_EXPANSION_BUS_SLOT_ADD(EP64_EXPANSION_BUS_TAG, nullptr) MCFG_EP64_EXPANSION_BUS_SLOT_DAVE(DAVE_TAG) MCFG_EP64_EXPANSION_BUS_SLOT_IRQ_CALLBACK(INPUTLINE(Z80_TAG, INPUT_LINE_IRQ0)) MCFG_EP64_EXPANSION_BUS_SLOT_NMI_CALLBACK(INPUTLINE(Z80_TAG, INPUT_LINE_NMI)) MCFG_EP64_EXPANSION_BUS_SLOT_WAIT_CALLBACK(INPUTLINE(Z80_TAG, Z80_INPUT_LINE_BOGUSWAIT)) MCFG_CENTRONICS_ADD(CENTRONICS_TAG, centronics_devices, "printer") MCFG_CENTRONICS_BUSY_HANDLER(WRITELINE(ep64_state, write_centronics_busy)) MCFG_CENTRONICS_OUTPUT_LATCH_ADD("cent_data_out", CENTRONICS_TAG) MCFG_RS232_PORT_ADD(RS232_TAG, default_rs232_devices, nullptr) MCFG_RS232_CTS_HANDLER(DEVWRITELINE(DAVE_TAG, dave_device, int2_w)) MCFG_CASSETTE_ADD(CASSETTE1_TAG) MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED | CASSETTE_MOTOR_DISABLED | CASSETTE_SPEAKER_MUTED) MCFG_CASSETTE_INTERFACE("ep64_cass") MCFG_CASSETTE_ADD(CASSETTE2_TAG) MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED | CASSETTE_MOTOR_DISABLED | CASSETTE_SPEAKER_MUTED) MCFG_CASSETTE_INTERFACE("ep64_cass") // internal RAM MCFG_RAM_ADD(RAM_TAG) MCFG_RAM_DEFAULT_SIZE("64K") // cartridge MCFG_GENERIC_CARTSLOT_ADD("cartslot", generic_linear_slot, "ep64_cart") MCFG_GENERIC_EXTENSIONS("bin,rom") // software lists MCFG_SOFTWARE_LIST_ADD("cart_list", "ep64_cart") MCFG_SOFTWARE_LIST_ADD("cass_list", "ep64_cass") MCFG_SOFTWARE_LIST_ADD("flop_list", "ep64_flop") MACHINE_CONFIG_END //------------------------------------------------- // MACHINE_CONFIG( ep128 ) //------------------------------------------------- static MACHINE_CONFIG_DERIVED( ep128, ep64 ) MCFG_DEVICE_MODIFY(DAVE_TAG) MCFG_DEVICE_ADDRESS_MAP(AS_PROGRAM, dave_128k_mem) // internal RAM MCFG_RAM_MODIFY(RAM_TAG) MCFG_RAM_DEFAULT_SIZE("128K") MACHINE_CONFIG_END //************************************************************************** // ROMS //************************************************************************** //------------------------------------------------- // ROM( ep64 ) //------------------------------------------------- ROM_START( ep64 ) ROM_REGION( 0x8000, Z80_TAG, 0 ) ROM_LOAD( "9256ds-0038_enter05-23-a.u2", 0x0000, 0x8000, CRC(d421795f) SHA1(6033a0535136c40c47137e4d1cd9273c06d5fdff) ) ROM_END #define rom_phc64 rom_ep64 //------------------------------------------------- // ROM( ep128 ) //------------------------------------------------- ROM_START( ep128 ) ROM_REGION( 0x8000, Z80_TAG, 0 ) ROM_LOAD( "9256ds-0019_enter08-45-a.u2", 0x0000, 0x8000, CRC(982a3b44) SHA1(55315b20fecb4441a07ee4bc5dc7153f396e0a2e) ) ROM_END //************************************************************************** // SYSTEM DRIVERS //************************************************************************** // YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS COMP( 1985, ep64, 0, 0, ep64, ep64, driver_device, 0, "Enterprise Computers", "Enterprise Sixty Four", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) COMP( 1985, phc64, ep64, 0, ep64, ep64, driver_device, 0, "Hegener & Glaser", "Mephisto PHC 64 (Germany)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) COMP( 1986, ep128, ep64, 0, ep128, ep64, driver_device, 0, "Enterprise Computers", "Enterprise One Two Eight", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )