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author hap <happppp@users.noreply.github.com>2020-04-03 21:58:40 +0200
committer hap <happppp@users.noreply.github.com>2020-04-03 21:58:40 +0200
commitceabc2c79869168a6919eb4df205f4dc11c16006 (patch)
treea5267bc60ba7591de704c3b53d6d176bb8e85af0
parentd23f786a01a4b92b1800d256c6dc5b69290cb2f2 (diff)
cpu/alph8201 can be removed now (nw)
-rw-r--r--scripts/src/cpu.lua17
-rw-r--r--scripts/target/mame/arcade.lua1
-rw-r--r--scripts/target/mame/mess.lua1
-rw-r--r--src/devices/cpu/alph8201/8201dasm.cpp404
-rw-r--r--src/devices/cpu/alph8201/8201dasm.h51
-rw-r--r--src/devices/cpu/alph8201/alph8201.cpp698
-rw-r--r--src/devices/cpu/alph8201/alph8201.h415
-rw-r--r--src/mame/drivers/equites.cpp2
-rw-r--r--src/tools/unidasm.cpp2
9 files changed, 1 insertions, 1590 deletions
diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua
index a0dbdb27e35..3ce76c9e72c 100644
--- a/scripts/src/cpu.lua
+++ b/scripts/src/cpu.lua
@@ -198,23 +198,6 @@ if (CPUS["AMIS2000"]~=null or _OPTIONS["with-tools"]) then
end
--------------------------------------------------
--- Alpha 8201
---@src/devices/cpu/alph8201/alph8201.h,CPUS["ALPHA8201"] = true
---------------------------------------------------
-
-if (CPUS["ALPHA8201"]~=null) then
- files {
- MAME_DIR .. "src/devices/cpu/alph8201/alph8201.cpp",
- MAME_DIR .. "src/devices/cpu/alph8201/alph8201.h",
- }
-end
-
-if (CPUS["ALPHA8201"]~=null or _OPTIONS["with-tools"]) then
- table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/alph8201/8201dasm.cpp")
- table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/alph8201/8201dasm.h")
-end
-
---------------------------------------------------
-- Analog Devices ADSP21xx series
--@src/devices/cpu/adsp2100/adsp2100.h,CPUS["ADSP21XX"] = true
--------------------------------------------------
diff --git a/scripts/target/mame/arcade.lua b/scripts/target/mame/arcade.lua
index 04256c705bc..a23f7e6d066 100644
--- a/scripts/target/mame/arcade.lua
+++ b/scripts/target/mame/arcade.lua
@@ -79,7 +79,6 @@ CPUS["MC68HC11"] = true
CPUS["ADSP21062"] = true
CPUS["DSP56156"] = true
CPUS["RSP"] = true
-CPUS["ALPHA8201"] = true
CPUS["COP400"] = true
CPUS["TLCS90"] = true
CPUS["TLCS870"] = true
diff --git a/scripts/target/mame/mess.lua b/scripts/target/mame/mess.lua
index 47aa48a379a..62c6299743b 100644
--- a/scripts/target/mame/mess.lua
+++ b/scripts/target/mame/mess.lua
@@ -79,7 +79,6 @@ CPUS["MC68HC11"] = true
CPUS["ADSP21062"] = true
CPUS["DSP56156"] = true
CPUS["RSP"] = true
-CPUS["ALPHA8201"] = true
CPUS["COP400"] = true
CPUS["TLCS90"] = true
CPUS["TLCS900"] = true
diff --git a/src/devices/cpu/alph8201/8201dasm.cpp b/src/devices/cpu/alph8201/8201dasm.cpp
deleted file mode 100644
index cf24aff16b3..00000000000
--- a/src/devices/cpu/alph8201/8201dasm.cpp
+++ /dev/null
@@ -1,404 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Tatsuyuki Satoh
-/*
-
-Notice: The alpha 8201 is now emulated using mame/alpha8201.*
-
-cpu/alph8201/ will be removed when the alpha 8304 has been dumped.
-
-
-
-
-*/
-
-/****************************************************************************
- Alpha 8201/8301 Disassembler
-
- Copyright Tatsuyuki Satoh
- Originally written for the MAME project.
-
-****************************************************************************/
-
-#include "emu.h"
-#include "8201dasm.h"
-
-#include <cctype>
-#include <stdexcept>
-
-
-#define FMT(a,b) a, b
-#define PTRS_PER_FORMAT 2
-
-/****************************************************
-
-8201 CONFIRMED OPCODES:
-
-opcode mnemonic function flags
--------- ------------ ------------- -----
-00000000 NOP - --
-00000001 RORA ror A -C
-00000010 ROLA rol A -C
-00000011 INC RXB RXB+=2 ZC
-00000100 DEC RXB RXB-=2 ZC (C=1 means No Borrow: RXB>=2)
-00000101 INC A A++ ZC
-00000110 DEC A A-- ZC (C=1 means No Borrow: A>=1)
-00000110 CPL A A^=$FF --
-00001aaa LD A,(IX0+i) A=[IX0+i] --
-00010aaa LD A,(IX1+i) A=[IX1+i] --
-00011aaa LD (IX2+i),A [IX2+i]=A --
-00111aaa BIT R0.n ZF=R0 bit n Z-
-0100aaa0 LD A,Rn A=Rn Z- [1]
-0100aaa1 LD Rn,A Rn=A --
-0101aaa0 ADD A,Rn A+=Rn ZC
-0101aaa1 SUB A,Rn A-=Rn ZC (C=1 means No Borrow: A>=Rn)
-0110aaa0 AND A,Rn A&=Rn Z-
-0110aaa1 OR A,Rn A|=Rn Z-
-0111aaaa ADD IX0,i IX0+=i --
-1000aaaa ADD IX1,i IX1+=i --
-1001aaaa ADD IX2,i IX2+=i --
-1010aaaa LD RB,i RB=i -- Note: no bounds checking. Can set bank up to F.
-1011-0aa LD MB,i set after-jump page
-1011-1-- STOP
-11000000 imm LD IX0,imm IX0=imm --
-11000001 imm LD IX1,imm IX1=imm --
-11000010 imm LD IX2,imm IX2=imm --
-11000011 imm LD A,imm A=imm --
-11000100 imm LD LP0,imm LP0=imm --
-11000101 imm LD LP1,imm LP1=imm --
-11000110 imm LD LP2,imm LP2=imm --
-11000111 imm LD RXB,imm RXB=imm --
-11001000 imm ADD A,imm A+=imm ZC
-11001001 imm SUB A,imm A-=imm ZC (C=1 means No Borrow: A>=imm)
-11001010 imm AND A,imm A&=imm Z-
-11001011 imm OR A,imm A|=imm Z-
-11001100 imm DJNZ LP0,imm LP0--,branch --
-11001101 imm DJNZ LP1,imm LP1--,branch --
-11001110 imm DJNZ LP2,imm LP2--,branch --
-11001111 imm JNZ imm branch if !Z --
-1101--00 imm JNC imm branch if !C --
-1101--01 imm JZ imm branch if Z --
-1101--1- imm J imm branch --
-1110--xx mirror for the above
-1111--xx mirror for the above
-
-Notes:
-[1] bug: the Z flag is not updated correctly after a LD A,Rn instruction. Fixed in 8302 (possibly 8301).
-
-
-8302 CONFIRMED OPCODES:
-----------------------
-all of the 8201 ones, with stricter decoding for the following:
-
-11010-00 imm JNC imm branch if !C --
-11010-01 imm JZ imm branch if Z --
-11010-1- imm J imm branch --
-
-and these new opcodes:
-
-opcode mnemonic function flags
--------- ------------ --------------- -----
-11011000 imm LD A,(imm) A=MB:[imm] --
-11011001 imm LD (imm),A MB:[imm]=A --
-11011010 imm CMP A,imm temp=A-imm ZC
-11011011 imm XOR A,imm A^=imm Z0
-11011100 imm LD A,R(imm) A=reg(imm) --
-11011101 imm LD R(imm),A reg(imm)=A --
-11011110 imm JC imm branch if C --
-11011111 imm CALL $xx save PC, branch --
-
-11100000 EXG A,IX0 A<->IX0 --
-11100001 EXG A,IX1 A<->IX1 --
-11100010 EXG A,IX2 A<->IX2 --
-11100011 EXG A,LP1 A<->LP1 --
-11100100 EXG A,LP2 A<->LP2 --
-11100101 EXG A,RXB A<->RXB --
-11100110 EXG A,LP0 A<->LP0 --
-11100111 EXG A,RB A<->RB --
-11101000 LD IX0,A IX0=A --
-11101001 LD IX1,A IX1=A --
-11101010 LD IX2,A IX2=A --
-11101011 LD LP1,A LP1=A --
-11101100 LD LP2,A LP2=A --
-11101101 LD RXB,A RXB=A --
-11101110 LD LP0,A LP0=A --
-11101111 LD RB,A RB=A --
-11110000 EXG IX0,IX1 IX0<->IX1 --
-11110001 EXG IX0,IX2 IX0<->IX2 --
-11110010 REP LD (IX2),(RXB) equivalent to LD (IX2),(RXB); INC RXB; DJNZ LP0
-11110011 REP LD (RXB),(IX0) equivalent to LD (RXB),(IX0); INC RXB; DJNZ LP0
-11110100 SAVE ZC save ZC --
-11110101 REST ZC restore ZC ZC
-11110110 LD (RXB),A reg(RXB)=A --
-11110111 LD A,(RXB) A=reg(RXB) --
-11111000 CMP A,(RXB) temp=A-reg(RXB) ZC
-11111001 XOR A,(RXB) A^=reg(RXB) Z0
-11111010 ADD A,CF if (C) A++ ZC
-11111011 SUB A,!CF if (!C) A-- ZC
-11111100 TST A A==0? Z-
-11111101 CLR A A=0 --
-11111110 LD A,(IX0+A) A=[IX0+A] --
-11111111 RET restore PC --
-
-
-8303 CONFIRMED OPCODES:
-----------------------
-all of the 8302 ones, with stricter decoding for the following:
-
-11010000 imm JNC imm branch if !C --
-11010001 imm JZ imm branch if Z --
-1101001- imm J imm branch --
-
-additionally, this opcode is modified to support 11-bit instead of 10-bit
-external addressing, this wasn't used in games however.
-
-1011-0aa LD MB,i modified so that bit 3 is shifted to bit 2 before loading MB.
-
-and these new opcodes are added:
-
-110101--
-11010100 imm LD A,(R77:$%02X)
-11010101 imm LD (R77:$%02X),A
-11010110 imm LD PC,(R77:$%02X) [1]
-11010111 imm LD (R77:$%02X),PC [2]
-
-Notes:
-[1] appears to be LD PC,x in the disassembly, however it's LD LP0,x for kouyakyu
- which uses a 8304, so the opcode was probably changed again.
-[2] appears to be LD x,PC in the disassembly, however it's LD x,LP0 for hvoltage
- which uses a 8304 (or 8404?), so the opcode was probably changed again.
-
-****************************************************/
-
-
-/****************************************************/
-
-const char *const alpha8201_disassembler::Formats[] = {
- FMT("0000_0000", "NOP"), // 00
- FMT("0000_0001", "RRCA"), // 01
- FMT("0000_0010", "RLCA"), // 02
- FMT("0000_0011", "INC RXB"), // 03 : shougi $360 to $377; splndrbt
- FMT("0000_0100", "DEC RXB"), // 04 : not found
- FMT("0000_0101", "INC A"), // 05
- FMT("0000_0110", "DEC A"), // 06
- FMT("0000_0111", "CPL A"), // 07
- FMT("0000_1aaa", "LD A,(IX0+%X)"), // 08-0F
- FMT("0001_0aaa", "LD A,(IX1+%X)"), // 10-17
- FMT("0001_1aaa", "LD (IX2+%X),A"), // 18-1F
- FMT("0010_0aaa", "LD (RXB),(IX0+%X)"),// 20-27 : shougi $360 to $377
- FMT("0010_1aaa", "LD (RXB),(IX1+%X)"),// 28-2f : not found
- FMT("0011_0aaa", "LD (IX2+%X),(RXB)"),// 30-37 : not found
- FMT("0011_1aaa", "BIT R0.%d"), // 38-3F ZF = R0.a (bit test)
- FMT("0100_aaa0", "LD A,R%X"), // 40-4E
- FMT("0100_aaa1", "LD R%X,A"), // 41-4F
- FMT("0101_aaa0", "ADD A,R%X"), // 50-5E
- FMT("0101_aaa1", "SUB A,R%X"), // 51-5F
- FMT("0110_aaa0", "AND A,R%X"), // 60-6E
- FMT("0110_aaa1", "OR A,R%X"), // 61-6F
- FMT("0111_aaaa", "ADD IX0,$%X"), // 70-7f
- FMT("1000_aaaa", "ADD IX1,$%X"), // 80-8f
- FMT("1001_aaaa", "ADD IX2,$%X"), // 90-9f
- FMT("1010_aaaa", "LD RB,%X"), // A0-AF
- FMT("1011_x0aa", "LD MB,%X"), // B0-B3 (+ mirrors)
- FMT("1011_x1xx", "STOP"), // B4 (+ mirrors)
-
- FMT("1100_0000 I", "LD IX0,$%02X"), // C0
- FMT("1100_0001 I", "LD IX1,$%02X"), // C1
- FMT("1100_0010 I", "LD IX2,$%02X"), // C2
- FMT("1100_0011 I", "LD A,$%02X"), // C3
- FMT("1100_0100 I", "LD LP0,$%02X"), // C4
- FMT("1100_0101 I", "LD LP1,$%02X"), // C5
- FMT("1100_0110 I", "LD LP2,$%02X"), // C6
- FMT("1100_0111 I", "LD RXB,$%02X"), // C7 : shougi, splndrbt, equites
- FMT("1100_1000 I", "ADD A,$%02X"), // C8
- FMT("1100_1001 I", "SUB A,$%02X"), // C9
- FMT("1100_1010 I", "AND A,$%02X"), // CA
- FMT("1100_1011 I", "OR A,$%02X"), // CB
- FMT("1100_1100 I", "DJNZ LP0,$%02X"), // CC
- FMT("1100_1101 I", "DJNZ LP1,$%02X"), // CD
- FMT("1100_1110 I", "DJNZ LP2,$%02X"), // CE
- FMT("1100_1111 I", "JNZ $%02X"), // CF
- FMT("1101_0000 I", "JNC $%02X"), // D0
- FMT("1101_0001 I", "JZ $%02X"), // D1
- FMT("1101_001x I", "J $%02X"), // D2 (+ mirror)
-
- /* -------------- 830x only ------------- */
-
- FMT("1101_0100 I", "LD A,(R77:$%02X)"), // D4 : 8303+ only. exctscc2, bullfgtr
- FMT("1101_0101 I", "LD (R77:$%02X),A"), // D5 : 8303+ only. exctscc2, bullfgtr, kouyakyu
- FMT("1101_0110 I", "LD LP0,(R77:$%02X)"), // D6 : 8303+ only. kouyakyu
- FMT("1101_0111 I", "LD (R77:$%02X),LP0"), // D7 : 8303+ only. hvoltage
- FMT("1101_1000 I", "LD A,($%02X)"), // D8 : equites
- FMT("1101_1001 I", "LD ($%02X),A"), // D9 : equites
- FMT("1101_1010 I", "CMP A,$%02X"), // DA :
- FMT("1101_1011 I", "XOR A,$%02X"), // DB : equites splndrbt
- FMT("1101_1100 I", "LD A,R($%02X)"), // DC : not found
- FMT("1101_1101 I", "LD R($%02X),A"), // DD : equites, splndrbt
- FMT("1101_1110 I", "JC $%02X"), // DE : not found
- FMT("1101_1111 I", "CALL $%02X"), // DF :
-
- FMT("1110_0000", "EXG A,IX0"), // E0 : exctsccr
- FMT("1110_0001", "EXG A,IX1"), // E1 : not found
- FMT("1110_0010", "EXG A,IX2"), // E2 : not found
- FMT("1110_0011", "EXG A,LP1"), // E3 : exctsccr in pair with EB
- FMT("1110_0100", "EXG A,LP2"), // E4 : not found
- FMT("1110_0101", "EXG A,RXB"), // E5 : splndrbt
- FMT("1110_0110", "EXG A,LP0"), // E6 : splndrbt, bullfgtr, kouyakyu. EXG, not LD: see splndrbt $3ba to $3d3
- FMT("1110_0111", "EXG A,RB"), // E7 : not found
- FMT("1110_1000", "LD IX0,A"), // E8 :
- FMT("1110_1001", "LD IX1,A"), // E9 : not found
- FMT("1110_1010", "LD IX2,A"), // EA :
- FMT("1110_1011", "LD LP1,A"), // EB : exctsccr in pair with E3
- FMT("1110_1100", "LP LP2,A"), // EC : not found
- FMT("1110_1101", "LD RXB,A"), // ED : splndrbt
- FMT("1110_1110", "LD LP0,A"), // EE : splndrbt, bullfgtr
- FMT("1110_1111", "LD RB,A"), // EF : not found
- FMT("1111_0000", "EXG IX0,IX1"), // F0 : not found
- FMT("1111_0001", "EXG IX0,IX2"), // F1 : splndrbt $2e to $38, equites $40 to $4a
- FMT("1111_0010", "REP LD (IX2),(RXB)"),// F2 : splndrbt LD (IX2),(RXB); INC RXB; DJNZ LP0
- FMT("1111_0011", "REP LD (RXB),(IX0)"),// F3 : not found LD (RXB),(IX0); INC RXB; DJNZ LP0
- FMT("1111_0100", "SAVE ZC"), // F4 : not found
- FMT("1111_0101", "REST ZC"), // F5 : not found
- FMT("1111_0110", "LD (RXB),A"), // F6 : exctsccr
- FMT("1111_0111", "LD A,(RXB)"), // F7 : not found
- FMT("1111_1000", "CMP A,(RXB)"), // F8 : exctsccr
- FMT("1111_1001", "XOR A,(RXB)"), // F9 : exctsccr
- FMT("1111_1010", "ADD A,CF"), // FA :
- FMT("1111_1011", "SUB A,!CF"), // FB : not found
- FMT("1111_1100", "TST A"), // FC :
- FMT("1111_1101", "CLR A"), // FD :
- FMT("1111_1110", "LD A,(IX0+A)"), // FE :
- FMT("1111_1111", "RET"), // FF :
- nullptr
-};
-
-alpha8201_disassembler::alpha8201_disassembler()
-{
- const char *p;
- u8 mask, bits;
- int bit;
- int i;
- char chr , type;
- int pmask , pdown;
-
- for(i=0;(p=Formats[i*2])!=nullptr;i++)
- {
- mask = 0;
- bits = 0;
- pmask = 0;
- pdown = 0;
- type = 0;
- bit = 7;
- while (*p && bit >= 0) {
- chr = *p++;
- switch (chr) {
- case '1': bits |= 1<<bit;
- case '0': mask |= 1<<bit; bit--; break;
-#if 0
- case 'b':
- type |= 0x80;
-#endif
- case 'a':
- pmask |= 1<<bit;
- pdown = bit;
- case 'x':
- bit--;
- break;
- case '_':
- continue;
- default:
- throw std::logic_error(util::string_format("Invalid instruction encoding '%s %s'\n", Formats[i*2],Formats[i*2+1]));
- }
- }
- if (bit != -1) {
- throw std::logic_error(util::string_format("not enough bits in encoding '%s %s' %d\n", Formats[i*2],Formats[i*2+1],bit));
- }
-
- Op[i].mask = mask;
- Op[i].bits = bits;
- Op[i].pmask = pmask;
- Op[i].pdown = pdown;
- Op[i].fmt = Formats[i*2+1];
- Op[i].type = type;
-
- /* 2 byte code ? */
- while (isspace(u8(*p))) p++;
- if( (*p) )
- Op[i].type |= 0x10;
- /* number of param */
- if( (p=strchr(Op[i].fmt,'%'))!=nullptr )
- {
- Op[i].type |= 0x01; /* single param */
- if(strchr(p+1,'%') )
- Op[i].type |= 0x02; /* double param */
- }
- }
- op_count = i;
-}
-
-offs_t alpha8201_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params)
-{
- offs_t dasmflags = 0;
- int i;
- int op;
- int cnt = 1;
- int code , disp;
-
- code = opcodes.r8(pc);
- op = -1; /* no matching opcode */
- for ( i = 0; i < op_count; i++)
- {
- if( (code & Op[i].mask) == Op[i].bits )
- {
- if (op != -1)
- {
- fprintf(stderr, "Error: opcode %02X matches %d (%s) and %d (%s)\n",
- code,i,Op[i].fmt,op,Op[op].fmt);
- }
- op = i;
- }
- }
-
- if (op == -1)
- {
- util::stream_format(stream, "db %2.2x",code);
- return cnt;
- }
-
- if (Op[op].type & 0x10)
- {
- disp = params.r8(pc+1);
- cnt++;
- }
- else
- {
- disp = (code & Op[op].pmask) >> Op[op].pdown;
- }
-
- if (Op[op].type & 0x02)
- util::stream_format(stream, Op[op].fmt,disp,disp);
- else if (Op[op].type & 0x01)
- util::stream_format(stream, Op[op].fmt,disp);
- else
- util::stream_format(stream, "%s",Op[op].fmt);
-
- switch (code)
- {
- case 0xcc:
- case 0xcd:
- case 0xce:
- case 0xdf:
- dasmflags = STEP_OVER;
- break;
-
- case 0xff:
- dasmflags = STEP_OUT;
- break;
- }
-
- return cnt | dasmflags | SUPPORTED;
-}
-
-u32 alpha8201_disassembler::opcode_alignment() const
-{
- return 1;
-}
diff --git a/src/devices/cpu/alph8201/8201dasm.h b/src/devices/cpu/alph8201/8201dasm.h
deleted file mode 100644
index 85676c5de10..00000000000
--- a/src/devices/cpu/alph8201/8201dasm.h
+++ /dev/null
@@ -1,51 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Tatsuyuki Satoh
-/*
-
-Notice: The alpha 8201 is now emulated using mame/alpha8201.*
-
-cpu/alph8201/ will be removed when the alpha 8304 has been dumped.
-
-
-
-
-*/
-
-/****************************************************************************
- Alpha 8201/8301 Disassembler
-
- Copyright Tatsuyuki Satoh
- Originally written for the MAME project.
-
-****************************************************************************/
-
-#ifndef MAME_CPU_ALPH8201_8201DASM_H
-#define MAME_CPU_ALPH8201_8201DASM_H
-
-#pragma once
-
-class alpha8201_disassembler : public util::disasm_interface
-{
-public:
- alpha8201_disassembler();
- virtual ~alpha8201_disassembler() = default;
-
- virtual u32 opcode_alignment() const override;
- virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params) override;
-
-private:
- struct AD8201Opcode {
- u8 mask;
- u8 bits;
- u8 type;
- u8 pmask;
- u8 pdown;
- const char *fmt;
- };
-
- static const char *const Formats[];
- AD8201Opcode Op[256];
- int op_count;
-};
-
-#endif
diff --git a/src/devices/cpu/alph8201/alph8201.cpp b/src/devices/cpu/alph8201/alph8201.cpp
deleted file mode 100644
index 3d007a8e523..00000000000
--- a/src/devices/cpu/alph8201/alph8201.cpp
+++ /dev/null
@@ -1,698 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Tatsuyuki Satoh
-/*
-
-Notice: The alpha 8201 is now emulated using mame/alpha8201.*
-
-cpu/alph8201/ will be removed when the alpha 8304 has been dumped.
-
-
-
-
-*/
-
-/****************************************************************************
- Alpha8201 Emulator
-
- Copyright Tatsuyuki Satoh
- Originally written for the MAME project.
-
-
-The Alpha8201/830x isn't a real CPU. It is a Hitachi HD44801 4-bit MCU,
-programmed to interpret an external program using a custom instruction set.
-Alpha8301 has an expanded instruction set, backwards compatible with Alpha8201
-
-The internal ROM hasn't been read (yet), so here we provide a simulation of
-the behaviour.
-
-
-Game Year MCU
------------------------- ---- ----
-Shougi 1982? 8201 (pcb)
-Shougi 2 1982? 8201 (pcb)
-Talbot 1982 8201?
-Champion Base Ball 1983 8201 (schematics)
-Exciting Soccer 1983 8302 (pcb)
-Champion Base Ball II 1983 8302 (pcb, unofficial schematics)
-Exciting Soccer II 1984 8303 (uses 8303+ opcodes)
-Equites 1984 8303 (post)
-Bull Fighter 1984 8303 (post)
-Splendor Blast 1985 8303 (post)
-Gekisou 1985 8304 (post)
-The Koukou Yakyuu 1985 8304 (post)
-High Voltage 1985 8304?(post says 8404, but readme says 8304)
-Bingo Time 1986 8505
-
-ALPHA-8201: "44801A75" -> HD44801, ROM code = A75
-ALPHA-8302: "44801B35" -> HD44801, ROM code = B35
-ALPHA-8303: "44801B42" -> HD44801, ROM code = B42
-ALPHA-8304: ?
-ALPHA-8505: "44801C57" -> HD44801, ROM code = C57
-
-
- Notes :
- some unknown instruction are not emulated.
-
- Because there was no information, opcode-syntax was created.
-
- TODO:
- verify with real chip or analyze more.
- -A lot of 8301 opcode.
- -memory address 000 specification
- -memory address 001 bit 7-5 specification
- -write value after HALT operation to ODD of vector memory.
- -operation cycle(execution speed).
-
-****************************************************************************/
-
-/****************************************************************************
-
------------------------
-package / pin assign
------------------------
-ALPHA 8201 DIP 42
-
-pin HD44801 Alpha
---- ------- -----
-1 : D3 WR
-2-4 : D4-D6 n.c.
-5-7 : D7-D9 GND in shougi , n.c. in champbas
-8-13 : D10-D15 n.c.
-14 : n.c. n.c.
-15 : RESET RESET
-16 : GND GND
-17 : OSC1 (champbas=384KHz)
-18 : OSC2 n.c.
-19 : !HLT Vcc
-20 : !TEST Vcc
-21 : Vcc Vcc
-22-25: R00-R03 DB4-DB7
-26-29: R10-R13 DB0-DB3
-30 : INT0 GO (input)
-31 : INT1 n.c.
-32-35: R20-R23 A4-A7
-36-39: R30-R33 A0-A3
-40-41: D0-D1 A8-A9
-42 : D2 /RD
-
-
------------------------
-Register Set
------------------------
-
-PC : 10bit Program Pointer
- A lower 8bits are loaded from the immidate.
- A higher 2bits are loaded from the MB register.
-
-MB : 2bit memory bank register, load PC[9:8] after branch
- load high to higher 2bit of PC after branch.
-
-RB : 3bit register bank select register
-
-R0-R7 : internal? RAM register 8bitx8 (x8 bank)
-
-A : 8bit
-
-cpustate->IX0/1 : memory indirect 'read' access pointer
-
-cpustate->IX2 : memory indirect 'write' access pointer
-
-RXB : unknown , looks index register
-
-cpustate->LP0/1/2 : loop count register used by DJNZ operation
-
-cpustate->cf : carry flag
-cpustate->zf : zero flag
-
------------------------
-Memoy Space
------------------------
-
-000 : unknown ...
-001 : bit4..0 = pointer of current entry , bit7..6 = unknown
-002-003 : entrypoint1 vector
-004-005 : entrypoint2 vector
-006-007 : entrypoint3 vector
-008-009 : entrypoint4 vector
-00A-00B : entrypoint5 vector
-00C-00D : entrypoint6 vector
-00E-00F : entrypoint7 vector
-010-011 : entrypoint8 vector
-012-013 : entrypoint9 vector
-014-015 : entrypoint10 vector
-016-017 : entrypoint11 vector
-018-019 : entrypoint12 vector
-01A-01B : entrypoint13 vector
-01C-01D : entrypoint14 vector
-01E-01F : entrypoint15 vector
-020-0FF : bank 0, program / data memory
-100-1FF : bank 1, program / data memory
-200-2FF : bank 2, program / data memory
-300-3FF : bank 3, program / data memory
-
-The even address is the lower byte of the entry address.
-The odd-address of entry point is a MB and status.
- Bit 0 and 1 are a memory bank.
- Bit 2 is HALT.At the time of set, it doesn't execute entry address.
- After EXIT operation, Bit2 is set.
-
------------------------
-Timming
------------------------
-
-****************************************************************************/
-
-#include "emu.h"
-#include "alph8201.h"
-#include "debugger.h"
-#include "8201dasm.h"
-
-DEFINE_DEVICE_TYPE(ALPHA8201L, alpha8201_cpu_device, "alpha8201l", "ALPHA-8201L")
-DEFINE_DEVICE_TYPE(ALPHA8301L, alpha8301_cpu_device, "alpha8301l", "ALPHA-8301L")
-
-
-/* instruction cycle count */
-#define C1 16
-#define C2 32
-
-/* debug option */
-#define TRACE_PC 0
-#define SHOW_ENTRY_POINT 0
-#define SHOW_MESSAGE_CONSOLE 0
-#define BREAK_ON_UNKNOWN_OPCODE 0
-#define BREAK_ON_UNCERTAIN_OPCODE 0
-
-
-#define FN(x) &alpha8201_cpu_device::x
-
-
-alpha8201_cpu_device::alpha8201_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
- : alpha8201_cpu_device(mconfig, ALPHA8201L, tag, owner, clock, opcode_8201)
-{
-}
-
-
-alpha8201_cpu_device::alpha8201_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, const s_opcode *opmap)
- : cpu_device(mconfig, type, tag, owner, clock)
- , m_program_config("program", ENDIANNESS_LITTLE, 8, 10, 0)
- , m_io_config("io", ENDIANNESS_LITTLE, 8, 6, 0)
- , m_opmap(opmap)
-{
-}
-
-alpha8301_cpu_device::alpha8301_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
- : alpha8201_cpu_device(mconfig, ALPHA8301L, tag, owner, clock, opcode_8301)
-{
-}
-
-device_memory_interface::space_config_vector alpha8201_cpu_device::memory_space_config() const
-{
- return space_config_vector {
- std::make_pair(AS_PROGRAM, &m_program_config),
- std::make_pair(AS_IO, &m_io_config)
- };
-}
-
-/* Get next opcode argument and increment program counter */
-unsigned alpha8201_cpu_device::M_RDMEM_OPCODE()
-{
- unsigned retval;
- retval=M_RDOP_ARG(m_pc.w.l);
- m_pc.b.l++;
- return retval;
-}
-
-void alpha8201_cpu_device::M_ADD(u8 dat)
-{
- u16 temp = m_A + dat;
- m_A = temp & 0xff;
- m_zf = (m_A==0);
- m_cf = temp>>8;
-}
-
-void alpha8201_cpu_device::M_ADDB(u8 dat)
-{
- u16 temp = m_B + dat;
- m_B = temp & 0xff;
- m_zf = (m_B==0);
- m_cf = temp>>8;
-}
-
-void alpha8201_cpu_device::M_SUB(u8 dat)
-{
- m_cf = (m_A>=dat); // m_cf is No Borrow
- m_A -= dat;
- m_zf = (m_A==0);
-}
-
-void alpha8201_cpu_device::M_AND(u8 dat)
-{
- m_A &= dat;
- m_zf = (m_A==0);
-}
-
-void alpha8201_cpu_device::M_OR(u8 dat)
-{
- m_A |= dat;
- m_zf = (m_A==0);
-}
-
-void alpha8201_cpu_device::M_XOR(u8 dat)
-{
- m_A ^= dat;
- m_zf = (m_A==0);
- m_cf = 0;
-}
-
-void alpha8201_cpu_device::M_JMP(u8 dat)
-{
- m_pc.b.l = dat;
- /* update pc page */
- m_pc.b.h = m_ix0.b.h = m_ix1.b.h = m_ix2.b.h = m_mb & 3;
-}
-
-void alpha8201_cpu_device::M_UNDEFINED()
-{
- logerror("alpha8201: PC = %03x, Unimplemented opcode = %02x\n", m_pc.w.l-1, M_RDMEM(m_pc.w.l-1));
-#if SHOW_MESSAGE_CONSOLE
- osd_printf_debug("alpha8201: PC = %03x, Unimplemented opcode = %02x\n", m_pc.w.l-1, M_RDMEM(m_pc.w.l-1));
-#endif
-#if BREAK_ON_UNKNOWN_OPCODE
- machine().debug_break();
-#endif
-}
-
-void alpha8201_cpu_device::M_UNDEFINED2()
-{
- u8 op = M_RDOP(m_pc.w.l-1);
- u8 imm = M_RDMEM_OPCODE();
- logerror("alpha8201: PC = %03x, Unimplemented opcode = %02x,%02x\n", m_pc.w.l-2, op,imm);
-#if SHOW_MESSAGE_CONSOLE
- osd_printf_debug("alpha8201: PC = %03x, Unimplemented opcode = %02x,%02x\n", m_pc.w.l-2, op,imm);
-#endif
-#if BREAK_ON_UNKNOWN_OPCODE
- machine().debug_break();
-#endif
-}
-
-
-void alpha8201_cpu_device::stop()
-{
- u8 pcptr = M_RDMEM(0x001) & 0x1f;
- M_WRMEM(pcptr,(M_RDMEM(pcptr)&0xf)+0x08); /* mark entry point ODD to HALT */
- m_mb |= 0x08; /* mark internal HALT state */
-}
-
-
-const alpha8201_cpu_device::s_opcode alpha8201_cpu_device::opcode_8201[256]=
-{
- {C1, FN(nop) },{C1,FN(rora) },{C1, FN(rola) },{C1,FN(inc_b) },{C1,FN(dec_b) },{C1, FN(inc_a) },{C1, FN(dec_a) },{C1, FN(cpl) },
- {C2,FN(ld_a_ix0_0) },{C2,FN(ld_a_ix0_1)},{C2, FN(ld_a_ix0_2)},{C2,FN(ld_a_ix0_3)},{C2,FN(ld_a_ix0_4)},{C2,FN(ld_a_ix0_5)},{C2,FN(ld_a_ix0_6)},{C2,FN(ld_a_ix0_7)},
- {C2,FN(ld_a_ix1_0) },{C2,FN(ld_a_ix1_1)},{C2, FN(ld_a_ix1_2)},{C2,FN(ld_a_ix1_3)},{C2,FN(ld_a_ix1_4)},{C2,FN(ld_a_ix1_5)},{C2,FN(ld_a_ix1_6)},{C2,FN(ld_a_ix1_7)},
- {C2,FN(ld_ix2_0_a) },{C2,FN(ld_ix2_1_a)},{C2, FN(ld_ix2_2_a)},{C2,FN(ld_ix2_3_a)},{C2,FN(ld_ix2_4_a)},{C2,FN(ld_ix2_5_a)},{C2,FN(ld_ix2_6_a)},{C2,FN(ld_ix2_7_a)},
-/* 20 */
- {C2,FN(ld_ix0_0_b) },{C2,FN(ld_ix0_1_b)},{C2, FN(ld_ix0_2_b)},{C2,FN(ld_ix0_3_b)},{C2,FN(ld_ix0_4_b)},{C2,FN(ld_ix0_5_b)},{C2,FN(ld_ix0_6_b)},{C2,FN(ld_ix0_7_b)},
- {C2,FN(undefined) },{C2,FN(undefined) },{C2, FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },
- {C2,FN(undefined) },{C2,FN(undefined) },{C2, FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },
- {C2,FN(bit_r0_0) },{C2,FN(bit_r0_1) },{C2, FN(bit_r0_2) },{C2, FN(bit_r0_3) },{C2, FN(bit_r0_4) },{C2, FN(bit_r0_5) },{C2, FN(bit_r0_6) },{C2, FN(bit_r0_7) },
-/* 40 : 8201 */
- {C2, FN(ld_a_r0) },{C2, FN(ld_r0_a) },{C2, FN(ld_a_r1) },{C2, FN(ld_r1_a) },{C2, FN(ld_a_r2) },{C2, FN(ld_r2_a) },{C2, FN(ld_a_r3) },{C2, FN(ld_r3_a) },
- {C2, FN(ld_a_r4) },{C2, FN(ld_r4_a) },{C2, FN(ld_a_r5) },{C2, FN(ld_r5_a) },{C2, FN(ld_a_r6) },{C2, FN(ld_r6_a) },{C2, FN(ld_a_r7) },{C2, FN(ld_r7_a) },
- {C1, FN(add_a_r0) },{C1, FN(sub_a_r0) },{C1, FN(add_a_r1) },{C1, FN(sub_a_r1) },{C1, FN(add_a_r2) },{C1, FN(sub_a_r2) },{C1, FN(add_a_r3) },{C1, FN(sub_a_r3) },
- {C1, FN(add_a_r4) },{C1, FN(sub_a_r4) },{C1, FN(add_a_r5) },{C1, FN(sub_a_r5) },{C1, FN(add_a_r6) },{C1, FN(sub_a_r6) },{C1, FN(add_a_r7) },{C1, FN(sub_a_r7) },
- {C1, FN(and_a_r0) },{C1, FN(or_a_r0) },{C1, FN(and_a_r1) },{C1, FN(or_a_r1) },{C1, FN(and_a_r2) },{C1, FN(or_a_r2) },{C1, FN(and_a_r3) },{C1, FN(or_a_r3) },
- {C1, FN(and_a_r4) },{C1, FN(or_a_r4) },{C1, FN(and_a_r5) },{C1, FN(or_a_r5) },{C1, FN(and_a_r6) },{C1, FN(or_a_r6) },{C1, FN(and_a_r7) },{C1, FN(or_a_r7) },
- {C1, FN(add_ix0_0) },{C1, FN(add_ix0_1)},{C1, FN(add_ix0_2)},{C1, FN(add_ix0_3)},{C1, FN(add_ix0_4)},{C1, FN(add_ix0_5)},{C1, FN(add_ix0_6)},{C1, FN(add_ix0_7)},
- {C1, FN(add_ix0_8) },{C1, FN(add_ix0_9)},{C1, FN(add_ix0_a)},{C1, FN(add_ix0_b)},{C1, FN(add_ix0_c)},{C1, FN(add_ix0_d)},{C1, FN(add_ix0_e)},{C1, FN(add_ix0_f)},
-/* 80 : 8201 */
- {C1, FN(add_ix1_0) },{C1, FN(add_ix1_1)},{C1, FN(add_ix1_2)},{C1, FN(add_ix1_3)},{C1, FN(add_ix1_4)},{C1, FN(add_ix1_5)},{C1, FN(add_ix1_6)},{C1, FN(add_ix1_7)},
- {C1, FN(add_ix1_8) },{C1, FN(add_ix1_9)},{C1, FN(add_ix1_a)},{C1, FN(add_ix1_b)},{C1, FN(add_ix1_c)},{C1, FN(add_ix1_d)},{C1, FN(add_ix1_e)},{C1, FN(add_ix1_f)},
- {C1, FN(add_ix2_0) },{C1, FN(add_ix2_1)},{C1, FN(add_ix2_2)},{C1, FN(add_ix2_3)},{C1, FN(add_ix2_4)},{C1, FN(add_ix2_5)},{C1, FN(add_ix2_6)},{C1, FN(add_ix2_7)},
- {C1, FN(add_ix2_8) },{C1, FN(add_ix2_9)},{C1, FN(add_ix2_a)},{C1, FN(add_ix2_b)},{C1, FN(add_ix2_c)},{C1, FN(add_ix2_d)},{C1, FN(add_ix2_e)},{C1, FN(add_ix2_f)},
- {C1, FN(ld_base_0) },{C1, FN(ld_base_1)},{C1, FN(ld_base_2)},{C1, FN(ld_base_3)},{C1, FN(ld_base_4)},{C1, FN(ld_base_5)},{C1, FN(ld_base_6)},{C1, FN(ld_base_7)},
- {C1, FN(undefined) },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
- {C1, FN(ld_bank_0) },{C1, FN(ld_bank_1)},{C1, FN(ld_bank_2)},{C1, FN(ld_bank_3)},{C2, FN(stop) },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
- {C1, FN(undefined) },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
-/* c0 : 8201 */
- {C2, FN(ld_ix0_n) },{C2, FN(ld_ix1_n) },{C2, FN(ld_ix2_n) },{C2, FN(ld_a_n) },{C2, FN(ld_lp0_n) },{C2, FN(ld_lp1_n) },{C2, FN(ld_lp2_n) },{C2, FN(ld_b_n) },
- {C2, FN(add_a_n) },{C2, FN(sub_a_n) },{C2, FN(and_a_n) },{C2, FN(or_a_n) },{C2, FN(djnz_lp0) },{C2, FN(djnz_lp1) },{C2, FN(djnz_lp2) },{C2, FN(jnz) },
- {C2, FN(jnc) },{C2, FN(jz) },{C2, FN(jmp) },{C2,FN(undefined2)},{C2,FN(undefined2)},{C2,FN(undefined2)},{C2,FN(undefined2)},{C2, FN(undefined2)},
- {C2, FN(undefined2) },{C2,FN(undefined2)},{C2,FN(undefined2)},{C2,FN(undefined2)},{C2,FN(undefined2)},{C2,FN(undefined2)},{C2,FN(undefined2)},{C2, FN(undefined2)},
-/* E0 : 8201*/
- {C1, FN(undefined) },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
- {C1, FN(undefined) },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
- {C1, FN(undefined) },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
- {C1, FN(undefined) },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined) }
-};
-
-
-const alpha8201_cpu_device::s_opcode alpha8201_cpu_device::opcode_8301[256]=
-{
- {C1, FN(nop) },{C1,FN(rora) },{C1, FN(rola) },{C1,FN(inc_b) },{C1,FN(dec_b) },{C1, FN(inc_a) },{C1, FN(dec_a) },{C1, FN(cpl) },
- {C2,FN(ld_a_ix0_0) },{C2,FN(ld_a_ix0_1)},{C2, FN(ld_a_ix0_2)},{C2,FN(ld_a_ix0_3)},{C2,FN(ld_a_ix0_4)},{C2,FN(ld_a_ix0_5)},{C2,FN(ld_a_ix0_6)},{C2,FN(ld_a_ix0_7)},
- {C2,FN(ld_a_ix1_0) },{C2,FN(ld_a_ix1_1)},{C2, FN(ld_a_ix1_2)},{C2,FN(ld_a_ix1_3)},{C2,FN(ld_a_ix1_4)},{C2,FN(ld_a_ix1_5)},{C2,FN(ld_a_ix1_6)},{C2,FN(ld_a_ix1_7)},
- {C2,FN(ld_ix2_0_a) },{C2,FN(ld_ix2_1_a)},{C2, FN(ld_ix2_2_a)},{C2,FN(ld_ix2_3_a)},{C2,FN(ld_ix2_4_a)},{C2,FN(ld_ix2_5_a)},{C2,FN(ld_ix2_6_a)},{C2,FN(ld_ix2_7_a)},
-/* 20 : 8301 */
- {C2,FN(ld_ix0_0_b) },{C2,FN(ld_ix0_1_b)},{C2, FN(ld_ix0_2_b)},{C2,FN(ld_ix0_3_b)},{C2,FN(ld_ix0_4_b)},{C2,FN(ld_ix0_5_b)},{C2,FN(ld_ix0_6_b)},{C2,FN(ld_ix0_7_b)},
- {C2,FN(undefined) },{C2,FN(undefined) },{C2, FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },
- {C2,FN(undefined) },{C2,FN(undefined) },{C2, FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },{C2,FN(undefined) },
- {C2,FN(bit_r0_0) },{C2,FN(bit_r0_1) },{C2, FN(bit_r0_2) },{C2, FN(bit_r0_3) },{C2, FN(bit_r0_4) },{C2, FN(bit_r0_5) },{C2, FN(bit_r0_6) },{C2, FN(bit_r0_7) },
-/* 40 : 8301 */
- {C2, FN(ld_a_r0) },{C2, FN(ld_r0_a) },{C2, FN(ld_a_r1) },{C2, FN(ld_r1_a) },{C2, FN(ld_a_r2) },{C2, FN(ld_r2_a) },{C2, FN(ld_a_r3) },{C2, FN(ld_r3_a) },
- {C2, FN(ld_a_r4) },{C2, FN(ld_r4_a) },{C2, FN(ld_a_r5) },{C2, FN(ld_r5_a) },{C2, FN(ld_a_r6) },{C2, FN(ld_r6_a) },{C2, FN(ld_a_r7) },{C2, FN(ld_r7_a) },
- {C1, FN(add_a_r0) },{C1, FN(sub_a_r0) },{C1, FN(add_a_r1) },{C1, FN(sub_a_r1) },{C1, FN(add_a_r2) },{C1, FN(sub_a_r2) },{C1, FN(add_a_r3) },{C1, FN(sub_a_r3) },
- {C1, FN(add_a_r4) },{C1, FN(sub_a_r4) },{C1, FN(add_a_r5) },{C1, FN(sub_a_r5) },{C1, FN(add_a_r6) },{C1, FN(sub_a_r6) },{C1, FN(add_a_r7) },{C1, FN(sub_a_r7) },
-/* 60 : 8301 */
- {C1, FN(and_a_r0) },{C1, FN(or_a_r0) },{C1, FN(and_a_r1) },{C1, FN(or_a_r1) },{C1, FN(and_a_r2) },{C1, FN(or_a_r2) },{C1, FN(and_a_r3) },{C1, FN(or_a_r3) },
- {C1, FN(and_a_r4) },{C1, FN(or_a_r4) },{C1, FN(and_a_r5) },{C1, FN(or_a_r5) },{C1, FN(and_a_r6) },{C1, FN(or_a_r6) },{C1, FN(and_a_r7) },{C1, FN(or_a_r7) },
- {C1, FN(add_ix0_0) },{C1, FN(add_ix0_1)},{C1, FN(add_ix0_2)},{C1, FN(add_ix0_3)},{C1, FN(add_ix0_4)},{C1, FN(add_ix0_5)},{C1, FN(add_ix0_6)},{C1, FN(add_ix0_7)},
- {C1, FN(add_ix0_8) },{C1, FN(add_ix0_9)},{C1, FN(add_ix0_a)},{C1, FN(add_ix0_b)},{C1, FN(add_ix0_c)},{C1, FN(add_ix0_d)},{C1, FN(add_ix0_e)},{C1, FN(add_ix0_f)},
-/* 80 : 8301 */
- {C1, FN(add_ix1_0) },{C1, FN(add_ix1_1)},{C1, FN(add_ix1_2)},{C1, FN(add_ix1_3)},{C1, FN(add_ix1_4)},{C1, FN(add_ix1_5)},{C1, FN(add_ix1_6)},{C1, FN(add_ix1_7)},
- {C1, FN(add_ix1_8) },{C1, FN(add_ix1_9)},{C1, FN(add_ix1_a)},{C1, FN(add_ix1_b)},{C1, FN(add_ix1_c)},{C1, FN(add_ix1_d)},{C1, FN(add_ix1_e)},{C1, FN(add_ix1_f)},
- {C1, FN(add_ix2_0) },{C1, FN(add_ix2_1)},{C1, FN(add_ix2_2)},{C1, FN(add_ix2_3)},{C1, FN(add_ix2_4)},{C1, FN(add_ix2_5)},{C1, FN(add_ix2_6)},{C1, FN(add_ix2_7)},
- {C1, FN(add_ix2_8) },{C1, FN(add_ix2_9)},{C1, FN(add_ix2_a)},{C1, FN(add_ix2_b)},{C1, FN(add_ix2_c)},{C1, FN(add_ix2_d)},{C1, FN(add_ix2_e)},{C1, FN(add_ix2_f)},
-/* A0 : 8301 */
- {C1, FN(ld_base_0) },{C1, FN(ld_base_1)},{C1, FN(ld_base_2)},{C1, FN(ld_base_3)},{C1, FN(ld_base_4)},{C1, FN(ld_base_5)},{C1, FN(ld_base_6)},{C1, FN(ld_base_7)},
- {C1, FN(undefined) },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
- {C1, FN(ld_bank_0) },{C1, FN(ld_bank_1)},{C1, FN(ld_bank_2)},{C1, FN(ld_bank_3)},{C2, FN(stop) },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
- {C1, FN(undefined) },{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},{C1, FN(undefined)},
-/* c0 : 8301 */
- {C2, FN(ld_ix0_n) },{C2, FN(ld_ix1_n)},{C2, FN(ld_ix2_n) },{C2, FN(ld_a_n) },{C2, FN(ld_lp0_n) },{C2, FN(ld_lp1_n) },{C2, FN(ld_lp2_n) },{C2, FN(ld_b_n) },
- {C2, FN(add_a_n) },{C2, FN(sub_a_n) },{C2, FN(and_a_n) },{C2, FN(or_a_n) },{C2, FN(djnz_lp0) },{C2, FN(djnz_lp1) },{C2, FN(djnz_lp2) },{C2, FN(jnz) },
- {C2, FN(jnc) },{C2, FN(jz) },{C2, FN(jmp) },{C2,FN(undefined2)},{C2, FN(op_d4) },{C2, FN(op_d5) },{C2, FN(op_d6) },{C2, FN(op_d7) },
- {C2, FN(ld_a_abs) },{C2, FN(ld_abs_a)},{C2,FN(cmp_a_n) },{C2,FN(xor_a_n) },{C2, FN(ld_a_r) },{C2, FN(ld_r_a) },{C2, FN(jc) },{C2, FN(call)},
-/* E0 : 8301 */
- {C1, FN(exg_a_ix0) },{C1, FN(exg_a_ix1)},{C1, FN(exg_a_ix2)},{C1, FN(exg_a_lp1)},{C1, FN(exg_a_lp2)},{C1, FN(exg_a_b) },{C1, FN(exg_a_lp0)},{C1, FN(exg_a_rb) },
- {C1, FN(ld_ix0_a) },{C1, FN(ld_ix1_a) },{C1, FN(ld_ix2_a) },{C1, FN(ld_lp1_a) },{C1, FN(ld_lp2_a) },{C1, FN(ld_b_a) },{C1, FN(ld_lp0_a) },{C1, FN(ld_rb_a) },
- {C1,FN(exg_ix0_ix1)},{C1,FN(exg_ix0_ix2)},{C1,FN(op_rep_ld_ix2_b)},{C1, FN(op_rep_ld_b_ix0)},{C1, FN(save_zc)},{C1, FN(rest_zc)},{C1, FN(ld_rxb_a) },{C1, FN(ld_a_rxb) },
- {C1, FN(cmp_a_rxb) },{C1, FN(xor_a_rxb)},{C1, FN(add_a_cf) },{C1, FN(sub_a_cf) },{C1, FN(tst_a) },{C1, FN(clr_a) },{C1, FN(ld_a_ix0_a)},{C1, FN(ret) }
-};
-
-
-/****************************************************************************
- * Initialize emulation
- ****************************************************************************/
-void alpha8201_cpu_device::device_start()
-{
- m_program = &space(AS_PROGRAM);
- m_cache = m_program->cache<0, 0, ENDIANNESS_LITTLE>();
-
- state_add( ALPHA8201_PC, "PC", m_pc.w.l ).callimport().mask(0x3ff).formatstr("%03X");
- state_add( ALPHA8201_SP, "SP", m_sp ).callimport().callexport().formatstr("%02X");
- state_add( ALPHA8201_RB, "RB", m_regPtr ).mask(0x7);
- state_add( ALPHA8201_MB, "MB", m_mb ).mask(0x3);
- state_add( ALPHA8201_IX0, "IX0", m_ix0.b.l );
- state_add( ALPHA8201_IX1, "IX1", m_ix1.b.l );
- state_add( ALPHA8201_IX2, "IX2", m_ix2.b.l );
- state_add( ALPHA8201_LP0, "LP0", m_lp0 );
- state_add( ALPHA8201_LP1, "LP1", m_lp1 );
- state_add( ALPHA8201_LP2, "LP2", m_lp2 );
- state_add( ALPHA8201_A, "A", m_A );
- state_add( ALPHA8201_B, "B", m_B );
- state_add( ALPHA8201_R0, "R0", m_R[0] ).callimport().callexport().formatstr("%02X");
- state_add( ALPHA8201_R1, "R1", m_R[1] ).callimport().callexport().formatstr("%02X");
- state_add( ALPHA8201_R2, "R2", m_R[2] ).callimport().callexport().formatstr("%02X");
- state_add( ALPHA8201_R3, "R3", m_R[3] ).callimport().callexport().formatstr("%02X");
- state_add( ALPHA8201_R4, "R4", m_R[4] ).callimport().callexport().formatstr("%02X");
- state_add( ALPHA8201_R5, "R5", m_R[5] ).callimport().callexport().formatstr("%02X");
- state_add( ALPHA8201_R6, "R6", m_R[6] ).callimport().callexport().formatstr("%02X");
- state_add( ALPHA8201_R7, "R7", m_R[7] ).callimport().callexport().formatstr("%02X");
- state_add( STATE_GENPCBASE, "CURPC", m_PREVPC ).callimport().noshow();
- state_add( STATE_GENFLAGS, "CURFLAGS", m_flags ).callimport().callexport().formatstr("%2s").noshow();
- state_add( STATE_GENSP, "CURSP", m_sp ).callimport().callexport();
-
- save_item(NAME(m_RAM));
- save_item(NAME(m_PREVPC));
- save_item(NAME(m_pc.w.l));
- save_item(NAME(m_regPtr));
- save_item(NAME(m_zf));
- save_item(NAME(m_cf));
- save_item(NAME(m_mb));
- save_item(NAME(m_halt));
- save_item(NAME(m_ix0.b.l));
- save_item(NAME(m_ix1.b.l));
- save_item(NAME(m_ix2.b.l));
- save_item(NAME(m_lp0));
- save_item(NAME(m_lp1));
- save_item(NAME(m_lp2));
- save_item(NAME(m_A));
- save_item(NAME(m_B));
- save_item(NAME(m_retptr));
- save_item(NAME(m_savec));
- save_item(NAME(m_savez));
-
- set_icountptr(m_icount);
-}
-
-
-//-------------------------------------------------
-// state_import - import state into the device,
-// after it has been set
-//-------------------------------------------------
-
-void alpha8201_cpu_device::state_import(const device_state_entry &entry)
-{
- switch (entry.index())
- {
- case ALPHA8201_PC:
- m_PREVPC = m_pc.w.l;
- break;
-
- case STATE_GENPCBASE:
- m_pc.w.l = m_PREVPC;
- break;
-
- case STATE_GENFLAGS:
- m_cf = BIT(m_flags, 1);
- m_zf = BIT(m_flags, 0);
- break;
-
- case ALPHA8201_SP:
- case STATE_GENSP:
- M_WRMEM(0x001, m_sp);
- break;
-
- case ALPHA8201_R0:
- WR_REG(0, m_R[0]);
- break;
-
- case ALPHA8201_R1:
- WR_REG(1, m_R[1]);
- break;
-
- case ALPHA8201_R2:
- WR_REG(2, m_R[2]);
- break;
-
- case ALPHA8201_R3:
- WR_REG(3, m_R[3]);
- break;
-
- case ALPHA8201_R4:
- WR_REG(4, m_R[4]);
- break;
-
- case ALPHA8201_R5:
- WR_REG(5, m_R[5]);
- break;
-
- case ALPHA8201_R6:
- WR_REG(6, m_R[6]);
- break;
-
- case ALPHA8201_R7:
- WR_REG(7, m_R[7]);
- break;
- }
-}
-
-
-//-------------------------------------------------
-// state_export - export state from the device,
-// to a known location where it can be read
-//-------------------------------------------------
-
-void alpha8201_cpu_device::state_export(const device_state_entry &entry)
-{
- switch (entry.index())
- {
- case STATE_GENFLAGS:
- m_flags = (m_cf << 1) | m_zf;
- break;
-
- case ALPHA8201_SP:
- case STATE_GENSP:
- m_sp = M_RDMEM(0x001);
- break;
-
- case ALPHA8201_R0:
- m_R[0] = RD_REG(0);
- break;
-
- case ALPHA8201_R1:
- m_R[1] = RD_REG(1);
- break;
-
- case ALPHA8201_R2:
- m_R[2] = RD_REG(2);
- break;
-
- case ALPHA8201_R3:
- m_R[3] = RD_REG(3);
- break;
-
- case ALPHA8201_R4:
- m_R[4] = RD_REG(4);
- break;
-
- case ALPHA8201_R5:
- m_R[5] = RD_REG(5);
- break;
-
- case ALPHA8201_R6:
- m_R[6] = RD_REG(6);
- break;
-
- case ALPHA8201_R7:
- m_R[7] = RD_REG(7);
- break;
- }
-}
-
-
-//-------------------------------------------------
-// state_string_export - export state as a string
-// for the debugger
-//-------------------------------------------------
-
-void alpha8201_cpu_device::state_string_export(const device_state_entry &entry, std::string &str) const
-{
- switch (entry.index())
- {
- case STATE_GENFLAGS:
- str = string_format("%c%c", m_cf ? 'C' : '.', m_zf ? 'Z' : '.');
- break;
- }
-}
-
-/****************************************************************************
- * Reset registers to their initial values
- ****************************************************************************/
-void alpha8201_cpu_device::device_reset()
-{
- m_pc.w.l = 0;
- m_regPtr = 0;
- m_zf = 0;
- m_cf = 0;
- m_mb = 0;
- m_ix0.w.l = 0;
- m_ix1.w.l = 0;
- m_ix2.w.l = 0;
- m_lp0 = 0;
- m_lp1 = 0;
- m_lp2 = 0;
- m_A = 0;
- m_B = 0;
- m_halt = 0;
-}
-
-
-/****************************************************************************
- * Execute cycles CPU cycles. Return number of cycles really executed
- ****************************************************************************/
-
-void alpha8201_cpu_device::execute_run()
-{
- unsigned opcode;
- u8 pcptr;
-
- if(m_halt)
- {
- m_icount = 0;
- return;
- }
-
- /* setup address bank & fall safe */
- m_ix0.b.h =
- m_ix1.b.h =
- m_ix2.b.h = (m_pc.b.h &= 3);
-
- /* reset start hack */
- if(m_pc.w.l<0x20)
- m_mb |= 0x08;
-
- do
- {
- if(m_mb & 0x08)
- {
- pcptr = M_RDMEM(0x001) & 0x1f; /* pointer of entry point */
- m_icount -= C1;
-
- /* entry point scan phase */
- if( (pcptr&1) == 0)
- {
- /* EVEN , get PC low */
- m_pc.b.l = M_RDMEM(pcptr);
-//osd_printf_debug("alpha8201 load PCL ENTRY=%02X PCL=%02X\n",pcptr, m_pc.b.l);
- m_icount -= C1;
- M_WRMEM(0x001,pcptr+1);
- continue;
- }
-
- /* ODD , check HALT flag */
- m_mb = M_RDMEM(pcptr) & (0x08|0x03);
- m_icount -= C1;
-
- /* not entryaddress 000,001 */
- if(pcptr<2) m_mb |= 0x08;
-
- if(m_mb & 0x08)
- {
- /* HALTED current entry point . next one */
- pcptr = (pcptr+1)&0x1f;
- M_WRMEM(0x001,pcptr);
- m_icount -= C1;
- continue;
- }
-
- /* goto run phase */
- M_JMP(m_pc.b.l);
-
-#if SHOW_ENTRY_POINT
-logerror("alpha8201 START ENTRY=%02X PC=%03X\n",pcptr,m_pc.w.l);
-osd_printf_debug("alpha8201 START ENTRY=%02X PC=%03X\n",pcptr,m_pc.w.l);
-#endif
- }
-
- /* run */
- m_PREVPC = m_pc.w.l;
- debugger_instruction_hook(m_pc.w.l);
- opcode =M_RDOP(m_pc.w.l);
-#if TRACE_PC
-osd_printf_debug("alpha8201: PC = %03x, opcode = %02x\n", m_pc.w.l, opcode);
-#endif
- m_pc.b.l++;
- m_inst_cycles = m_opmap[opcode].cycles;
- (this->*m_opmap[opcode].opcode_func)();
- m_icount -= m_inst_cycles;
- } while (m_icount>0);
-}
-
-
-/****************************************************************************
- * Set IRQ line state
- ****************************************************************************/
-void alpha8201_cpu_device::execute_set_input(int inputnum, int state)
-{
- if(inputnum == INPUT_LINE_HALT)
- {
- m_halt = (state==ASSERT_LINE) ? 1 : 0;
-/* osd_printf_debug("alpha8201 HALT %d\n",m_halt); */
- }
-}
-
-std::unique_ptr<util::disasm_interface> alpha8201_cpu_device::create_disassembler()
-{
- return std::make_unique<alpha8201_disassembler>();
-}
diff --git a/src/devices/cpu/alph8201/alph8201.h b/src/devices/cpu/alph8201/alph8201.h
deleted file mode 100644
index fa735606215..00000000000
--- a/src/devices/cpu/alph8201/alph8201.h
+++ /dev/null
@@ -1,415 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Tatsuyuki Satoh
-/*
-
-Notice: The alpha 8201 is now emulated using mame/alpha8201.*
-
-cpu/alph8201/ will be removed when the alpha 8304 has been dumped.
-
-
-
-
-*/
-
- /**************************************************************************\
- * Alpha8201 Emulator *
- * *
- * Copyright Tatsuyuki Satoh *
- * Originally written for the MAME project. *
- * *
- * *
- \**************************************************************************/
-
-#ifndef MAME_CPU_ALPH8201_ALPH8201_H
-#define MAME_CPU_ALPH8201_ALPH8201_H
-
-#pragma once
-
-enum
-{
- ALPHA8201_PC = STATE_GENPC,
- ALPHA8201_SP = 0,
- ALPHA8201_RB,
- ALPHA8201_MB,
-//
- ALPHA8201_IX0,
- ALPHA8201_IX1,
- ALPHA8201_IX2,
- ALPHA8201_LP0,
- ALPHA8201_LP1,
- ALPHA8201_LP2,
- ALPHA8201_A,
- ALPHA8201_B,
-//
- ALPHA8201_R0,ALPHA8201_R1,ALPHA8201_R2,ALPHA8201_R3,
- ALPHA8201_R4,ALPHA8201_R5,ALPHA8201_R6,ALPHA8201_R7
-};
-
-
-class alpha8201_cpu_device : public cpu_device
-{
-public:
- // construction/destruction
- alpha8201_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
-
-protected:
- typedef void ( alpha8201_cpu_device::*opcode_fun ) ();
-
- /* The opcode table now is a combination of cycle counts and function pointers */
- struct s_opcode {
- unsigned cycles;
- opcode_fun opcode_func;
- };
-
- alpha8201_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, const s_opcode *opmap);
-
- // device-level overrides
- virtual void device_start() override;
- virtual void device_reset() override;
-
- // device_execute_interface overrides
- virtual u32 execute_min_cycles() const noexcept override { return 1; }
- virtual u32 execute_max_cycles() const noexcept override { return 16; }
- virtual u32 execute_input_lines() const noexcept override { return 1; }
- virtual void execute_run() override;
- virtual void execute_set_input(int inputnum, int state) override;
-
- // device_memory_interface overrides
- virtual space_config_vector memory_space_config() const override;
-
- // device_state_interface overrides
- virtual void state_import(const device_state_entry &entry) override;
- virtual void state_export(const device_state_entry &entry) override;
- virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
-
- // device_disasm_interface overrides
- virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
-
- u8 M_RDMEM(u16 A) { return m_program->read_byte(A); }
- void M_WRMEM(u16 A, u8 V) { m_program->write_byte(A, V); }
- u8 M_RDOP(u16 A) { return m_cache->read_byte(A); }
- u8 M_RDOP_ARG(u16 A) { return m_cache->read_byte(A); }
- u8 RD_REG(u8 x) { return m_RAM[(m_regPtr<<3)+(x)]; }
- void WR_REG(u8 x, u8 d) { m_RAM[(m_regPtr<<3)+(x)]=(d); }
-
- unsigned M_RDMEM_OPCODE();
- void M_ADD(u8 dat);
- void M_ADDB(u8 dat);
- void M_SUB(u8 dat);
- void M_AND(u8 dat);
- void M_OR(u8 dat);
- void M_XOR(u8 dat);
- void M_JMP(u8 dat);
- void M_UNDEFINED();
- void M_UNDEFINED2();
-
- void undefined() { M_UNDEFINED(); }
- void undefined2() { M_UNDEFINED2(); }
-
- void nop() { }
- void rora() { m_cf = m_A &1; m_A = (m_A>>1) | (m_A<<7); }
- void rola() { m_cf = (m_A>>7)&1; m_A = (m_A<<1) | (m_A>>7); }
- void inc_b() { M_ADDB(0x02); }
- void dec_b() { M_ADDB(0xfe); }
- void inc_a() { M_ADD(0x01); }
- void dec_a() { M_ADD(0xff); }
- void cpl() { m_A ^= 0xff; };
-
- void ld_a_ix0_0() { m_A = M_RDMEM(m_ix0.w.l+0); }
- void ld_a_ix0_1() { m_A = M_RDMEM(m_ix0.w.l+1); }
- void ld_a_ix0_2() { m_A = M_RDMEM(m_ix0.w.l+2); }
- void ld_a_ix0_3() { m_A = M_RDMEM(m_ix0.w.l+3); }
- void ld_a_ix0_4() { m_A = M_RDMEM(m_ix0.w.l+4); }
- void ld_a_ix0_5() { m_A = M_RDMEM(m_ix0.w.l+5); }
- void ld_a_ix0_6() { m_A = M_RDMEM(m_ix0.w.l+6); }
- void ld_a_ix0_7() { m_A = M_RDMEM(m_ix0.w.l+7); }
-
- void ld_a_ix1_0() { m_A = M_RDMEM(m_ix1.w.l+0); }
- void ld_a_ix1_1() { m_A = M_RDMEM(m_ix1.w.l+1); }
- void ld_a_ix1_2() { m_A = M_RDMEM(m_ix1.w.l+2); }
- void ld_a_ix1_3() { m_A = M_RDMEM(m_ix1.w.l+3); }
- void ld_a_ix1_4() { m_A = M_RDMEM(m_ix1.w.l+4); }
- void ld_a_ix1_5() { m_A = M_RDMEM(m_ix1.w.l+5); }
- void ld_a_ix1_6() { m_A = M_RDMEM(m_ix1.w.l+6); }
- void ld_a_ix1_7() { m_A = M_RDMEM(m_ix1.w.l+7); }
-
- void ld_ix2_0_a() { M_WRMEM(m_ix2.w.l+0,m_A); }
- void ld_ix2_1_a() { M_WRMEM(m_ix2.w.l+1,m_A); }
- void ld_ix2_2_a() { M_WRMEM(m_ix2.w.l+2,m_A); }
- void ld_ix2_3_a() { M_WRMEM(m_ix2.w.l+3,m_A); }
- void ld_ix2_4_a() { M_WRMEM(m_ix2.w.l+4,m_A); }
- void ld_ix2_5_a() { M_WRMEM(m_ix2.w.l+5,m_A); }
- void ld_ix2_6_a() { M_WRMEM(m_ix2.w.l+6,m_A); }
- void ld_ix2_7_a() { M_WRMEM(m_ix2.w.l+7,m_A); }
-
- void ld_ix0_0_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+0); }
- void ld_ix0_1_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+1); }
- void ld_ix0_2_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+2); }
- void ld_ix0_3_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+3); }
- void ld_ix0_4_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+4); }
- void ld_ix0_5_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+5); }
- void ld_ix0_6_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+6); }
- void ld_ix0_7_b() { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l+7); }
-
- void bit_r0_0() { m_zf = RD_REG(0)&(1<<0)?0:1; }
- void bit_r0_1() { m_zf = RD_REG(0)&(1<<1)?0:1; }
- void bit_r0_2() { m_zf = RD_REG(0)&(1<<2)?0:1; }
- void bit_r0_3() { m_zf = RD_REG(0)&(1<<3)?0:1; }
- void bit_r0_4() { m_zf = RD_REG(0)&(1<<4)?0:1; }
- void bit_r0_5() { m_zf = RD_REG(0)&(1<<5)?0:1; }
- void bit_r0_6() { m_zf = RD_REG(0)&(1<<6)?0:1; }
- void bit_r0_7() { m_zf = RD_REG(0)&(1<<7)?0:1; }
-
- void ld_a_n() { m_A = M_RDMEM_OPCODE(); }
-
- void ld_a_r0() { m_A = RD_REG(0); m_zf = (m_A==0); }
- void ld_a_r1() { m_A = RD_REG(1); m_zf = (m_A==0); }
- void ld_a_r2() { m_A = RD_REG(2); m_zf = (m_A==0); }
- void ld_a_r3() { m_A = RD_REG(3); m_zf = (m_A==0); }
- void ld_a_r4() { m_A = RD_REG(4); m_zf = (m_A==0); }
- void ld_a_r5() { m_A = RD_REG(5); m_zf = (m_A==0); }
- void ld_a_r6() { m_A = RD_REG(6); m_zf = (m_A==0); }
- void ld_a_r7() { m_A = RD_REG(7); m_zf = (m_A==0); }
-
- void ld_r0_a() { WR_REG(0,m_A); }
- void ld_r1_a() { WR_REG(1,m_A); }
- void ld_r2_a() { WR_REG(2,m_A); }
- void ld_r3_a() { WR_REG(3,m_A); }
- void ld_r4_a() { WR_REG(4,m_A); }
- void ld_r5_a() { WR_REG(5,m_A); }
- void ld_r6_a() { WR_REG(6,m_A); }
- void ld_r7_a() { WR_REG(7,m_A); }
-
- void add_a_n() { M_ADD(M_RDMEM_OPCODE()); }
-
- void add_a_r0() { M_ADD(RD_REG(0)); }
- void add_a_r1() { M_ADD(RD_REG(1)); }
- void add_a_r2() { M_ADD(RD_REG(2)); }
- void add_a_r3() { M_ADD(RD_REG(3)); }
- void add_a_r4() { M_ADD(RD_REG(4)); }
- void add_a_r5() { M_ADD(RD_REG(5)); }
- void add_a_r6() { M_ADD(RD_REG(6)); }
- void add_a_r7() { M_ADD(RD_REG(7)); }
-
- void sub_a_n() { M_SUB(M_RDMEM_OPCODE()); }
-
- void sub_a_r0() { M_SUB(RD_REG(0)); }
- void sub_a_r1() { M_SUB(RD_REG(1)); }
- void sub_a_r2() { M_SUB(RD_REG(2)); }
- void sub_a_r3() { M_SUB(RD_REG(3)); }
- void sub_a_r4() { M_SUB(RD_REG(4)); }
- void sub_a_r5() { M_SUB(RD_REG(5)); }
- void sub_a_r6() { M_SUB(RD_REG(6)); }
- void sub_a_r7() { M_SUB(RD_REG(7)); }
-
- void and_a_n() { M_AND(M_RDMEM_OPCODE()); }
-
- void and_a_r0() { M_AND(RD_REG(0)); }
- void and_a_r1() { M_AND(RD_REG(1)); }
- void and_a_r2() { M_AND(RD_REG(2)); }
- void and_a_r3() { M_AND(RD_REG(3)); }
- void and_a_r4() { M_AND(RD_REG(4)); }
- void and_a_r5() { M_AND(RD_REG(5)); }
- void and_a_r6() { M_AND(RD_REG(6)); }
- void and_a_r7() { M_AND(RD_REG(7)); }
-
- void or_a_n() { M_OR(M_RDMEM_OPCODE()); }
-
- void or_a_r0() { M_OR(RD_REG(0)); }
- void or_a_r1() { M_OR(RD_REG(1)); }
- void or_a_r2() { M_OR(RD_REG(2)); }
- void or_a_r3() { M_OR(RD_REG(3)); }
- void or_a_r4() { M_OR(RD_REG(4)); }
- void or_a_r5() { M_OR(RD_REG(5)); }
- void or_a_r6() { M_OR(RD_REG(6)); }
- void or_a_r7() { M_OR(RD_REG(7)); }
-
- void add_ix0_0() { }
- void add_ix0_1() { m_ix0.b.l += 1; }
- void add_ix0_2() { m_ix0.b.l += 2; }
- void add_ix0_3() { m_ix0.b.l += 3; }
- void add_ix0_4() { m_ix0.b.l += 4; }
- void add_ix0_5() { m_ix0.b.l += 5; }
- void add_ix0_6() { m_ix0.b.l += 6; }
- void add_ix0_7() { m_ix0.b.l += 7; }
- void add_ix0_8() { m_ix0.b.l += 8; }
- void add_ix0_9() { m_ix0.b.l += 9; }
- void add_ix0_a() { m_ix0.b.l += 10; }
- void add_ix0_b() { m_ix0.b.l += 11; }
- void add_ix0_c() { m_ix0.b.l += 12; }
- void add_ix0_d() { m_ix0.b.l += 13; }
- void add_ix0_e() { m_ix0.b.l += 14; }
- void add_ix0_f() { m_ix0.b.l += 15; }
-
- void add_ix1_0() { }
- void add_ix1_1() { m_ix1.b.l += 1; }
- void add_ix1_2() { m_ix1.b.l += 2; }
- void add_ix1_3() { m_ix1.b.l += 3; }
- void add_ix1_4() { m_ix1.b.l += 4; }
- void add_ix1_5() { m_ix1.b.l += 5; }
- void add_ix1_6() { m_ix1.b.l += 6; }
- void add_ix1_7() { m_ix1.b.l += 7; }
- void add_ix1_8() { m_ix1.b.l += 8; }
- void add_ix1_9() { m_ix1.b.l += 9; }
- void add_ix1_a() { m_ix1.b.l += 10; }
- void add_ix1_b() { m_ix1.b.l += 11; }
- void add_ix1_c() { m_ix1.b.l += 12; }
- void add_ix1_d() { m_ix1.b.l += 13; }
- void add_ix1_e() { m_ix1.b.l += 14; }
- void add_ix1_f() { m_ix1.b.l += 15; }
-
- void add_ix2_0() { }
- void add_ix2_1() { m_ix2.b.l += 1; }
- void add_ix2_2() { m_ix2.b.l += 2; }
- void add_ix2_3() { m_ix2.b.l += 3; }
- void add_ix2_4() { m_ix2.b.l += 4; }
- void add_ix2_5() { m_ix2.b.l += 5; }
- void add_ix2_6() { m_ix2.b.l += 6; }
- void add_ix2_7() { m_ix2.b.l += 7; }
- void add_ix2_8() { m_ix2.b.l += 8; }
- void add_ix2_9() { m_ix2.b.l += 9; }
- void add_ix2_a() { m_ix2.b.l += 10; }
- void add_ix2_b() { m_ix2.b.l += 11; }
- void add_ix2_c() { m_ix2.b.l += 12; }
- void add_ix2_d() { m_ix2.b.l += 13; }
- void add_ix2_e() { m_ix2.b.l += 14; }
- void add_ix2_f() { m_ix2.b.l += 15; }
-
- void ld_base_0() { m_regPtr = 0; }
- void ld_base_1() { m_regPtr = 1; }
- void ld_base_2() { m_regPtr = 2; }
- void ld_base_3() { m_regPtr = 3; }
- void ld_base_4() { m_regPtr = 4; }
- void ld_base_5() { m_regPtr = 5; }
- void ld_base_6() { m_regPtr = 6; }
- void ld_base_7() { m_regPtr = 7; }
-
- void ld_bank_0() { m_mb = 0; }
- void ld_bank_1() { m_mb = 1; }
- void ld_bank_2() { m_mb = 2; }
- void ld_bank_3() { m_mb = 3; }
-
- void ld_ix0_n() { m_ix0.b.l = M_RDMEM_OPCODE(); }
- void ld_ix1_n() { m_ix1.b.l = M_RDMEM_OPCODE(); }
- void ld_ix2_n() { m_ix2.b.l = M_RDMEM_OPCODE(); }
- void ld_lp0_n() { m_lp0 = M_RDMEM_OPCODE(); }
- void ld_lp1_n() { m_lp1 = M_RDMEM_OPCODE(); }
- void ld_lp2_n() { m_lp2 = M_RDMEM_OPCODE(); }
- void ld_b_n() { m_B = M_RDMEM_OPCODE(); }
-
- void djnz_lp0() { u8 i=M_RDMEM_OPCODE(); m_lp0--; if (m_lp0 != 0) M_JMP(i); }
- void djnz_lp1() { u8 i=M_RDMEM_OPCODE(); m_lp1--; if (m_lp1 != 0) M_JMP(i); }
- void djnz_lp2() { u8 i=M_RDMEM_OPCODE(); m_lp2--; if (m_lp2 != 0) M_JMP(i); }
- void jnz() { u8 i=M_RDMEM_OPCODE(); if (!m_zf) M_JMP(i); }
- void jnc() { u8 i=M_RDMEM_OPCODE(); if (!m_cf) M_JMP(i);}
- void jz() { u8 i=M_RDMEM_OPCODE(); if ( m_zf) M_JMP(i); }
- void jc() { u8 i=M_RDMEM_OPCODE(); if ( m_cf) M_JMP(i);}
- void jmp() { M_JMP(M_RDMEM_OPCODE() ); }
-
- void stop();
-
- /* ALPHA 8301 : added instruction */
- void exg_a_ix0() { u8 t=m_A; m_A = m_ix0.b.l; m_ix0.b.l = t; }
- void exg_a_ix1() { u8 t=m_A; m_A = m_ix1.b.l; m_ix1.b.l = t; }
- void exg_a_ix2() { u8 t=m_A; m_A = m_ix2.b.l; m_ix2.b.l = t; }
- void exg_a_lp0() { u8 t=m_A; m_A = m_lp0; m_lp0 = t; }
- void exg_a_lp1() { u8 t=m_A; m_A = m_lp1; m_lp1 = t; }
- void exg_a_lp2() { u8 t=m_A; m_A = m_lp2; m_lp2 = t; }
- void exg_a_b() { u8 t=m_A; m_A = m_B; m_B = t; }
- void exg_a_rb() { u8 t=m_A; m_A = m_regPtr; m_regPtr = t; }
-
- void ld_ix0_a() { m_ix0.b.l = m_A; }
- void ld_ix1_a() { m_ix1.b.l = m_A; }
- void ld_ix2_a() { m_ix2.b.l = m_A; }
- void ld_lp0_a() { m_lp0 = m_A; }
- void ld_lp1_a() { m_lp1 = m_A; }
- void ld_lp2_a() { m_lp2 = m_A; }
- void ld_b_a() { m_B = m_A; }
- void ld_rb_a() { m_regPtr = m_A; }
-
- void exg_ix0_ix1() { u8 t=m_ix1.b.l; m_ix1.b.l = m_ix0.b.l; m_ix0.b.l = t; }
- void exg_ix0_ix2() { u8 t=m_ix2.b.l; m_ix2.b.l = m_ix0.b.l; m_ix0.b.l = t; }
-
- void op_d4() { m_A = M_RDMEM( ((m_RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE() ); }
- void op_d5() { M_WRMEM( ((m_RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE(), m_A ); }
- void op_d6() { m_lp0 = M_RDMEM( ((m_RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE() ); }
- void op_d7() { M_WRMEM( ((m_RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE(), m_lp0 ); }
-
- void ld_a_abs() { m_A = M_RDMEM( ((m_mb & 3) << 8) | M_RDMEM_OPCODE() ); }
- void ld_abs_a() { M_WRMEM( ((m_mb & 3) << 8) | M_RDMEM_OPCODE(), m_A ); }
-
- void ld_a_r() { m_A = m_RAM[(M_RDMEM_OPCODE()>>1)&0x3f]; }
- void ld_r_a() { m_RAM[(M_RDMEM_OPCODE()>>1)&0x3f] = m_A; }
- void op_rep_ld_ix2_b() { do { M_WRMEM(m_ix2.w.l, m_RAM[(m_B>>1)&0x3f]); m_ix2.b.l++; m_B+=2; m_lp0--; } while (m_lp0 != 0); }
- void op_rep_ld_b_ix0() { do { m_RAM[(m_B>>1)&0x3f] = M_RDMEM(m_ix0.w.l); m_ix0.b.l++; m_B+=2; m_lp0--; } while (m_lp0 != 0); }
- void ld_rxb_a() { m_RAM[(m_B>>1)&0x3f] = m_A; }
- void ld_a_rxb() { m_A = m_RAM[(m_B>>1)&0x3f]; }
- void cmp_a_rxb() { u8 i=m_RAM[(m_B>>1)&0x3f]; m_zf = (m_A==i); m_cf = (m_A>=i); }
- void xor_a_rxb() { M_XOR(m_RAM[(m_B>>1)&0x3f] ); }
-
- void add_a_cf() { if (m_cf) inc_a(); }
- void sub_a_cf() { if (m_cf) dec_a(); }
- void tst_a() { m_zf = (m_A==0); }
- void clr_a() { m_A = 0; m_zf = (m_A==0); }
- void cmp_a_n() { u8 i=M_RDMEM_OPCODE(); m_zf = (m_A==i); m_cf = (m_A>=i); }
- void xor_a_n() { M_XOR(M_RDMEM_OPCODE() ); }
- void call() { u8 i=M_RDMEM_OPCODE(); m_retptr.w.l = m_pc.w.l; M_JMP(i); };
- void ld_a_ix0_a() { m_A = M_RDMEM(m_ix0.w.l+m_A); }
- void ret() { m_mb = m_retptr.b.h; M_JMP( m_retptr.b.l ); };
- void save_zc() { m_savez = m_zf; m_savec = m_cf; };
- void rest_zc() { m_zf = m_savez; m_cf = m_savec; };
-
- static const s_opcode opcode_8201[256];
- static const s_opcode opcode_8301[256];
-
- address_space_config m_program_config;
- address_space_config m_io_config;
-
- u8 m_RAM[8*8]; /* internal GP register 8 * 8bank */
- unsigned m_PREVPC;
- PAIR m_retptr; /* for 8301, return address of CALL */
- PAIR m_pc; /* 2bit+8bit program counter */
- u8 m_regPtr; /* RB register base */
- u8 m_mb; /* MB memory bank reg. latch after Branch */
- u8 m_cf; /* C flag */
- u8 m_zf; /* Z flag */
- u8 m_savec; /* for 8301, save flags */
- u8 m_savez; /* for 8301, save flags */
-
- PAIR m_ix0; /* 8bit memory read index reg. */
- PAIR m_ix1; /* 8bitmemory read index reg. */
- PAIR m_ix2; /* 8bitmemory write index reg. */
- u8 m_lp0; /* 8bit loop reg. */
- u8 m_lp1; /* 8bit loop reg. */
- u8 m_lp2; /* 8bit loop reg. */
- u8 m_A; /* 8bit accumulator */
- u8 m_B; /* 8bit register */
-
- u8 m_halt; /* halt input line */
-
- address_space *m_program;
- memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_cache;
- int m_icount;
- int m_inst_cycles;
-
- const s_opcode *const m_opmap;
-
- // Used for import/export only
- u8 m_sp;
- u8 m_R[8];
- u8 m_flags;
-};
-
-
-class alpha8301_cpu_device : public alpha8201_cpu_device
-{
-public:
- // construction/destruction
- alpha8301_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
-};
-
-
-DECLARE_DEVICE_TYPE(ALPHA8201L, alpha8201_cpu_device)
-DECLARE_DEVICE_TYPE(ALPHA8301L, alpha8301_cpu_device)
-
-#endif // MAME_CPU_ALPH8201_ALPH8201_H
diff --git a/src/mame/drivers/equites.cpp b/src/mame/drivers/equites.cpp
index 51bbb7db873..87900c8c9f3 100644
--- a/src/mame/drivers/equites.cpp
+++ b/src/mame/drivers/equites.cpp
@@ -1522,7 +1522,7 @@ ROM_START( kouyakyu )
ROM_LOAD( "epr-6698.bin", 0x0a000, 0x2000, CRC(7adfd1ff) SHA1(b543dd6734a681a187dabf602bea390de663039c) )
ROM_REGION( 0x2000, "alpha_8201:mcu", 0 )
- ROM_LOAD( "alpha-8303_44801b42.bin", 0x0000, 0x2000, BAD_DUMP CRC(66adcb37) SHA1(e1c72ecb161129dcbddc0b16dd90e716d0c79311) ) // 8304 is not dumped yet, using 8303 instead
+ ROM_LOAD( "alpha-8505_44801c57.bin", 0x0000, 0x2000, BAD_DUMP CRC(1f5a1405) SHA1(23f2e23db402f88037a5cbdab2935ec1b9a05298) ) // 8304 is not dumped yet, using 8505 instead
ROM_REGION( 0x1000, "gfx1", 0 ) // chars
ROM_LOAD( "epr-6710.bin", 0x00000, 0x1000, CRC(accda190) SHA1(265d2fd92574d65e7890e48d5f305bf903a67bc8) )
diff --git a/src/tools/unidasm.cpp b/src/tools/unidasm.cpp
index 91082741c8d..d2f49db0f29 100644
--- a/src/tools/unidasm.cpp
+++ b/src/tools/unidasm.cpp
@@ -16,7 +16,6 @@ using util::BIT;
#include "cpu/8x300/8x300dasm.h"
#include "cpu/adsp2100/2100dasm.h"
-#include "cpu/alph8201/8201dasm.h"
#include "cpu/alpha/alphad.h"
#include "cpu/alto2/alto2dsm.h"
#include "cpu/am29000/am29dasm.h"
@@ -332,7 +331,6 @@ static const dasm_table_entry dasm_table[] =
{ "alpha_nt", le, 0, []() -> util::disasm_interface * { return new alpha_disassembler(alpha_disassembler::TYPE_NT); } },
{ "alpha_unix", le, 0, []() -> util::disasm_interface * { return new alpha_disassembler(alpha_disassembler::TYPE_UNIX); } },
{ "alpha_vms", le, 0, []() -> util::disasm_interface * { return new alpha_disassembler(alpha_disassembler::TYPE_VMS); } },
- { "alpha8201", le, 0, []() -> util::disasm_interface * { return new alpha8201_disassembler; } },
{ "alto2", be, -2, []() -> util::disasm_interface * { return new alto2_disassembler; } },
{ "am29000", be, 0, []() -> util::disasm_interface * { return new am29000_disassembler; } },
{ "amis2000", le, 0, []() -> util::disasm_interface * { return new amis2000_disassembler; } },