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author Lord-Nightmare <Lord-Nightmare@users.noreply.github.com>2017-09-03 05:16:11 -0400
committer Lord-Nightmare <Lord-Nightmare@users.noreply.github.com>2017-09-03 05:16:11 -0400
commitce49928623177f336bbde51ab234b3054e6821e5 (patch)
treea8faa3c738d1f2b009959fe9dc288748324a6836
parentc7100413ef3b35ff2ec1d95cfe0d757f564006ff (diff)
upd7725: update ov1 and s1 flag calculation to be correct based on AWJ's nesdev forums post and the original datasheets. [AWJ, Lord Nightmare]
-rw-r--r--src/devices/cpu/upd7725/upd7725.cpp30
-rw-r--r--src/devices/cpu/upd7725/upd7725.h6
2 files changed, 11 insertions, 25 deletions
diff --git a/src/devices/cpu/upd7725/upd7725.cpp b/src/devices/cpu/upd7725/upd7725.cpp
index 697a8b075b7..f010acc8b0f 100644
--- a/src/devices/cpu/upd7725/upd7725.cpp
+++ b/src/devices/cpu/upd7725/upd7725.cpp
@@ -119,16 +119,12 @@ void necdsp_device::device_start()
save_item(NAME(regs.flaga.z));
save_item(NAME(regs.flaga.ov1));
save_item(NAME(regs.flaga.ov0));
- save_item(NAME(regs.flaga.ov0p));
- save_item(NAME(regs.flaga.ov0pp));
save_item(NAME(regs.flagb.s1));
save_item(NAME(regs.flagb.s0));
save_item(NAME(regs.flagb.c));
save_item(NAME(regs.flagb.z));
save_item(NAME(regs.flagb.ov1));
save_item(NAME(regs.flagb.ov0));
- save_item(NAME(regs.flagb.ov0p));
- save_item(NAME(regs.flagb.ov0pp));
save_item(NAME(regs.tr));
save_item(NAME(regs.trb));
save_item(NAME(regs.dr));
@@ -251,9 +247,7 @@ void necdsp_device::state_string_export(const device_state_entry &entry, std::st
regs.flaga.c ? 'C' : 'c',
regs.flaga.z ? 'Z' : 'z',
regs.flaga.ov1 ? "OV1" : "ov1",
- regs.flaga.ov0 ? "OV0" : "ov0",
- regs.flaga.ov0p ? "OV0P" : "ov0p",
- regs.flaga.ov0pp ? "OV0PP" : "ov0pp");
+ regs.flaga.ov0 ? "OV0" : "ov0");
break;
case UPD7725_FLAGB:
@@ -263,9 +257,7 @@ void necdsp_device::state_string_export(const device_state_entry &entry, std::st
regs.flagb.c ? 'C' : 'c',
regs.flagb.z ? 'Z' : 'z',
regs.flagb.ov1 ? "OV1" : "ov1",
- regs.flagb.ov0 ? "OV0" : "ov0",
- regs.flagb.ov0p ? "OV0P" : "ov0p",
- regs.flagb.ov0pp ? "OV0PP" : "ov0pp");
+ regs.flagb.ov0 ? "OV0" : "ov0");
break;
}
}
@@ -442,8 +434,6 @@ void necdsp_device::exec_op(uint32_t opcode) {
flag.s1 = 0;
flag.ov0 = 0;
flag.ov1 = 0;
- flag.ov0p = 0;
- flag.ov0pp = 0;
switch(pselect) {
case 0: p = dataRAM[regs.dp]; break;
@@ -469,7 +459,7 @@ void necdsp_device::exec_op(uint32_t opcode) {
case 9: r = q + 1; p = 1; break; //INC
case 10: r = ~q; break; //CMP
case 11: r = (q >> 1) | (q & 0x8000); break; //SHR1 (ASR)
- case 12: r = (q << 1) | (c ? 1 : 0); break; //SHL1 (ROL)
+ case 12: r = (q << 1) | (c ? 1 : 0); break; //SHL1 (ROL)
case 13: r = (q << 2) | 3; break; //SHL2
case 14: r = (q << 4) | 15; break; //SHL4
case 15: r = (q << 8) | (q >> 8); break; //XCHG
@@ -477,13 +467,12 @@ void necdsp_device::exec_op(uint32_t opcode) {
flag.s0 = (r & 0x8000);
flag.z = (r == 0);
- flag.ov0pp = flag.ov0p;
- flag.ov0p = flag.ov0;
+ if (!flag.ov1) flag.s1 = flag.s0;
switch(alu) {
case 1: case 2: case 3: case 10: case 13: case 14: case 15: {
flag.c = 0;
- flag.ov0 = flag.ov0p = flag.ov0pp = 0; // ASSUMPTION: previous ov0 values are nulled here to make ov1 zero
+ flag.ov0 = flag.ov1 = 0; // OV0 and OV1 are cleared by any non-add/sub/nop operation
break;
}
case 4: case 5: case 6: case 7: case 8: case 9: {
@@ -496,23 +485,20 @@ void necdsp_device::exec_op(uint32_t opcode) {
flag.ov0 = (q ^ r) & (q ^ p) & 0x8000;
flag.c = (r > q);
}
+ flag.ov1 = (flag.ov0 & flag.ov1) ? (flag.s1 == flag.s0) : (flag.ov0 | flag.ov1);
break;
}
case 11: {
flag.c = q & 1;
- flag.ov0 = flag.ov0p = flag.ov0pp = 0; // ASSUMPTION: previous ov0 values are nulled here to make ov1 zero
+ flag.ov0 = flag.ov1 = 0; // OV0 and OV1 are cleared by any non-add/sub/nop operation
break;
}
case 12: {
flag.c = q >> 15;
- flag.ov0 = flag.ov0p = flag.ov0pp = 0; // ASSUMPTION: previous ov0 values are nulled here to make ov1 zero
+ flag.ov0 = flag.ov1 = 0; // OV0 and OV1 are cleared by any non-add/sub/nop operation
break;
}
}
- // flag.ov1 is only set if the number of overflows of the past 3 opcodes (of type 4,5,6,7,8,9) is odd
- flag.ov1 = (flag.ov0 + flag.ov0p + flag.ov0pp) & 1;
- // flag.s1 is based on ov1: s1 = ov1 ^ s0;
- flag.s1 = flag.ov1 ^ flag.s0;
switch(asl) {
case 0: regs.a = r; regs.flaga = flag; break;
diff --git a/src/devices/cpu/upd7725/upd7725.h b/src/devices/cpu/upd7725/upd7725.h
index 3210c4d6c3a..76cc13b9226 100644
--- a/src/devices/cpu/upd7725/upd7725.h
+++ b/src/devices/cpu/upd7725/upd7725.h
@@ -119,16 +119,16 @@ protected:
private:
struct Flag
{
- bool s1, s0, c, z, ov1, ov0, ov0p, ov0pp;
+ bool s1, s0, c, z, ov1, ov0;
inline operator unsigned() const
{
- return (s1 << 7) + (s0 << 6) + (c << 5) + (z << 4) + (ov1 << 3) + (ov0 << 2) + (ov0p << 1) + (ov0pp << 0);
+ return (s1 << 5) + (s0 << 4) + (c << 3) + (z << 2) + (ov1 << 1) + (ov0 << 0);
}
inline unsigned operator=(unsigned d)
{
- s1 = d & 0x80; s0 = d & 0x40; c = d & 0x20; z = d & 0x10; ov1 = d & 0x08; ov0 = d & 0x04; ov0p = d & 0x02; ov0pp = d & 0x01;
+ s1 = d & 0x20; s0 = d & 0x10; c = d & 0x08; z = d & 0x04; ov1 = d & 0x02; ov0 = d & 0x01;
return d;
}
};