diff options
author | AJR <ajrhacker@users.noreply.github.com> | 2019-04-17 15:40:23 -0400 |
---|---|---|
committer | AJR <ajrhacker@users.noreply.github.com> | 2019-04-17 15:41:23 -0400 |
commit | cdd6766fe48154e389ae639c60023a28d28d1849 (patch) | |
tree | 47cbc9f95b08ce5072884e699277c7743a3c0062 | |
parent | 320677695062222adfefc501fb384af86b863033 (diff) |
scc68070: Merge CPU device with on-chip peripheral emulation
- Add internal clock divider
- Add a few crude hacks to force status bits in unemulated UART and I2C
-rw-r--r-- | scripts/src/machine.lua | 11 | ||||
-rw-r--r-- | scripts/target/mame/arcade.lua | 3 | ||||
-rw-r--r-- | scripts/target/mame/mess.lua | 3 | ||||
-rw-r--r-- | src/devices/cpu/m68000/m68000.h | 11 | ||||
-rw-r--r-- | src/devices/cpu/m68000/m68kcpu.cpp | 10 | ||||
-rw-r--r-- | src/devices/machine/scc68070.cpp (renamed from src/mame/machine/cdi070.cpp) | 290 | ||||
-rw-r--r-- | src/devices/machine/scc68070.h (renamed from src/mame/machine/cdi070.h) | 43 | ||||
-rw-r--r-- | src/mame/drivers/cdi.cpp | 68 | ||||
-rw-r--r-- | src/mame/drivers/magicard.cpp | 190 | ||||
-rw-r--r-- | src/mame/includes/cdi.h | 6 | ||||
-rw-r--r-- | src/mame/machine/cdicdic.cpp | 5 | ||||
-rw-r--r-- | src/mame/machine/cdicdic.h | 4 |
12 files changed, 235 insertions, 409 deletions
diff --git a/scripts/src/machine.lua b/scripts/src/machine.lua index 91e24545359..611d33f7bf7 100644 --- a/scripts/src/machine.lua +++ b/scripts/src/machine.lua @@ -2543,6 +2543,17 @@ end --------------------------------------------------- -- +--@src/devices/machine/scc68070.h,MACHINES["SCC68070"] = true +--------------------------------------------------- +if (MACHINES["SCC68070"]~=null) then + files { + MAME_DIR .. "src/devices/machine/scc68070.cpp", + MAME_DIR .. "src/devices/machine/scc68070.h", + } +end + +--------------------------------------------------- +-- --@src/devices/machine/scnxx562.h,MACHINES["DUSCC"] = true --------------------------------------------------- diff --git a/scripts/target/mame/arcade.lua b/scripts/target/mame/arcade.lua index 470e669cd34..88f2884210c 100644 --- a/scripts/target/mame/arcade.lua +++ b/scripts/target/mame/arcade.lua @@ -573,6 +573,7 @@ MACHINES["S3520CF"] = true MACHINES["S3C24XX"] = true --MACHINES["S3C44B0"] = true MACHINES["SATURN"] = true +MACHINES["SCC68070"] = true MACHINES["SCSI"] = true MACHINES["SCUDSP"] = true --MACHINES["SECFLASH"] = true @@ -4586,8 +4587,6 @@ files { MAME_DIR .. "src/mame/includes/cdi.h", MAME_DIR .. "src/mame/video/mcd212.cpp", MAME_DIR .. "src/mame/video/mcd212.h", - MAME_DIR .. "src/mame/machine/cdi070.cpp", - MAME_DIR .. "src/mame/machine/cdi070.h", MAME_DIR .. "src/mame/machine/cdislave.cpp", MAME_DIR .. "src/mame/machine/cdislave.h", MAME_DIR .. "src/mame/machine/cdicdic.cpp", diff --git a/scripts/target/mame/mess.lua b/scripts/target/mame/mess.lua index 7141868971f..9fd4c3a1551 100644 --- a/scripts/target/mame/mess.lua +++ b/scripts/target/mame/mess.lua @@ -582,6 +582,7 @@ MACHINES["S3C24XX"] = true MACHINES["S3C44B0"] = true MACHINES["SAA1043"] = true MACHINES["SATURN"] = true +MACHINES["SCC68070"] = true --MACHINES["SCSI"] = true MACHINES["SCC2698B"] = true MACHINES["SCUDSP"] = true @@ -1385,8 +1386,6 @@ files { MAME_DIR .. "src/mame/video/neogeo_spr.h", MAME_DIR .. "src/mame/drivers/cdi.cpp", MAME_DIR .. "src/mame/includes/cdi.h", - MAME_DIR .. "src/mame/machine/cdi070.cpp", - MAME_DIR .. "src/mame/machine/cdi070.h", MAME_DIR .. "src/mame/machine/cdicdic.cpp", MAME_DIR .. "src/mame/machine/cdicdic.h", MAME_DIR .. "src/mame/machine/cdislave.cpp", diff --git a/src/devices/cpu/m68000/m68000.h b/src/devices/cpu/m68000/m68000.h index ddb9644a07b..b9a2ac4d266 100644 --- a/src/devices/cpu/m68000/m68000.h +++ b/src/devices/cpu/m68000/m68000.h @@ -577,12 +577,9 @@ public: virtual void device_start() override; }; -class scc68070_device : public m68000_base_device +class scc68070_base_device : public m68000_base_device { -public: - // construction/destruction - scc68070_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); - +protected: virtual std::unique_ptr<util::disasm_interface> create_disassembler() override; virtual uint32_t execute_min_cycles() const override { return 4; }; @@ -590,6 +587,9 @@ public: // device-level overrides virtual void device_start() override; + + scc68070_base_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, + const device_type type, address_map_constructor internal_map); }; @@ -647,7 +647,6 @@ DECLARE_DEVICE_TYPE(M68030, m68030_device) DECLARE_DEVICE_TYPE(M68EC040, m68ec040_device) DECLARE_DEVICE_TYPE(M68LC040, m68lc040_device) DECLARE_DEVICE_TYPE(M68040, m68040_device) -DECLARE_DEVICE_TYPE(SCC68070, scc68070_device) DECLARE_DEVICE_TYPE(FSCPU32, fscpu32_device) DECLARE_DEVICE_TYPE(MCF5206E, mcf5206e_device) diff --git a/src/devices/cpu/m68000/m68kcpu.cpp b/src/devices/cpu/m68000/m68kcpu.cpp index 5e10749478d..c2ac1556192 100644 --- a/src/devices/cpu/m68000/m68kcpu.cpp +++ b/src/devices/cpu/m68000/m68kcpu.cpp @@ -2087,7 +2087,7 @@ std::unique_ptr<util::disasm_interface> m68040_device::create_disassembler() return std::make_unique<m68k_disassembler>(m68k_disassembler::TYPE_68040); } -std::unique_ptr<util::disasm_interface> scc68070_device::create_disassembler() +std::unique_ptr<util::disasm_interface> scc68070_base_device::create_disassembler() { return std::make_unique<m68k_disassembler>(m68k_disassembler::TYPE_68000); } @@ -2417,7 +2417,6 @@ DEFINE_DEVICE_TYPE(M68030, m68030_device, "m68030", "Motorola MC DEFINE_DEVICE_TYPE(M68EC040, m68ec040_device, "m68ec040", "Motorola MC68EC040") DEFINE_DEVICE_TYPE(M68LC040, m68lc040_device, "m68lc040", "Motorola MC68LC040") DEFINE_DEVICE_TYPE(M68040, m68040_device, "m68040", "Motorola MC68040") -DEFINE_DEVICE_TYPE(SCC68070, scc68070_device, "scc68070", "Philips SCC68070") DEFINE_DEVICE_TYPE(FSCPU32, fscpu32_device, "fscpu32", "Freescale CPU32 Core") DEFINE_DEVICE_TYPE(MCF5206E, mcf5206e_device, "mcf5206e", "Freescale MCF5206E") @@ -2608,12 +2607,13 @@ void m68lc040_device::device_start() } -scc68070_device::scc68070_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : m68000_base_device(mconfig, tag, owner, clock, SCC68070, 16,32) +scc68070_base_device::scc68070_base_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, + const device_type type, address_map_constructor internal_map) + : m68000_base_device(mconfig, tag, owner, clock, type, 16,32, internal_map) { } -void scc68070_device::device_start() +void scc68070_base_device::device_start() { init_cpu_scc68070(); } diff --git a/src/mame/machine/cdi070.cpp b/src/devices/machine/scc68070.cpp index fa47abfa71d..35ec484f1f5 100644 --- a/src/mame/machine/cdi070.cpp +++ b/src/devices/machine/scc68070.cpp @@ -3,7 +3,7 @@ /****************************************************************************** - CD-i-specific cdi68070 SoC peripheral emulation + SCC68070 SoC peripheral emulation ------------------- written by Ryan Holtz @@ -22,9 +22,7 @@ TODO: *******************************************************************************/ #include "emu.h" -#include "machine/cdi070.h" - -#include "cpu/m68000/m68000.h" +#include "machine/scc68070.h" /*----------- debug defines -----------*/ @@ -35,7 +33,7 @@ TODO: #define ENABLE_UART_PRINTING (0) // device type definition -DEFINE_DEVICE_TYPE(CDI_68070, cdi68070_device, "cdi68070", "CDI68070") +DEFINE_DEVICE_TYPE(SCC68070, scc68070_device, "scc68070", "Philips SCC68070") #if ENABLE_VERBOSE_LOG static inline void ATTR_PRINTF(3,4) verboselog(device_t& device, int n_level, const char *s_fmt, ...) @@ -58,13 +56,22 @@ static inline void ATTR_PRINTF(3,4) verboselog(device_t& device, int n_level, co // LIVE DEVICE //************************************************************************** +void scc68070_device::internal_map(address_map &map) +{ + map(0x80000000, 0x8000807f).rw(FUNC(scc68070_device::periphs_r), FUNC(scc68070_device::periphs_w)); +} + +void scc68070_device::cpu_space_map(address_map &map) +{ + map(0xfffffff0, 0xffffffff).r(FUNC(scc68070_device::iack_r)).umask16(0x00ff); +} + //------------------------------------------------- -// cdi68070_device - constructor +// scc68070_device - constructor //------------------------------------------------- -cdi68070_device::cdi68070_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : device_t(mconfig, CDI_68070, tag, owner, clock) - , m_maincpu(*this, finder_base::DUMMY_TAG) +scc68070_device::scc68070_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : scc68070_base_device(mconfig, tag, owner, clock, SCC68070, address_map_constructor(FUNC(scc68070_device::internal_map), this)) , m_iack2_callback(*this) , m_iack4_callback(*this) , m_iack5_callback(*this) @@ -77,6 +84,7 @@ cdi68070_device::cdi68070_device(const machine_config &mconfig, const char *tag, , m_int1_line(CLEAR_LINE) , m_int2_line(CLEAR_LINE) { + m_cpu_space_config.m_internal_map = address_map_constructor(FUNC(scc68070_device::cpu_space_map), this); } //------------------------------------------------- @@ -85,20 +93,24 @@ cdi68070_device::cdi68070_device(const machine_config &mconfig, const char *tag, // initial conditions at start time //------------------------------------------------- -void cdi68070_device::device_resolve_objects() +void scc68070_device::device_resolve_objects() { - m_iack2_callback.resolve_safe(scc68070_device::autovector(2)); - m_iack4_callback.resolve_safe(scc68070_device::autovector(4)); - m_iack5_callback.resolve_safe(scc68070_device::autovector(5)); - m_iack7_callback.resolve_safe(scc68070_device::autovector(7)); + scc68070_base_device::device_resolve_objects(); + + m_iack2_callback.resolve_safe(autovector(2)); + m_iack4_callback.resolve_safe(autovector(4)); + m_iack5_callback.resolve_safe(autovector(5)); + m_iack7_callback.resolve_safe(autovector(7)); } //------------------------------------------------- // device_start - device-specific startup //------------------------------------------------- -void cdi68070_device::device_start() +void scc68070_device::device_start() { + scc68070_base_device::device_start(); + save_item(NAME(m_ipl)); save_item(NAME(m_in2_line)); @@ -191,13 +203,13 @@ void cdi68070_device::device_start() save_item(NAME(m_mmu.desc[7].segment)); save_item(NAME(m_mmu.desc[7].base)); - m_timers.timer0_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(cdi68070_device::timer0_callback), this)); + m_timers.timer0_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(scc68070_device::timer0_callback), this)); m_timers.timer0_timer->adjust(attotime::never); - m_uart.rx_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(cdi68070_device::rx_callback), this)); + m_uart.rx_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(scc68070_device::rx_callback), this)); m_uart.rx_timer->adjust(attotime::never); - m_uart.tx_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(cdi68070_device::tx_callback), this)); + m_uart.tx_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(scc68070_device::tx_callback), this)); m_uart.tx_timer->adjust(attotime::never); } @@ -205,8 +217,10 @@ void cdi68070_device::device_start() // device_reset - device-specific reset //------------------------------------------------- -void cdi68070_device::device_reset() +void scc68070_device::device_reset() { + scc68070_base_device::device_reset(); + m_lir = 0; m_picr1 = 0; @@ -269,7 +283,7 @@ void cdi68070_device::device_reset() update_ipl(); } -void cdi68070_device::update_ipl() +void scc68070_device::update_ipl() { const uint8_t external_level = (m_nmi_line == ASSERT_LINE) ? 7 : (m_in5_line == ASSERT_LINE) ? 5 @@ -289,38 +303,38 @@ void cdi68070_device::update_ipl() if (m_ipl != new_ipl) { if (m_ipl != 0) - m_maincpu->set_input_line(m_ipl, CLEAR_LINE); + set_input_line(m_ipl, CLEAR_LINE); if (new_ipl != 0) - m_maincpu->set_input_line(new_ipl, ASSERT_LINE); + set_input_line(new_ipl, ASSERT_LINE); m_ipl = new_ipl; } } -WRITE_LINE_MEMBER(cdi68070_device::in2_w) +WRITE_LINE_MEMBER(scc68070_device::in2_w) { m_in2_line = state; update_ipl(); } -WRITE_LINE_MEMBER(cdi68070_device::in4_w) +WRITE_LINE_MEMBER(scc68070_device::in4_w) { m_in4_line = state; update_ipl(); } -WRITE_LINE_MEMBER(cdi68070_device::in5_w) +WRITE_LINE_MEMBER(scc68070_device::in5_w) { m_in5_line = state; update_ipl(); } -WRITE_LINE_MEMBER(cdi68070_device::nmi_w) +WRITE_LINE_MEMBER(scc68070_device::nmi_w) { m_nmi_line = state; update_ipl(); } -WRITE_LINE_MEMBER(cdi68070_device::int1_w) +WRITE_LINE_MEMBER(scc68070_device::int1_w) { if (m_int1_line != state) { @@ -334,7 +348,7 @@ WRITE_LINE_MEMBER(cdi68070_device::int1_w) } } -WRITE_LINE_MEMBER(cdi68070_device::int2_w) +WRITE_LINE_MEMBER(scc68070_device::int2_w) { if (m_int2_line != state) { @@ -348,7 +362,7 @@ WRITE_LINE_MEMBER(cdi68070_device::int2_w) } } -uint8_t cdi68070_device::iack_r(offs_t offset) +uint8_t scc68070_device::iack_r(offs_t offset) { switch (offset) { @@ -410,7 +424,7 @@ uint8_t cdi68070_device::iack_r(offs_t offset) return 0x38 + offset; } -void cdi68070_device::set_timer_callback(int channel) +void scc68070_device::set_timer_callback(int channel) { switch (channel) { @@ -418,7 +432,7 @@ void cdi68070_device::set_timer_callback(int channel) { // Timer clock period is 96/CLKOUT uint32_t compare = 0x10000 - m_timers.timer0; - attotime period = m_maincpu->cycles_to_attotime(96 * compare); + attotime period = cycles_to_attotime(96 * compare); m_timers.timer0_timer->adjust(period); break; } @@ -429,17 +443,17 @@ void cdi68070_device::set_timer_callback(int channel) } } -void cdi68070_device::set_quizard_mcu_ack(uint8_t ack) +void scc68070_device::set_quizard_mcu_ack(uint8_t ack) { m_mcu_ack = ack; } -void cdi68070_device::set_quizard_mcu_value(uint16_t value) +void scc68070_device::set_quizard_mcu_value(uint16_t value) { m_mcu_value = value; } -TIMER_CALLBACK_MEMBER( cdi68070_device::timer0_callback ) +TIMER_CALLBACK_MEMBER( scc68070_device::timer0_callback ) { m_timers.timer0 = m_timers.reload_register; m_timers.timer_status_register |= TSR_OV0; @@ -452,7 +466,7 @@ TIMER_CALLBACK_MEMBER( cdi68070_device::timer0_callback ) set_timer_callback(0); } -void cdi68070_device::uart_rx_check() +void scc68070_device::uart_rx_check() { if ((m_uart.command_register & 3) == 1) { @@ -466,7 +480,7 @@ void cdi68070_device::uart_rx_check() } } -void cdi68070_device::uart_tx_check() +void scc68070_device::uart_tx_check() { if (((m_uart.command_register >> 2) & 3) == 1) { @@ -491,21 +505,21 @@ void cdi68070_device::uart_tx_check() } } -void cdi68070_device::uart_rx(uint8_t data) +void scc68070_device::uart_rx(uint8_t data) { m_uart.receive_pointer++; m_uart.receive_buffer[m_uart.receive_pointer] = data; uart_rx_check(); } -void cdi68070_device::uart_tx(uint8_t data) +void scc68070_device::uart_tx(uint8_t data) { m_uart.transmit_pointer++; m_uart.transmit_buffer[m_uart.transmit_pointer] = data; uart_tx_check(); } -TIMER_CALLBACK_MEMBER( cdi68070_device::rx_callback ) +TIMER_CALLBACK_MEMBER( scc68070_device::rx_callback ) { if ((m_uart.command_register & 3) == 1) { @@ -544,13 +558,13 @@ TIMER_CALLBACK_MEMBER( cdi68070_device::rx_callback ) uart_rx_check(); } -void cdi68070_device::quizard_rx(uint8_t data) +void scc68070_device::quizard_rx(uint8_t data) { uart_rx(0x5a); uart_rx(data); } -void cdi68070_device::quizard_set_seeds(uint8_t *rx) +void scc68070_device::quizard_set_seeds(uint8_t *rx) { m_seeds[0] = (rx[1] << 8) | rx[0]; m_seeds[1] = (rx[3] << 8) | rx[2]; @@ -564,7 +578,7 @@ void cdi68070_device::quizard_set_seeds(uint8_t *rx) m_seeds[9] = (rx[19] << 8) | rx[18]; } -void cdi68070_device::quizard_calculate_state() +void scc68070_device::quizard_calculate_state() { //const uint16_t desired_bitfield = mcu_value; const uint16_t field0 = 0x00ff; @@ -602,7 +616,7 @@ void cdi68070_device::quizard_calculate_state() m_state[5] = lo1 - m_state[4]; } -void cdi68070_device::mcu_frame() +void scc68070_device::mcu_frame() { if (0)//mcu_active) { @@ -615,7 +629,7 @@ void cdi68070_device::mcu_frame() } } -void cdi68070_device::quizard_handle_byte_tx() +void scc68070_device::quizard_handle_byte_tx() { static int state = 0; static uint8_t rx[0x100]; @@ -711,7 +725,7 @@ void cdi68070_device::quizard_handle_byte_tx() } } -TIMER_CALLBACK_MEMBER( cdi68070_device::tx_callback ) +TIMER_CALLBACK_MEMBER( scc68070_device::tx_callback ) { if (((m_uart.command_register >> 2) & 3) == 1) { @@ -723,7 +737,7 @@ TIMER_CALLBACK_MEMBER( cdi68070_device::tx_callback ) m_uart.transmit_holding_register = m_uart.transmit_buffer[0]; quizard_handle_byte_tx(); - verboselog(*this, 2, "cdi68070_tx_callback: Transmitting %02x\n", m_uart.transmit_holding_register); + verboselog(*this, 2, "tx_callback: Transmitting %02x\n", m_uart.transmit_holding_register); for(int index = 0; index < m_uart.transmit_pointer; index++) { m_uart.transmit_buffer[index] = m_uart.transmit_buffer[index+1]; @@ -746,7 +760,7 @@ TIMER_CALLBACK_MEMBER( cdi68070_device::tx_callback ) uart_tx_check(); } -READ16_MEMBER( cdi68070_device::periphs_r ) +READ16_MEMBER( scc68070_device::periphs_r ) { switch (offset) { @@ -758,31 +772,31 @@ READ16_MEMBER( cdi68070_device::periphs_r ) case 0x2000/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: I2C Data Register: %04x & %04x\n", m_i2c.data_register, mem_mask); + verboselog(*this, 2, "periphs_w: I2C Data Register: %04x & %04x\n", m_i2c.data_register, mem_mask); } return m_i2c.data_register; case 0x2002/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: I2C Address Register: %04x & %04x\n", m_i2c.address_register, mem_mask); + verboselog(*this, 2, "periphs_w: I2C Address Register: %04x & %04x\n", m_i2c.address_register, mem_mask); } return m_i2c.address_register; case 0x2004/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: I2C Status Register: %04x & %04x\n", m_i2c.status_register, mem_mask); + verboselog(*this, 2, "periphs_w: I2C Status Register: %04x & %04x\n", m_i2c.status_register, mem_mask); } - return m_i2c.status_register; + return m_i2c.status_register & 0xef; // hack for magicard case 0x2006/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: I2C Control Register: %04x & %04x\n", m_i2c.control_register, mem_mask); + verboselog(*this, 2, "periphs_w: I2C Control Register: %04x & %04x\n", m_i2c.control_register, mem_mask); } return m_i2c.control_register; case 0x2008/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: I2C Clock Control Register: %04x & %04x\n", m_i2c.clock_control_register, mem_mask); + verboselog(*this, 2, "periphs_w: I2C Clock Control Register: %04x & %04x\n", m_i2c.clock_control_register, mem_mask); } return m_i2c.clock_control_register; @@ -790,64 +804,64 @@ READ16_MEMBER( cdi68070_device::periphs_r ) case 0x2010/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: UART Mode Register: %04x & %04x\n", m_uart.mode_register, mem_mask); + verboselog(*this, 2, "periphs_r: UART Mode Register: %04x & %04x\n", m_uart.mode_register, mem_mask); } else { - verboselog(*this, 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); + verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); } return m_uart.mode_register | 0x20; case 0x2012/2: m_uart.status_register |= (1 << 1); if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: UART Status Register: %04x & %04x\n", m_uart.status_register, mem_mask); + verboselog(*this, 2, "periphs_r: UART Status Register: %04x & %04x\n", m_uart.status_register, mem_mask); } else { - verboselog(*this, 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); + verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); } - return m_uart.status_register; + return m_uart.status_register | 0x08; // hack for magicard case 0x2014/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: UART Clock Select: %04x & %04x\n", m_uart.clock_select, mem_mask); + verboselog(*this, 2, "periphs_r: UART Clock Select: %04x & %04x\n", m_uart.clock_select, mem_mask); } else { - verboselog(*this, 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); + verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); } return m_uart.clock_select | 0x08; case 0x2016/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: UART Command Register: %02x & %04x\n", m_uart.command_register, mem_mask); + verboselog(*this, 2, "periphs_r: UART Command Register: %02x & %04x\n", m_uart.command_register, mem_mask); } else { - verboselog(*this, 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); + verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); } return m_uart.command_register | 0x80; case 0x2018/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: UART Transmit Holding Register: %02x & %04x\n", m_uart.transmit_holding_register, mem_mask); + verboselog(*this, 2, "periphs_r: UART Transmit Holding Register: %02x & %04x\n", m_uart.transmit_holding_register, mem_mask); } else { - verboselog(*this, 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); + verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); } return m_uart.transmit_holding_register; case 0x201a/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: UART Receive Holding Register: %02x & %04x\n", m_uart.receive_holding_register, mem_mask); + verboselog(*this, 2, "periphs_r: UART Receive Holding Register: %02x & %04x\n", m_uart.receive_holding_register, mem_mask); } else { - verboselog(*this, 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); + verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); } if (m_uart_rx_int) { @@ -871,31 +885,31 @@ READ16_MEMBER( cdi68070_device::periphs_r ) case 0x2020/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: Timer Control Register: %02x & %04x\n", m_timers.timer_control_register, mem_mask); + verboselog(*this, 2, "periphs_r: Timer Control Register: %02x & %04x\n", m_timers.timer_control_register, mem_mask); } if (ACCESSING_BITS_8_15) { - verboselog(*this, 12, "cdi68070_periphs_r: Timer Status Register: %02x & %04x\n", m_timers.timer_status_register, mem_mask); + verboselog(*this, 12, "periphs_r: Timer Status Register: %02x & %04x\n", m_timers.timer_status_register, mem_mask); } return (m_timers.timer_status_register << 8) | m_timers.timer_control_register; case 0x2022/2: - verboselog(*this, 2, "cdi68070_periphs_r: Timer Reload Register: %04x & %04x\n", m_timers.reload_register, mem_mask); + verboselog(*this, 2, "periphs_r: Timer Reload Register: %04x & %04x\n", m_timers.reload_register, mem_mask); return m_timers.reload_register; case 0x2024/2: - verboselog(*this, 2, "cdi68070_periphs_r: Timer 0: %04x & %04x\n", m_timers.timer0, mem_mask); + verboselog(*this, 2, "periphs_r: Timer 0: %04x & %04x\n", m_timers.timer0, mem_mask); return m_timers.timer0; case 0x2026/2: - verboselog(*this, 2, "cdi68070_periphs_r: Timer 1: %04x & %04x\n", m_timers.timer1, mem_mask); + verboselog(*this, 2, "periphs_r: Timer 1: %04x & %04x\n", m_timers.timer1, mem_mask); return m_timers.timer1; case 0x2028/2: - verboselog(*this, 2, "cdi68070_periphs_r: Timer 2: %04x & %04x\n", m_timers.timer2, mem_mask); + verboselog(*this, 2, "periphs_r: Timer 2: %04x & %04x\n", m_timers.timer2, mem_mask); return m_timers.timer2; // PICR1: 80002045 case 0x2044/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: Peripheral Interrupt Control Register 1: %02x & %04x\n", m_picr1, mem_mask); + verboselog(*this, 2, "periphs_r: Peripheral Interrupt Control Register 1: %02x & %04x\n", m_picr1, mem_mask); } return m_picr1 & 0x77; @@ -903,7 +917,7 @@ READ16_MEMBER( cdi68070_device::periphs_r ) case 0x2046/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: Peripheral Interrupt Control Register 2: %02x & %04x\n", m_picr2, mem_mask); + verboselog(*this, 2, "periphs_r: Peripheral Interrupt Control Register 2: %02x & %04x\n", m_picr2, mem_mask); } return m_picr2 & 0x77; @@ -912,65 +926,65 @@ READ16_MEMBER( cdi68070_device::periphs_r ) case 0x4040/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Error Register: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_error, mem_mask); + verboselog(*this, 2, "periphs_r: DMA(%d) Error Register: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_error, mem_mask); } if (ACCESSING_BITS_8_15) { - verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Status Register: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_status, mem_mask); + verboselog(*this, 2, "periphs_r: DMA(%d) Status Register: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_status, mem_mask); } return (m_dma.channel[(offset - 0x2000) / 32].channel_status << 8) | m_dma.channel[(offset - 0x2000) / 32].channel_error; case 0x4004/2: case 0x4044/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Operation Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].operation_control, mem_mask); + verboselog(*this, 2, "periphs_r: DMA(%d) Operation Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].operation_control, mem_mask); } if (ACCESSING_BITS_8_15) { - verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Device Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].device_control, mem_mask); + verboselog(*this, 2, "periphs_r: DMA(%d) Device Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].device_control, mem_mask); } return (m_dma.channel[(offset - 0x2000) / 32].device_control << 8) | m_dma.channel[(offset - 0x2000) / 32].operation_control; case 0x4006/2: case 0x4046/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Channel Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_control, mem_mask); + verboselog(*this, 2, "periphs_r: DMA(%d) Channel Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].channel_control, mem_mask); } if (ACCESSING_BITS_8_15) { - verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Sequence Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].sequence_control, mem_mask); + verboselog(*this, 2, "periphs_r: DMA(%d) Sequence Control Register: %02x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].sequence_control, mem_mask); } return (m_dma.channel[(offset - 0x2000) / 32].sequence_control << 8) | m_dma.channel[(offset - 0x2000) / 32].channel_control; case 0x400a/2: - verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Memory Transfer Counter: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].transfer_counter, mem_mask); + verboselog(*this, 2, "periphs_r: DMA(%d) Memory Transfer Counter: %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].transfer_counter, mem_mask); return m_dma.channel[(offset - 0x2000) / 32].transfer_counter; case 0x400c/2: case 0x404c/2: - verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Memory Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, (m_dma.channel[(offset - 0x2000) / 32].memory_address_counter >> 16), mem_mask); + verboselog(*this, 2, "periphs_r: DMA(%d) Memory Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, (m_dma.channel[(offset - 0x2000) / 32].memory_address_counter >> 16), mem_mask); return (m_dma.channel[(offset - 0x2000) / 32].memory_address_counter >> 16); case 0x400e/2: case 0x404e/2: - verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Memory Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].memory_address_counter, mem_mask); + verboselog(*this, 2, "periphs_r: DMA(%d) Memory Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].memory_address_counter, mem_mask); return m_dma.channel[(offset - 0x2000) / 32].memory_address_counter; case 0x4014/2: case 0x4054/2: - verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Device Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, (m_dma.channel[(offset - 0x2000) / 32].device_address_counter >> 16), mem_mask); + verboselog(*this, 2, "periphs_r: DMA(%d) Device Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, (m_dma.channel[(offset - 0x2000) / 32].device_address_counter >> 16), mem_mask); return (m_dma.channel[(offset - 0x2000) / 32].device_address_counter >> 16); case 0x4016/2: case 0x4056/2: - verboselog(*this, 2, "cdi68070_periphs_r: DMA(%d) Device Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].device_address_counter, mem_mask); + verboselog(*this, 2, "periphs_r: DMA(%d) Device Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, m_dma.channel[(offset - 0x2000) / 32].device_address_counter, mem_mask); return m_dma.channel[(offset - 0x2000) / 32].device_address_counter; // MMU: 80008000 to 8000807f case 0x8000/2: // Status / Control register if (ACCESSING_BITS_0_7) { // Control - verboselog(*this, 2, "cdi68070_periphs_r: MMU Control: %02x & %04x\n", m_mmu.control, mem_mask); + verboselog(*this, 2, "periphs_r: MMU Control: %02x & %04x\n", m_mmu.control, mem_mask); return m_mmu.control; } // Status else { - verboselog(*this, 2, "cdi68070_periphs_r: MMU Status: %02x & %04x\n", m_mmu.status, mem_mask); + verboselog(*this, 2, "periphs_r: MMU Status: %02x & %04x\n", m_mmu.status, mem_mask); return m_mmu.status; } case 0x8040/2: @@ -981,7 +995,7 @@ READ16_MEMBER( cdi68070_device::periphs_r ) case 0x8068/2: case 0x8070/2: case 0x8078/2: // Attributes (SD0-7) - verboselog(*this, 2, "cdi68070_periphs_r: MMU descriptor %d attributes: %04x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].attr, mem_mask); + verboselog(*this, 2, "periphs_r: MMU descriptor %d attributes: %04x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].attr, mem_mask); return m_mmu.desc[(offset - 0x4020) / 4].attr; case 0x8042/2: case 0x804a/2: @@ -991,7 +1005,7 @@ READ16_MEMBER( cdi68070_device::periphs_r ) case 0x806a/2: case 0x8072/2: case 0x807a/2: // Segment Length (SD0-7) - verboselog(*this, 2, "cdi68070_periphs_r: MMU descriptor %d length: %04x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].length, mem_mask); + verboselog(*this, 2, "periphs_r: MMU descriptor %d length: %04x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].length, mem_mask); return m_mmu.desc[(offset - 0x4020) / 4].length; case 0x8044/2: case 0x804c/2: @@ -1003,7 +1017,7 @@ READ16_MEMBER( cdi68070_device::periphs_r ) case 0x807c/2: // Segment Number (SD0-7, A0=1 only) if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_r: MMU descriptor %d segment: %02x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].segment, mem_mask); + verboselog(*this, 2, "periphs_r: MMU descriptor %d segment: %02x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].segment, mem_mask); return m_mmu.desc[(offset - 0x4020) / 4].segment; } break; @@ -1015,23 +1029,23 @@ READ16_MEMBER( cdi68070_device::periphs_r ) case 0x806e/2: case 0x8076/2: case 0x807e/2: // Base Address (SD0-7) - verboselog(*this, 2, "cdi68070_periphs_r: MMU descriptor %d base: %04x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].base, mem_mask); + verboselog(*this, 2, "periphs_r: MMU descriptor %d base: %04x & %04x\n", (offset - 0x4020) / 4, m_mmu.desc[(offset - 0x4020) / 4].base, mem_mask); return m_mmu.desc[(offset - 0x4020) / 4].base; default: - verboselog(*this, 0, "cdi68070_periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); + verboselog(*this, 0, "periphs_r: Unknown address: %04x & %04x\n", offset * 2, mem_mask); break; } return 0; } -WRITE16_MEMBER( cdi68070_device::periphs_w ) +WRITE16_MEMBER( scc68070_device::periphs_w ) { switch (offset) { // Interrupts: 80001001 case 0x1000/2: // LIR priority level - verboselog(*this, 2, "cdi68070_periphs_w: LIR: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: LIR: %04x & %04x\n", data, mem_mask); COMBINE_DATA(&m_lir); break; @@ -1039,35 +1053,35 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x2000/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: I2C Data Register: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: I2C Data Register: %04x & %04x\n", data, mem_mask); m_i2c.data_register = data & 0x00ff; } break; case 0x2002/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: I2C Address Register: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: I2C Address Register: %04x & %04x\n", data, mem_mask); m_i2c.address_register = data & 0x00ff; } break; case 0x2004/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: I2C Status Register: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: I2C Status Register: %04x & %04x\n", data, mem_mask); m_i2c.status_register = data & 0x00ff; } break; case 0x2006/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: I2C Control Register: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: I2C Control Register: %04x & %04x\n", data, mem_mask); m_i2c.control_register = data & 0x00ff; } break; case 0x2008/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: I2C Clock Control Register: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: I2C Clock Control Register: %04x & %04x\n", data, mem_mask); m_i2c.clock_control_register = data & 0x00ff; } break; @@ -1076,70 +1090,70 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x2010/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: UART Mode Register: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: UART Mode Register: %04x & %04x\n", data, mem_mask); m_uart.mode_register = data & 0x00ff; } else { - verboselog(*this, 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); + verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); } break; case 0x2012/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: UART Status Register: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: UART Status Register: %04x & %04x\n", data, mem_mask); m_uart.status_register = data & 0x00ff; } else { - verboselog(*this, 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); + verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); } break; case 0x2014/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: UART Clock Select: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: UART Clock Select: %04x & %04x\n", data, mem_mask); m_uart.clock_select = data & 0x00ff; } else { - verboselog(*this, 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); + verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); } break; case 0x2016/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: UART Command Register: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: UART Command Register: %04x & %04x\n", data, mem_mask); m_uart.command_register = data & 0x00ff; uart_rx_check(); uart_tx_check(); } else { - verboselog(*this, 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); + verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); } break; case 0x2018/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: UART Transmit Holding Register: %04x & %04x: %c\n", data, mem_mask, (data >= 0x20 && data < 0x7f) ? (data & 0x00ff) : ' '); + verboselog(*this, 2, "periphs_w: UART Transmit Holding Register: %04x & %04x: %c\n", data, mem_mask, (data >= 0x20 && data < 0x7f) ? (data & 0x00ff) : ' '); uart_tx(data & 0x00ff); m_uart.transmit_holding_register = data & 0x00ff; } else { - verboselog(*this, 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); + verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); } break; case 0x201a/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: UART Receive Holding Register: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: UART Receive Holding Register: %04x & %04x\n", data, mem_mask); m_uart.receive_holding_register = data & 0x00ff; } else { - verboselog(*this, 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); + verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); } break; @@ -1147,30 +1161,30 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x2020/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: Timer Control Register: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: Timer Control Register: %04x & %04x\n", data, mem_mask); m_timers.timer_control_register = data & 0x00ff; } if (ACCESSING_BITS_8_15) { - verboselog(*this, 12, "cdi68070_periphs_w: Timer Status Register: %04x & %04x\n", data, mem_mask); + verboselog(*this, 12, "periphs_w: Timer Status Register: %04x & %04x\n", data, mem_mask); m_timers.timer_status_register &= ~(data >> 8); } break; case 0x2022/2: - verboselog(*this, 2, "cdi68070_periphs_w: Timer Reload Register: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: Timer Reload Register: %04x & %04x\n", data, mem_mask); COMBINE_DATA(&m_timers.reload_register); break; case 0x2024/2: - verboselog(*this, 2, "cdi68070_periphs_w: Timer 0: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: Timer 0: %04x & %04x\n", data, mem_mask); COMBINE_DATA(&m_timers.timer0); set_timer_callback(0); break; case 0x2026/2: - verboselog(*this, 2, "cdi68070_periphs_w: Timer 1: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: Timer 1: %04x & %04x\n", data, mem_mask); COMBINE_DATA(&m_timers.timer1); break; case 0x2028/2: - verboselog(*this, 2, "cdi68070_periphs_w: Timer 2: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: Timer 2: %04x & %04x\n", data, mem_mask); COMBINE_DATA(&m_timers.timer2); break; @@ -1178,7 +1192,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x2044/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: Peripheral Interrupt Control Register 1: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: Peripheral Interrupt Control Register 1: %04x & %04x\n", data, mem_mask); m_picr1 = data & 0x0077; switch (data & 0x0088) { @@ -1214,7 +1228,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x2046/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: Peripheral Interrupt Control Register 2: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: Peripheral Interrupt Control Register 2: %04x & %04x\n", data, mem_mask); m_picr2 = data & 0x0077; switch (data & 0x0088) { @@ -1251,11 +1265,11 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x4040/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Error (invalid): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); + verboselog(*this, 2, "periphs_w: DMA(%d) Error (invalid): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); } if (ACCESSING_BITS_8_15) { - verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Status: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); + verboselog(*this, 2, "periphs_w: DMA(%d) Status: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); m_dma.channel[(offset - 0x2000) / 32].channel_status &= ~((data >> 8) & 0xb0); update_ipl(); } @@ -1264,12 +1278,12 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x4044/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Operation Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); + verboselog(*this, 2, "periphs_w: DMA(%d) Operation Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); m_dma.channel[(offset - 0x2000) / 32].operation_control = data & 0x00ff; } if (ACCESSING_BITS_8_15) { - verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Device Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); + verboselog(*this, 2, "periphs_w: DMA(%d) Device Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); m_dma.channel[(offset - 0x2000) / 32].device_control = data >> 8; } break; @@ -1277,7 +1291,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x4046/2: if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Channel Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); + verboselog(*this, 2, "periphs_w: DMA(%d) Channel Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); m_dma.channel[(offset - 0x2000) / 32].channel_control = data & 0x007f; if (data & CCR_SO) { @@ -1287,35 +1301,35 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) } if (ACCESSING_BITS_8_15) { - verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Sequence Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); + verboselog(*this, 2, "periphs_w: DMA(%d) Sequence Control Register: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); m_dma.channel[(offset - 0x2000) / 32].sequence_control = data >> 8; } break; case 0x400a/2: - verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Memory Transfer Counter: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); + verboselog(*this, 2, "periphs_w: DMA(%d) Memory Transfer Counter: %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); COMBINE_DATA(&m_dma.channel[(offset - 0x2000) / 32].transfer_counter); break; case 0x400c/2: case 0x404c/2: - verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Memory Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); + verboselog(*this, 2, "periphs_w: DMA(%d) Memory Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); m_dma.channel[(offset - 0x2000) / 32].memory_address_counter &= ~(mem_mask << 16); m_dma.channel[(offset - 0x2000) / 32].memory_address_counter |= data << 16; break; case 0x400e/2: case 0x404e/2: - verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Memory Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); + verboselog(*this, 2, "periphs_w: DMA(%d) Memory Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); m_dma.channel[(offset - 0x2000) / 32].memory_address_counter &= ~mem_mask; m_dma.channel[(offset - 0x2000) / 32].memory_address_counter |= data; break; case 0x4014/2: case 0x4054/2: - verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Device Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); + verboselog(*this, 2, "periphs_w: DMA(%d) Device Address Counter (High Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); m_dma.channel[(offset - 0x2000) / 32].device_address_counter &= ~(mem_mask << 16); m_dma.channel[(offset - 0x2000) / 32].device_address_counter |= data << 16; break; case 0x4016/2: case 0x4056/2: - verboselog(*this, 2, "cdi68070_periphs_w: DMA(%d) Device Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); + verboselog(*this, 2, "periphs_w: DMA(%d) Device Address Counter (Low Word): %04x & %04x\n", (offset - 0x2000) / 32, data, mem_mask); m_dma.channel[(offset - 0x2000) / 32].device_address_counter &= ~mem_mask; m_dma.channel[(offset - 0x2000) / 32].device_address_counter |= data; break; @@ -1324,12 +1338,12 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x8000/2: // Status / Control register if (ACCESSING_BITS_0_7) { // Control - verboselog(*this, 2, "cdi68070_periphs_w: MMU Control: %04x & %04x\n", data, mem_mask); + verboselog(*this, 2, "periphs_w: MMU Control: %04x & %04x\n", data, mem_mask); m_mmu.control = data & 0x00ff; } // Status else { - verboselog(*this, 0, "cdi68070_periphs_w: MMU Status (invalid): %04x & %04x\n", data, mem_mask); + verboselog(*this, 0, "periphs_w: MMU Status (invalid): %04x & %04x\n", data, mem_mask); } break; case 0x8040/2: @@ -1340,7 +1354,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x8068/2: case 0x8070/2: case 0x8078/2: // Attributes (SD0-7) - verboselog(*this, 2, "cdi68070_periphs_w: MMU descriptor %d attributes: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask); + verboselog(*this, 2, "periphs_w: MMU descriptor %d attributes: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask); COMBINE_DATA(&m_mmu.desc[(offset - 0x4020) / 4].attr); break; case 0x8042/2: @@ -1351,7 +1365,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x806a/2: case 0x8072/2: case 0x807a/2: // Segment Length (SD0-7) - verboselog(*this, 2, "cdi68070_periphs_w: MMU descriptor %d length: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask); + verboselog(*this, 2, "periphs_w: MMU descriptor %d length: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask); COMBINE_DATA(&m_mmu.desc[(offset - 0x4020) / 4].length); break; case 0x8044/2: @@ -1364,7 +1378,7 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x807c/2: // Segment Number (SD0-7, A0=1 only) if (ACCESSING_BITS_0_7) { - verboselog(*this, 2, "cdi68070_periphs_w: MMU descriptor %d segment: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask); + verboselog(*this, 2, "periphs_w: MMU descriptor %d segment: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask); m_mmu.desc[(offset - 0x4020) / 4].segment = data & 0x00ff; } break; @@ -1376,17 +1390,17 @@ WRITE16_MEMBER( cdi68070_device::periphs_w ) case 0x806e/2: case 0x8076/2: case 0x807e/2: // Base Address (SD0-7) - verboselog(*this, 2, "cdi68070_periphs_w: MMU descriptor %d base: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask); + verboselog(*this, 2, "periphs_w: MMU descriptor %d base: %04x & %04x\n", (offset - 0x4020) / 4, data, mem_mask); COMBINE_DATA(&m_mmu.desc[(offset - 0x4020) / 4].base); break; default: - verboselog(*this, 0, "cdi68070_periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); + verboselog(*this, 0, "periphs_w: Unknown address: %04x = %04x & %04x\n", offset * 2, data, mem_mask); break; } } #if ENABLE_UART_PRINTING -READ16_MEMBER( cdi68070_device::uart_loopback_enable ) +READ16_MEMBER( scc68070_device::uart_loopback_enable ) { return 0x1234; } diff --git a/src/mame/machine/cdi070.h b/src/devices/machine/scc68070.h index 1f63cca4452..c910a7d7970 100644 --- a/src/mame/machine/cdi070.h +++ b/src/devices/machine/scc68070.h @@ -3,7 +3,7 @@ /****************************************************************************** - CD-i-specific SCC68070 SoC peripheral emulation + SCC68070 SoC peripheral emulation ------------------- written by Ryan Holtz @@ -21,11 +21,13 @@ TODO: *******************************************************************************/ -#ifndef MAME_MACHINE_CDI070_H -#define MAME_MACHINE_CDI070_H +#ifndef MAME_MACHINE_SCC68070_H +#define MAME_MACHINE_SCC68070_H #pragma once +#include "cpu/m68000/m68000.h" + #define ISR_MST 0x80 // Master #define ISR_TRX 0x40 // Transmitter @@ -126,21 +128,12 @@ TODO: // TYPE DEFINITIONS //************************************************************************** -// ======================> cdi68070_device +// ======================> scc68070_device -class cdi68070_device : public device_t +class scc68070_device : public scc68070_base_device { public: - template <typename T> void set_cpu_tag(T &&tag) { m_maincpu.set_tag(std::forward<T>(tag)); } - - // construction/destruction - template <typename T> cdi68070_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag) - : cdi68070_device(mconfig, tag, owner, clock) - { - set_cpu_tag(std::forward<T>(cpu_tag)); - } - - cdi68070_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + scc68070_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); auto iack2_callback() { return m_iack2_callback.bind(); } auto iack4_callback() { return m_iack4_callback.bind(); } @@ -165,9 +158,6 @@ public: void mcu_frame(); - DECLARE_READ16_MEMBER(periphs_r); - DECLARE_WRITE16_MEMBER(periphs_w); - TIMER_CALLBACK_MEMBER( timer0_callback ); TIMER_CALLBACK_MEMBER( rx_callback ); TIMER_CALLBACK_MEMBER( tx_callback ); @@ -273,18 +263,25 @@ public: dma_regs_t& dma() { return m_dma; } - uint8_t iack_r(offs_t offset); - protected: // device-level overrides virtual void device_resolve_objects() override; virtual void device_start() override; virtual void device_reset() override; + // device_execute_interface overrides + virtual u64 execute_clocks_to_cycles(u64 clocks) const override { return (clocks + 2 - 1) / 2; } + virtual u64 execute_cycles_to_clocks(u64 cycles) const override { return (cycles * 2); } + private: - required_device<cpu_device> m_maincpu; + void internal_map(address_map &map); + void cpu_space_map(address_map &map); void update_ipl(); + uint8_t iack_r(offs_t offset); + + DECLARE_READ16_MEMBER(periphs_r); + DECLARE_WRITE16_MEMBER(periphs_w); void uart_rx_check(); void uart_tx_check(); @@ -332,6 +329,6 @@ private: }; // device type definition -DECLARE_DEVICE_TYPE(CDI_68070, cdi68070_device) +DECLARE_DEVICE_TYPE(SCC68070, scc68070_device) -#endif // MAME_MACHINE_CDI070_H +#endif // MAME_MACHINE_SCC68070_H diff --git a/src/mame/drivers/cdi.cpp b/src/mame/drivers/cdi.cpp index aa4483b9d65..44e9ea99f7b 100644 --- a/src/mame/drivers/cdi.cpp +++ b/src/mame/drivers/cdi.cpp @@ -29,7 +29,6 @@ TODO: #include "emu.h" #include "includes/cdi.h" -#include "cpu/m68000/m68000.h" #include "cpu/m6805/m6805.h" #include "imagedev/chd_cd.h" #include "machine/timekpr.h" @@ -82,7 +81,7 @@ void cdi_state::cdimono1_mem(address_map &map) map(0x00200000, 0x0027ffff).ram().share("planeb"); map(0x00300000, 0x00303bff).rw(m_cdic, FUNC(cdicdic_device::ram_r), FUNC(cdicdic_device::ram_w)); #if ENABLE_UART_PRINTING - map(0x00301400, 0x00301403).r(m_scc, FUNC(cdi68070_device::uart_loopback_enable)); + map(0x00301400, 0x00301403).r(m_maincpu, FUNC(scc68070_device::uart_loopback_enable)); #endif map(0x00303c00, 0x00303fff).rw(m_cdic, FUNC(cdicdic_device::regs_r), FUNC(cdicdic_device::regs_w)); map(0x00310000, 0x00317fff).rw(m_slave_hle, FUNC(cdislave_device::slave_r), FUNC(cdislave_device::slave_w)); @@ -93,7 +92,6 @@ void cdi_state::cdimono1_mem(address_map &map) map(0x00500000, 0x0057ffff).ram(); map(0x00580000, 0x00ffffff).noprw(); map(0x00e00000, 0x00efffff).ram(); // DVC - map(0x80000000, 0x8000807f).rw(m_scc, FUNC(cdi68070_device::periphs_r), FUNC(cdi68070_device::periphs_w)); } void cdi_state::cdimono2_mem(address_map &map) @@ -101,7 +99,7 @@ void cdi_state::cdimono2_mem(address_map &map) map(0x00000000, 0x0007ffff).ram().share("planea"); map(0x00200000, 0x0027ffff).ram().share("planeb"); #if ENABLE_UART_PRINTING - map(0x00301400, 0x00301403).r(m_scc, FUNC(cdi68070_device::uart_loopback_enable)); + map(0x00301400, 0x00301403).r(m_maincpu, FUNC(scc68070_device::uart_loopback_enable)); #endif //AM_RANGE(0x00300000, 0x00303bff) AM_DEVREADWRITE("cdic", cdicdic_device, ram_r, ram_w) //AM_RANGE(0x00303c00, 0x00303fff) AM_DEVREADWRITE("cdic", cdicdic_device, regs_r, regs_w) @@ -113,7 +111,6 @@ void cdi_state::cdimono2_mem(address_map &map) //AM_RANGE(0x00500000, 0x0057ffff) AM_RAM map(0x00500000, 0x00ffffff).noprw(); //AM_RANGE(0x00e00000, 0x00efffff) AM_RAM // DVC - map(0x80000000, 0x8000807f).rw(m_scc, FUNC(cdi68070_device::periphs_r), FUNC(cdi68070_device::periphs_w)); } void cdi_state::cdi910_mem(address_map &map) @@ -123,7 +120,7 @@ void cdi_state::cdi910_mem(address_map &map) map(0x00200000, 0x0027ffff).ram().share("planeb"); #if ENABLE_UART_PRINTING - map(0x00301400, 0x00301403).r(m_scc, FUNC(cdi68070_device::uart_loopback_enable)); + map(0x00301400, 0x00301403).r(m_maincpu, FUNC(scc68070_device::uart_loopback_enable)); #endif // AM_RANGE(0x00300000, 0x00303bff) AM_DEVREADWRITE("cdic", cdicdic_device, ram_r, ram_w) // AM_RANGE(0x00303c00, 0x00303fff) AM_DEVREADWRITE("cdic", cdicdic_device, regs_r, regs_w) @@ -134,7 +131,6 @@ void cdi_state::cdi910_mem(address_map &map) // AM_RANGE(0x00500000, 0x0057ffff) AM_RAM map(0x00500000, 0x00ffffff).noprw(); // AM_RANGE(0x00e00000, 0x00efffff) AM_RAM // DVC - map(0x80000000, 0x8000807f).rw(m_scc, FUNC(cdi68070_device::periphs_r), FUNC(cdi68070_device::periphs_w)); } @@ -153,11 +149,6 @@ void cdi_state::cdimono2_slave_mem(address_map &map) } -void cdi_state::cdi070_cpuspace(address_map &map) -{ - map(0xfffffff0, 0xffffffff).r(m_scc, FUNC(cdi68070_device::iack_r)).umask16(0x00ff); -} - /************************* * Input ports * *************************/ @@ -204,7 +195,7 @@ INPUT_CHANGED_MEMBER(cdi_state::mcu_input) if(send) { uint8_t data = (uint8_t)((uintptr_t)param & 0x000000ff); - m_scc->quizard_rx(data); + m_maincpu->quizard_rx(data); } } @@ -292,7 +283,7 @@ INPUT_PORTS_END INTERRUPT_GEN_MEMBER( cdi_state::mcu_frame ) { - m_scc->mcu_frame(); + m_maincpu->mcu_frame(); } MACHINE_RESET_MEMBER( cdi_state, cdimono1 ) @@ -319,8 +310,8 @@ MACHINE_RESET_MEMBER( cdi_state, quizard1 ) { MACHINE_RESET_CALL_MEMBER( cdimono1 ); - m_scc->set_quizard_mcu_value(0x021f); - m_scc->set_quizard_mcu_ack(0x5a); + m_maincpu->set_quizard_mcu_value(0x021f); + m_maincpu->set_quizard_mcu_ack(0x5a); } MACHINE_RESET_MEMBER( cdi_state, quizard2 ) @@ -331,8 +322,8 @@ MACHINE_RESET_MEMBER( cdi_state, quizard2 ) // 0x001: French // 0x188: German - m_scc->set_quizard_mcu_value(0x188); - m_scc->set_quizard_mcu_ack(0x59); + m_maincpu->set_quizard_mcu_value(0x188); + m_maincpu->set_quizard_mcu_ack(0x59); } @@ -341,17 +332,17 @@ MACHINE_RESET_MEMBER( cdi_state, quizard3 ) { MACHINE_RESET_CALL_MEMBER( cdimono1 ); - m_scc->set_quizard_mcu_value(0x00ae); - m_scc->set_quizard_mcu_ack(0x58); + m_maincpu->set_quizard_mcu_value(0x00ae); + m_maincpu->set_quizard_mcu_ack(0x58); } MACHINE_RESET_MEMBER( cdi_state, quizard4 ) { MACHINE_RESET_CALL_MEMBER( cdimono1 ); - //m_scc->set_quizard_mcu_value(0x0139); - m_scc->set_quizard_mcu_value(0x011f); - m_scc->set_quizard_mcu_ack(0x57); + //m_maincpu->set_quizard_mcu_value(0x0139); + m_maincpu->set_quizard_mcu_value(0x011f); + m_maincpu->set_quizard_mcu_ack(0x57); } @@ -831,14 +822,14 @@ uint32_t cdi_state::screen_update_cdimono1_lcd(screen_device &screen, bitmap_rgb // CD-i Mono-I system base void cdi_state::cdimono1_base(machine_config &config) { - SCC68070(config, m_maincpu, CLOCK_A/2); + SCC68070(config, m_maincpu, CLOCK_A); m_maincpu->set_addrmap(AS_PROGRAM, &cdi_state::cdimono1_mem); - m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &cdi_state::cdi070_cpuspace); + m_maincpu->iack4_callback().set_constant(0x80); MCD212(config, m_mcd212, CLOCK_A); m_mcd212->set_screen("screen"); - m_mcd212->int1_callback().set(m_scc, FUNC(cdi68070_device::int1_w)); - m_mcd212->int2_callback().set(m_scc, FUNC(cdi68070_device::int2_w)); + m_mcd212->int1_callback().set(m_maincpu, FUNC(scc68070_device::int1_w)); + m_mcd212->int2_callback().set(m_maincpu, FUNC(scc68070_device::int2_w)); m_mcd212->set_scanline_callback(FUNC(cdi_state::draw_lcd)); screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); @@ -859,16 +850,13 @@ void cdi_state::cdimono1_base(machine_config &config) config.set_default_layout(layout_cdi); - CDI_68070(config, m_scc, 0, "maincpu"); - m_scc->iack4_callback().set_constant(0x80); - // IMS66490 CDIC input clocks are 22.5792 MHz and 19.3536 MHz (latter is generated by PLL circuit incorporating 19.3575 MHz XTAL) // DSP input clock is 7.5264 MHz CDI_CDIC(config, m_cdic, 45.1584_MHz_XTAL / 2); - m_cdic->int_callback().set(m_scc, FUNC(cdi68070_device::in4_w)); + m_cdic->int_callback().set(m_maincpu, FUNC(scc68070_device::in4_w)); CDI_SLAVE(config, m_slave_hle, 0); - m_slave_hle->int_callback().set(m_scc, FUNC(cdi68070_device::in2_w)); + m_slave_hle->int_callback().set(m_maincpu, FUNC(scc68070_device::in2_w)); /* sound hardware */ SPEAKER(config, "lspeaker").front_left(); @@ -890,14 +878,13 @@ void cdi_state::cdimono1_base(machine_config &config) // CD-i model 220 (Mono-II, NTSC) void cdi_state::cdimono2(machine_config &config) { - SCC68070(config, m_maincpu, CLOCK_A/2); + SCC68070(config, m_maincpu, CLOCK_A); m_maincpu->set_addrmap(AS_PROGRAM, &cdi_state::cdimono2_mem); - m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &cdi_state::cdi070_cpuspace); MCD212(config, m_mcd212, CLOCK_A); m_mcd212->set_screen("screen"); - m_mcd212->int1_callback().set(m_scc, FUNC(cdi68070_device::int1_w)); - m_mcd212->int2_callback().set(m_scc, FUNC(cdi68070_device::int2_w)); + m_mcd212->int1_callback().set(m_maincpu, FUNC(scc68070_device::int1_w)); + m_mcd212->int2_callback().set(m_maincpu, FUNC(scc68070_device::int2_w)); m_mcd212->set_scanline_callback(FUNC(cdi_state::draw_lcd)); screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); @@ -920,7 +907,6 @@ void cdi_state::cdimono2(machine_config &config) MCFG_MACHINE_RESET_OVERRIDE( cdi_state, cdimono2 ) - CDI_68070(config, m_scc, 0, "maincpu"); M68HC05EG(config, m_servo, 4_MHz_XTAL); // FIXME: actually MC68HC05C8 m_servo->set_addrmap(AS_PROGRAM, &cdi_state::cdimono2_servo_mem); M68HC05EG(config, m_slave, 4_MHz_XTAL); // FIXME: actually MC68HC05C8 @@ -948,14 +934,13 @@ void cdi_state::cdimono2(machine_config &config) void cdi_state::cdi910(machine_config &config) { - SCC68070(config, m_maincpu, CLOCK_A/2); + SCC68070(config, m_maincpu, CLOCK_A); m_maincpu->set_addrmap(AS_PROGRAM, &cdi_state::cdi910_mem); - m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &cdi_state::cdi070_cpuspace); MCD212(config, m_mcd212, CLOCK_A); m_mcd212->set_screen("screen"); - m_mcd212->int1_callback().set(m_scc, FUNC(cdi68070_device::int1_w)); - m_mcd212->int2_callback().set(m_scc, FUNC(cdi68070_device::int2_w)); + m_mcd212->int1_callback().set(m_maincpu, FUNC(scc68070_device::int1_w)); + m_mcd212->int2_callback().set(m_maincpu, FUNC(scc68070_device::int2_w)); m_mcd212->set_scanline_callback(FUNC(cdi_state::draw_lcd)); screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER)); @@ -978,7 +963,6 @@ void cdi_state::cdi910(machine_config &config) MCFG_MACHINE_RESET_OVERRIDE( cdi_state, cdimono2 ) - CDI_68070(config, m_scc, 0, "maincpu"); M68HC05EG(config, m_servo, 4_MHz_XTAL); // FIXME: actually MC68HSC05C8 m_servo->set_addrmap(AS_PROGRAM, &cdi_state::cdimono2_servo_mem); M68HC05EG(config, m_slave, 4_MHz_XTAL); // FIXME: actually MC68HSC05C8 diff --git a/src/mame/drivers/magicard.cpp b/src/mame/drivers/magicard.cpp index 7fd94a4d1b4..8b366eb09ee 100644 --- a/src/mame/drivers/magicard.cpp +++ b/src/mame/drivers/magicard.cpp @@ -395,7 +395,7 @@ *******************************************************************************/ #include "emu.h" -#include "cpu/m68000/m68000.h" +#include "machine/scc68070.h" #include "sound/ay8910.h" #include "sound/saa1099.h" #include "video/ramdac.h" @@ -417,14 +417,6 @@ public: m_magicram(*this, "magicram"), m_magicramb(*this, "magicramb"), m_pcab_vregs(*this, "pcab_vregs"), - m_scc68070_ext_irqc_regs(*this, "scc_xirqc_regs"), - m_scc68070_iic_regs(*this, "scc_iic_regs"), - m_scc68070_uart_regs(*this, "scc_uart_regs"), - m_scc68070_timer_regs(*this, "scc_timer_regs"), - m_scc68070_int_irqc_regs(*this, "scc_iirqc_regs"), - m_scc68070_dma_ch1_regs(*this, "scc_dma1_regs"), - m_scc68070_dma_ch2_regs(*this, "scc_dma2_regs"), - m_scc68070_mmu_regs(*this, "scc_mmu_regs"), m_maincpu(*this, "maincpu"), m_screen(*this, "screen"), m_palette(*this, "palette") { } @@ -435,37 +427,13 @@ public: void init_magicard(); private: - u16 m_vector; + //u16 m_vector; required_shared_ptr<uint16_t> m_magicram; required_shared_ptr<uint16_t> m_magicramb; required_shared_ptr<uint16_t> m_pcab_vregs; - required_shared_ptr<uint16_t> m_scc68070_ext_irqc_regs; - required_shared_ptr<uint16_t> m_scc68070_iic_regs; - required_shared_ptr<uint16_t> m_scc68070_uart_regs; - required_shared_ptr<uint16_t> m_scc68070_timer_regs; - required_shared_ptr<uint16_t> m_scc68070_int_irqc_regs; - required_shared_ptr<uint16_t> m_scc68070_dma_ch1_regs; - required_shared_ptr<uint16_t> m_scc68070_dma_ch2_regs; - required_shared_ptr<uint16_t> m_scc68070_mmu_regs; DECLARE_READ16_MEMBER(test_r); DECLARE_READ16_MEMBER(philips_66470_r); DECLARE_WRITE16_MEMBER(philips_66470_w); - DECLARE_READ16_MEMBER(scc68070_ext_irqc_r); - DECLARE_WRITE16_MEMBER(scc68070_ext_irqc_w); - DECLARE_READ16_MEMBER(scc68070_iic_r); - DECLARE_WRITE16_MEMBER(scc68070_iic_w); - DECLARE_READ16_MEMBER(scc68070_uart_r); - DECLARE_WRITE16_MEMBER(scc68070_uart_w); - DECLARE_READ16_MEMBER(scc68070_timer_r); - DECLARE_WRITE16_MEMBER(scc68070_timer_w); - DECLARE_READ16_MEMBER(scc68070_int_irqc_r); - DECLARE_WRITE16_MEMBER(scc68070_int_irqc_w); - DECLARE_READ16_MEMBER(scc68070_dma_ch1_r); - DECLARE_WRITE16_MEMBER(scc68070_dma_ch1_w); - DECLARE_READ16_MEMBER(scc68070_dma_ch2_r); - DECLARE_WRITE16_MEMBER(scc68070_dma_ch2_w); - DECLARE_READ16_MEMBER(scc68070_mmu_r); - DECLARE_WRITE16_MEMBER(scc68070_mmu_w); virtual void machine_reset() override; virtual void video_start() override; uint32_t screen_update_magicard(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); @@ -476,8 +444,6 @@ private: void hotslots_mem(address_map &map); void magicard_mem(address_map &map); void ramdac_map(address_map &map); - void scc68070_mem(address_map &map); - void cpu_space_map(address_map &map); }; @@ -782,147 +748,14 @@ WRITE16_MEMBER(magicard_state::philips_66470_w) // } } -/* scc68070 specific stuff (to be moved) */ - -READ16_MEMBER(magicard_state::scc68070_ext_irqc_r) -{ - return m_scc68070_ext_irqc_regs[offset]; -} - -WRITE16_MEMBER(magicard_state::scc68070_ext_irqc_w) -{ - data &= mem_mask; - - m_scc68070_ext_irqc_regs[offset] = data; -} - -READ16_MEMBER(magicard_state::scc68070_iic_r) -{ - //printf("%04x\n",offset*2); - - switch(offset) - { - case 0x04/2: return m_scc68070_iic_regs[offset] & 0xef; //iic status register, bit 4 = pending irq - } - - return m_scc68070_iic_regs[offset]; -} - -WRITE16_MEMBER(magicard_state::scc68070_iic_w) -{ - data &= mem_mask; - - m_scc68070_iic_regs[offset] = data; -} - -READ16_MEMBER(magicard_state::scc68070_uart_r) -{ - //printf("%02x\n",offset*2); - - switch(offset) - { - case 0x02/2: return machine().rand(); //uart mode register - } - - return m_scc68070_uart_regs[offset]; -} - -WRITE16_MEMBER(magicard_state::scc68070_uart_w) -{ - data &= mem_mask; - - m_scc68070_uart_regs[offset] = data; -} - -READ16_MEMBER(magicard_state::scc68070_timer_r) -{ - return m_scc68070_timer_regs[offset]; -} - -WRITE16_MEMBER(magicard_state::scc68070_timer_w) -{ - data &= mem_mask; - - m_scc68070_timer_regs[offset] = data; -} - -READ16_MEMBER(magicard_state::scc68070_int_irqc_r) -{ - return m_scc68070_int_irqc_regs[offset]; -} - -WRITE16_MEMBER(magicard_state::scc68070_int_irqc_w) -{ - data &= mem_mask; - - m_scc68070_int_irqc_regs[offset] = data; -} - -READ16_MEMBER(magicard_state::scc68070_dma_ch1_r) -{ - return m_scc68070_dma_ch1_regs[offset]; -} - -WRITE16_MEMBER(magicard_state::scc68070_dma_ch1_w) -{ - data &= mem_mask; - - m_scc68070_dma_ch1_regs[offset] = data; -} - -READ16_MEMBER(magicard_state::scc68070_dma_ch2_r) -{ - return m_scc68070_dma_ch2_regs[offset]; -} - -WRITE16_MEMBER(magicard_state::scc68070_dma_ch2_w) -{ - data &= mem_mask; - - m_scc68070_dma_ch2_regs[offset] = data; -} - -READ16_MEMBER(magicard_state::scc68070_mmu_r) -{ - return m_scc68070_mmu_regs[offset]; -} - -WRITE16_MEMBER(magicard_state::scc68070_mmu_w) -{ - data &= mem_mask; - - m_scc68070_mmu_regs[offset] = data; - - switch(offset) - { - case 0x0000/2: - if(data & 0x80) //throw an error if the (unemulated) MMU is enabled - fatalerror("SCC68070: MMU enable bit active\n"); - break; - } -} - /************************* * Memory Maps * *************************/ -void magicard_state::scc68070_mem(address_map &map) -{ - map(0x80001000, 0x8000100f).rw(FUNC(magicard_state::scc68070_ext_irqc_r), FUNC(magicard_state::scc68070_ext_irqc_w)).share("scc_xirqc_regs"); //lir - map(0x80002000, 0x8000200f).rw(FUNC(magicard_state::scc68070_iic_r), FUNC(magicard_state::scc68070_iic_w)).share("scc_iic_regs"); //i2c - map(0x80002010, 0x8000201f).rw(FUNC(magicard_state::scc68070_uart_r), FUNC(magicard_state::scc68070_uart_w)).share("scc_uart_regs"); - map(0x80002020, 0x8000202f).rw(FUNC(magicard_state::scc68070_timer_r), FUNC(magicard_state::scc68070_timer_w)).share("scc_timer_regs"); - map(0x80002040, 0x8000204f).rw(FUNC(magicard_state::scc68070_int_irqc_r), FUNC(magicard_state::scc68070_int_irqc_w)).share("scc_iirqc_regs"); - map(0x80004000, 0x8000403f).rw(FUNC(magicard_state::scc68070_dma_ch1_r), FUNC(magicard_state::scc68070_dma_ch1_w)).share("scc_dma1_regs"); - map(0x80004040, 0x8000407f).rw(FUNC(magicard_state::scc68070_dma_ch2_r), FUNC(magicard_state::scc68070_dma_ch2_w)).share("scc_dma2_regs"); - map(0x80008000, 0x8000807f).rw(FUNC(magicard_state::scc68070_mmu_r), FUNC(magicard_state::scc68070_mmu_w)).share("scc_mmu_regs"); -} - void magicard_state::magicard_mem(address_map &map) { // ADDRESS_MAP_GLOBAL_MASK(0x1fffff) - scc68070_mem(map); map(0x00000000, 0x001ffbff).mirror(0x00200000).ram().share("magicram"); map(0x00600000, 0x007ffbff).ram().share("magicramb"); /* 001ffc00-001ffdff System I/O */ @@ -941,7 +774,6 @@ void magicard_state::magicard_mem(address_map &map) void magicard_state::hotslots_mem(address_map &map) { // ADDRESS_MAP_GLOBAL_MASK(0x1fffff) - scc68070_mem(map); map(0x00000000, 0x001ffbff).mirror(0x00200000).ram().share("magicram"); map(0x00600000, 0x007ffbff).ram().share("magicramb"); map(0x001fff80, 0x001fffbf).mirror(0x7fe00000).ram(); //DRAM I/O, not accessed by this game, CD buffer? @@ -970,12 +802,12 @@ void magicard_state::machine_reset() memcpy (dst, src, 0x80000); memcpy (dst + 0x40000 * 1, src, 0x80000); memcpy (dst + 0x40000 * 2, src, 0x80000); - memcpy (dst + 0x40000 * 3, src, 0x80000); + memcpy (dst + 0x40000 * 3, src, 0x7fc00); dst = m_magicramb; memcpy (dst, src, 0x80000); memcpy (dst + 0x40000 * 1, src, 0x80000); memcpy (dst + 0x40000 * 2, src, 0x80000); - memcpy (dst + 0x40000 * 3, src, 0x80000); + memcpy (dst + 0x40000 * 3, src, 0x7fc00); m_maincpu->reset(); } @@ -986,15 +818,9 @@ void magicard_state::machine_reset() /*Probably there's a mask somewhere if it REALLY uses irqs at all...irq vectors dynamically changes after some time.*/ -//In practice, needs a *real* 68070 emu -void magicard_state::cpu_space_map(address_map &map) -{ - map(0xfffff0, 0xffffff).m(m_maincpu, FUNC(m68000_base_device::autovectors_map)); - map(0xfffff2, 0xfffff3).lr16("irq 2", [this]() -> u16 { return m_vector; }); -} - INTERRUPT_GEN_MEMBER(magicard_state::magicard_irq) { +#if 0 if(machine().input().code_pressed(KEYCODE_Z)) { //vblank? m_vector = 0xe4; device.execute().set_input_line(1, HOLD_LINE); @@ -1002,7 +828,8 @@ INTERRUPT_GEN_MEMBER(magicard_state::magicard_irq) if(machine().input().code_pressed(KEYCODE_X)) { //uart irq m_vector = 0xf0; device.execute().set_input_line(1, HOLD_LINE); - } + } +#endif } void magicard_state::ramdac_map(address_map &map) @@ -1013,9 +840,8 @@ void magicard_state::ramdac_map(address_map &map) void magicard_state::magicard(machine_config &config) { - SCC68070(config, m_maincpu, CLOCK_A / 2); /* SCC-68070 CCA84 datasheet */ + SCC68070(config, m_maincpu, CLOCK_A); /* SCC-68070 CCA84 datasheet */ m_maincpu->set_addrmap(AS_PROGRAM, &magicard_state::magicard_mem); - m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &magicard_state::cpu_space_map); m_maincpu->set_vblank_int("screen", FUNC(magicard_state::magicard_irq)); /* no interrupts? (it erases the vectors..) */ SCREEN(config, m_screen, SCREEN_TYPE_RASTER); diff --git a/src/mame/includes/cdi.h b/src/mame/includes/cdi.h index ef5e1b9c9cb..5caf579a772 100644 --- a/src/mame/includes/cdi.h +++ b/src/mame/includes/cdi.h @@ -4,7 +4,7 @@ #ifndef MAME_INCLUDES_CDI_H #define MAME_INCLUDES_CDI_H -#include "machine/cdi070.h" +#include "machine/scc68070.h" #include "machine/cdislave.h" #include "machine/cdicdic.h" #include "sound/dmadac.h" @@ -27,7 +27,6 @@ public: , m_slave_hle(*this, "slave_hle") , m_servo(*this, "servo") , m_slave(*this, "slave") - , m_scc(*this, "scc68070") , m_cdic(*this, "cdic") , m_cdda(*this, "cdda") , m_mcd212(*this, "mcd212") @@ -71,7 +70,7 @@ public: INV_CADDYSWITCH_IN = (1 << 7) }; - required_device<cpu_device> m_maincpu; + required_device<scc68070_device> m_maincpu; required_shared_ptr<uint16_t> m_planea; required_shared_ptr<uint16_t> m_planeb; optional_ioport m_input1; @@ -79,7 +78,6 @@ public: optional_device<cdislave_device> m_slave_hle; optional_device<cpu_device> m_servo; optional_device<cpu_device> m_slave; - required_device<cdi68070_device> m_scc; optional_device<cdicdic_device> m_cdic; required_device<cdda_device> m_cdda; required_device<mcd212_device> m_mcd212; diff --git a/src/mame/machine/cdicdic.cpp b/src/mame/machine/cdicdic.cpp index 781c5d412ea..98717ee7c29 100644 --- a/src/mame/machine/cdicdic.cpp +++ b/src/mame/machine/cdicdic.cpp @@ -23,7 +23,6 @@ TODO: #include "emu.h" #include "machine/cdicdic.h" -#include "includes/cdi.h" #include "cdrom.h" #include "romload.h" @@ -38,7 +37,7 @@ TODO: // device type definition -DEFINE_DEVICE_TYPE(CDI_CDIC, cdicdic_device, "cdicdic", "CDICDIC") +DEFINE_DEVICE_TYPE(CDI_CDIC, cdicdic_device, "cdicdic", "CD-i CDIC") #if ENABLE_VERBOSE_LOG static inline void ATTR_PRINTF(3,4) verboselog(device_t& device, int n_level, const char *s_fmt, ...) @@ -1161,7 +1160,7 @@ cdicdic_device::cdicdic_device(const machine_config &mconfig, const char *tag, d , m_int_callback(*this) , m_memory_space(*this, ":maincpu", AS_PROGRAM) , m_dmadac(*this, ":dac%u", 1U) - , m_scc(*this, ":scc68070") + , m_scc(*this, ":maincpu") , m_cdda(*this, ":cdda") , m_cdrom_dev(*this, ":cdrom") { diff --git a/src/mame/machine/cdicdic.h b/src/mame/machine/cdicdic.h index e16bdf5150a..b7832d54235 100644 --- a/src/mame/machine/cdicdic.h +++ b/src/mame/machine/cdicdic.h @@ -27,7 +27,7 @@ TODO: #pragma once #include "imagedev/chd_cd.h" -#include "machine/cdi070.h" +#include "machine/scc68070.h" #include "sound/cdda.h" #include "sound/dmadac.h" #include "cdrom.h" @@ -72,7 +72,7 @@ private: required_address_space m_memory_space; required_device_array<dmadac_sound_device, 2> m_dmadac; - required_device<cdi68070_device> m_scc; + required_device<scc68070_device> m_scc; required_device<cdda_device> m_cdda; optional_device<cdrom_image_device> m_cdrom_dev; |