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author yz70s <yz70s@users.noreply.github.com>2017-11-19 18:46:44 +0100
committer yz70s <yz70s@users.noreply.github.com>2017-11-19 20:54:57 +0100
commitad9dac1ac79093d1174782e5b6f56de1b74aa11b (patch)
tree666abda10c6ea7ee2a9e72388738d948faf45e45
parent6b5b4c345ccd02c6d36ffdab0ef512fffa5f67c2 (diff)
southbridge.cpp: some updates: (nw)
not all sothbridges have an internal keyboard controller,rtc,serial and parallel devices now southbridge_device does not have them there is a new southbridge_extended_device that has them i82371ab_device derives from southbridge_extended_device converted comments to c++
-rw-r--r--src/devices/bus/lpci/i82371ab.cpp32
-rw-r--r--src/devices/bus/lpci/i82371ab.h2
-rw-r--r--src/devices/bus/lpci/i82371sb.cpp56
-rw-r--r--src/devices/bus/lpci/southbridge.cpp126
-rw-r--r--src/devices/bus/lpci/southbridge.h30
5 files changed, 165 insertions, 81 deletions
diff --git a/src/devices/bus/lpci/i82371ab.cpp b/src/devices/bus/lpci/i82371ab.cpp
index 1c6d2f0e166..df44ac6c1d1 100644
--- a/src/devices/bus/lpci/i82371ab.cpp
+++ b/src/devices/bus/lpci/i82371ab.cpp
@@ -23,7 +23,7 @@ DEFINE_DEVICE_TYPE(I82371AB, i82371ab_device, "i82371ab", "Intel 82371AB")
i82371ab_device::i82371ab_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : southbridge_device(mconfig, I82371AB, tag, owner, clock)
+ : southbridge_extended_device(mconfig, I82371AB, tag, owner, clock)
, pci_device_interface(mconfig, *this)
{
}
@@ -53,11 +53,11 @@ void i82371ab_device::pci_isa_w(device_t *busdevice, int offset, uint32_t data,
switch (offset)
{
case 0x04:
- /* clear reserved bits */
+ // clear reserved bits
m_regs[0][offset] = cdata & 0x05;
break;
case 0x06:
- /* set new status */
+ // set new status
m_regs[0][offset] |= 0x80;
break;
case 0x07:
@@ -92,11 +92,11 @@ void i82371ab_device::pci_ide_w(device_t *busdevice, int offset, uint32_t data,
switch (offset)
{
case 0x04:
- /* clear reserved bits */
+ // clear reserved bits
m_regs[1][offset] = cdata & 0x05;
break;
case 0x06:
- /* set new status */
+ // set new status
m_regs[1][offset] |= 0x80;
break;
case 0x07:
@@ -131,11 +131,11 @@ void i82371ab_device::pci_usb_w(device_t *busdevice, int offset, uint32_t data,
switch (offset)
{
case 0x04:
- /* clear reserved bits */
+ // clear reserved bits
m_regs[2][offset] = cdata & 0x05;
break;
case 0x06:
- /* set new status */
+ // set new status
m_regs[2][offset] |= 0x80;
break;
case 0x07:
@@ -170,11 +170,11 @@ void i82371ab_device::pci_acpi_w(device_t *busdevice, int offset, uint32_t data,
switch (offset)
{
case 0x04:
- /* clear reserved bits */
+ // clear reserved bits
m_regs[3][offset] = cdata & 0x05;
break;
case 0x06:
- /* set new status */
+ // set new status
m_regs[3][offset] |= 0x80;
break;
case 0x07:
@@ -216,8 +216,8 @@ void i82371ab_device::pci_write(pci_bus_device *pcibus, int function, int offset
void i82371ab_device::device_start()
{
- southbridge_device::device_start();
- /* setup save states */
+ southbridge_extended_device::device_start();
+ // setup save states
save_item(NAME(m_regs));
}
@@ -227,29 +227,29 @@ void i82371ab_device::device_start()
void i82371ab_device::device_reset()
{
- southbridge_device::device_reset();
+ southbridge_extended_device::device_reset();
memset(m_regs, 0, sizeof(m_regs));
uint32_t (*regs32)[64] = (uint32_t (*)[64])(m_regs);
- /* isa */
+ // isa
regs32[0][0x00] = 0x71108086;
regs32[0][0x04] = 0x00000000;
regs32[0][0x08] = 0x06010000;
regs32[0][0x0c] = 0x00800000;
- /* ide */
+ // ide
regs32[1][0x00] = 0x71118086;
regs32[1][0x04] = 0x02800000;
regs32[1][0x08] = 0x01018000;
regs32[1][0x0c] = 0x00000000;
- /* usb */
+ // usb
regs32[2][0x00] = 0x71128086;
regs32[2][0x04] = 0x02800000;
regs32[2][0x08] = 0x0c030000;
regs32[2][0x0c] = 0x00000000;
- /* acpi */
+ // acpi
regs32[3][0x00] = 0x71138086;
regs32[3][0x04] = 0x02800000;
regs32[3][0x08] = 0x06800000;
diff --git a/src/devices/bus/lpci/i82371ab.h b/src/devices/bus/lpci/i82371ab.h
index dc251bee0bf..776ae8d00d5 100644
--- a/src/devices/bus/lpci/i82371ab.h
+++ b/src/devices/bus/lpci/i82371ab.h
@@ -18,7 +18,7 @@
// ======================> i82371ab_device
-class i82371ab_device : public southbridge_device,
+class i82371ab_device : public southbridge_extended_device,
public pci_device_interface
{
public:
diff --git a/src/devices/bus/lpci/i82371sb.cpp b/src/devices/bus/lpci/i82371sb.cpp
index 6fd7308a922..e30640440e8 100644
--- a/src/devices/bus/lpci/i82371sb.cpp
+++ b/src/devices/bus/lpci/i82371sb.cpp
@@ -19,6 +19,7 @@
#include "emu.h"
#include "i82371sb.h"
+//#define VERBOSE
/***************************************************************************
IMPLEMENTATION
@@ -38,24 +39,28 @@ uint32_t i82371sb_device::pci_isa_r(device_t *busdevice,int offset, uint32_t mem
{
uint32_t result = m_regs[0][offset];
- //logerror("i82371sb_pci_isa_r, offset = %02x, mem_mask = %08x\n", offset, mem_mask);
+#ifdef VERBOSE
+ logerror("i82371sb_pci_isa_r, offset = %02x, mem_mask = %08x\n", offset, mem_mask);
+#endif
return result;
}
void i82371sb_device::pci_isa_w(device_t *busdevice, int offset, uint32_t data, uint32_t mem_mask)
{
- //logerror("i82371sb_pci_isa_w, offset = %02x, data = %08x, mem_mask = %08x\n", offset, data, mem_mask);
+#ifdef VERBOSE
+ logerror("i82371sb_pci_isa_w, offset = %02x, data = %08x, mem_mask = %08x\n", offset, data, mem_mask);
+#endif
switch (offset)
{
case 0x04:
COMBINE_DATA(&m_regs[0][offset]);
- /* clear reserved bits */
+ // clear reserved bits
m_regs[0][offset] &= 0x00000005;
- /* set new status */
+ // set new status
m_regs[0][offset] |= 0x02800000;
break;
@@ -64,24 +69,30 @@ void i82371sb_device::pci_isa_w(device_t *busdevice, int offset, uint32_t data,
uint32_t i82371sb_device::pci_ide_r(device_t *busdevice, int offset, uint32_t mem_mask)
{
- //logerror("i82371sb_pci_ide_r, offset = %02x, mem_mask = %08x\n", offset, mem_mask);
uint32_t result = m_regs[1][offset];
+
+#ifdef VERBOSE
+ logerror("i82371sb_pci_ide_r, offset = %02x, mem_mask = %08x\n", offset, mem_mask);
+#endif
+
return result;
}
void i82371sb_device::pci_ide_w(device_t *busdevice, int offset, uint32_t data, uint32_t mem_mask)
{
- //logerror("i82371sb_pci_ide_w, offset = %02x, data = %08x, mem_mask = %08x\n", offset, data, mem_mask);
+#ifdef VERBOSE
+ logerror("i82371sb_pci_ide_w, offset = %02x, data = %08x, mem_mask = %08x\n", offset, data, mem_mask);
+#endif
switch (offset)
{
case 0x04:
COMBINE_DATA(&m_regs[1][offset]);
- /* clear reserved bits */
+ // clear reserved bits
m_regs[1][offset] &= 0x00000005;
- /* set new status */
+ // set new status
m_regs[1][offset] |= 0x02800000;
break;
@@ -92,24 +103,28 @@ uint32_t i82371sb_device::pci_usb_r(device_t *busdevice, int offset, uint32_t me
{
uint32_t result = m_regs[2][offset];
- //logerror("i82371sb_pci_usb_r, offset = %02x, mem_mask = %08x\n", offset, mem_mask);
+#ifdef VERBOSE
+ logerror("i82371sb_pci_usb_r, offset = %02x, mem_mask = %08x\n", offset, mem_mask);
+#endif
return result;
}
void i82371sb_device::pci_usb_w(device_t *busdevice, int offset, uint32_t data, uint32_t mem_mask)
{
- //logerror("i82371sb_pci_usb_w, offset = %02x, data = %08x, mem_mask = %08x\n", offset, data, mem_mask);
+#ifdef VERBOSE
+ logerror("i82371sb_pci_usb_w, offset = %02x, data = %08x, mem_mask = %08x\n", offset, data, mem_mask);
+#endif
switch (offset)
{
case 0x04:
COMBINE_DATA(&m_regs[2][offset]);
- /* clear reserved bits */
+ // clear reserved bits
m_regs[2][offset] &= 0x00000005;
- /* set new status */
+ // set new status
m_regs[2][offset] |= 0x02800000;
break;
@@ -124,8 +139,9 @@ uint32_t i82371sb_device::pci_read(pci_bus_device *pcibus, int function, int off
case 1: return pci_ide_r(pcibus, offset, mem_mask);
case 2: return pci_usb_r(pcibus, offset, mem_mask);
}
-
- //logerror("i82371sb_pci_read: read from undefined function %d\n", function);
+#ifdef VERBOSE
+ logerror("i82371sb_pci_read: read from undefined function %d offset %08X mask %08X\n", function,offset,mem_mask);
+#endif
return 0;
}
@@ -138,7 +154,9 @@ void i82371sb_device::pci_write(pci_bus_device *pcibus, int function, int offset
case 1: pci_ide_w(pcibus, offset, data, mem_mask); break;
case 2: pci_usb_w(pcibus, offset, data, mem_mask); break;
}
- //logerror("i82371sb_pci_write: write to undefined function %d\n", function);
+#ifdef VERBOSE
+ logerror("i82371sb_pci_write: write to undefined function %d offset %08X mask %08X data %08X\n", function, offset, mem_mask, data);
+#endif
}
//-------------------------------------------------
@@ -149,7 +167,7 @@ void i82371sb_device::device_start()
{
southbridge_device::device_start();
m_boot_state_hook.resolve_safe();
- /* setup save states */
+ // setup save states
save_item(NAME(m_regs));
}
@@ -163,19 +181,19 @@ void i82371sb_device::device_reset()
memset(m_regs, 0, sizeof(m_regs));
- /* isa */
+ // isa
m_regs[0][0x00] = 0x70008086;
m_regs[0][0x04] = 0x00000000;
m_regs[0][0x08] = 0x06010000;
m_regs[0][0x0c] = 0x00800000;
- /* ide */
+ // ide
m_regs[1][0x00] = 0x70108086;
m_regs[1][0x04] = 0x02800000;
m_regs[1][0x08] = 0x01018000;
m_regs[1][0x0c] = 0x00000000;
- /* usb */
+ // usb
m_regs[2][0x00] = 0x70208086;
m_regs[2][0x04] = 0x02800000;
m_regs[2][0x08] = 0x0c030000;
diff --git a/src/devices/bus/lpci/southbridge.cpp b/src/devices/bus/lpci/southbridge.cpp
index c571815ab06..a9b7350cff6 100644
--- a/src/devices/bus/lpci/southbridge.cpp
+++ b/src/devices/bus/lpci/southbridge.cpp
@@ -17,12 +17,9 @@
#include "speaker.h"
-static SLOT_INTERFACE_START(pc_isa_onboard)
- SLOT_INTERFACE("comat", ISA8_COM_AT)
- SLOT_INTERFACE("lpt", ISA8_LPT)
- SLOT_INTERFACE("fdcsmc", ISA8_FDC_SMC)
-SLOT_INTERFACE_END
-
+/***************************************************************************
+ Southbridge Device
+***************************************************************************/
//-------------------------------------------------
// device_add_mconfig - add device configuration
@@ -30,11 +27,11 @@ SLOT_INTERFACE_END
MACHINE_CONFIG_MEMBER( southbridge_device::device_add_mconfig )
MCFG_DEVICE_ADD("pit8254", PIT8254, 0)
- MCFG_PIT8253_CLK0(4772720/4) /* heartbeat IRQ */
+ MCFG_PIT8253_CLK0(4772720/4) // heartbeat IRQ
MCFG_PIT8253_OUT0_HANDLER(WRITELINE(southbridge_device, at_pit8254_out0_changed))
- MCFG_PIT8253_CLK1(4772720/4) /* dram refresh */
+ MCFG_PIT8253_CLK1(4772720/4) // dram refresh
MCFG_PIT8253_OUT1_HANDLER(WRITELINE(southbridge_device, at_pit8254_out1_changed))
- MCFG_PIT8253_CLK2(4772720/4) /* pio port c pin 4, and speaker polling enough */
+ MCFG_PIT8253_CLK2(4772720/4) // pio port c pin 4, and speaker polling enough
MCFG_PIT8253_OUT2_HANDLER(WRITELINE(southbridge_device, at_pit8254_out2_changed))
MCFG_DEVICE_ADD( "dma8237_1", AM9517A, XTAL_14_31818MHz/3 )
@@ -79,21 +76,6 @@ MACHINE_CONFIG_MEMBER( southbridge_device::device_add_mconfig )
MCFG_PIC8259_OUT_INT_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir2_w))
MCFG_PIC8259_IN_SP_CB(GND)
- MCFG_DEVICE_ADD("keybc", AT_KEYBOARD_CONTROLLER, XTAL_12MHz)
- MCFG_AT_KEYBOARD_CONTROLLER_SYSTEM_RESET_CB(INPUTLINE(":maincpu", INPUT_LINE_RESET))
- MCFG_AT_KEYBOARD_CONTROLLER_GATE_A20_CB(INPUTLINE(":maincpu", INPUT_LINE_A20))
- MCFG_AT_KEYBOARD_CONTROLLER_INPUT_BUFFER_FULL_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir1_w))
- MCFG_AT_KEYBOARD_CONTROLLER_KEYBOARD_CLOCK_CB(DEVWRITELINE("pc_kbdc", pc_kbdc_device, clock_write_from_mb))
- MCFG_AT_KEYBOARD_CONTROLLER_KEYBOARD_DATA_CB(DEVWRITELINE("pc_kbdc", pc_kbdc_device, data_write_from_mb))
- MCFG_DEVICE_ADD("pc_kbdc", PC_KBDC, 0)
- MCFG_PC_KBDC_OUT_CLOCK_CB(DEVWRITELINE("keybc", at_keyboard_controller_device, keyboard_clock_w))
- MCFG_PC_KBDC_OUT_DATA_CB(DEVWRITELINE("keybc", at_keyboard_controller_device, keyboard_data_w))
- MCFG_PC_KBDC_SLOT_ADD("pc_kbdc", "kbd", pc_at_keyboards, STR_KBD_MICROSOFT_NATURAL)
-
- MCFG_DS12885_ADD("rtc")
- MCFG_MC146818_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir0_w))
- MCFG_MC146818_CENTURY_INDEX(0x32)
-
MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", nullptr, false)
MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir6_w))
MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
@@ -102,7 +84,7 @@ MACHINE_CONFIG_MEMBER( southbridge_device::device_add_mconfig )
MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir7_w))
MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
- /* sound hardware */
+ // sound hardware
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_SOUND_ADD("speaker", SPEAKER_SOUND, 0)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
@@ -127,10 +109,6 @@ MACHINE_CONFIG_MEMBER( southbridge_device::device_add_mconfig )
MCFG_ISA_OUT_DRQ5_CB(DEVWRITELINE("dma8237_2", am9517a_device, dreq1_w))
MCFG_ISA_OUT_DRQ6_CB(DEVWRITELINE("dma8237_2", am9517a_device, dreq2_w))
MCFG_ISA_OUT_DRQ7_CB(DEVWRITELINE("dma8237_2", am9517a_device, dreq3_w))
- // on board devices
- MCFG_ISA16_SLOT_ADD("isabus","board1", pc_isa_onboard, "fdcsmc", true)
- MCFG_ISA16_SLOT_ADD("isabus","board2", pc_isa_onboard, "comat", true)
- MCFG_ISA16_SLOT_ADD("isabus","board3", pc_isa_onboard, "lpt", true)
MACHINE_CONFIG_END
southbridge_device::southbridge_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
@@ -141,15 +119,14 @@ southbridge_device::southbridge_device(const machine_config &mconfig, device_typ
m_dma8237_1(*this, "dma8237_1"),
m_dma8237_2(*this, "dma8237_2"),
m_pit8254(*this, "pit8254"),
- m_keybc(*this, "keybc"),
m_isabus(*this, "isabus"),
m_speaker(*this, "speaker"),
- m_ds12885(*this, "rtc"),
- m_pc_kbdc(*this, "pc_kbdc"),
m_ide(*this, "ide"),
- m_ide2(*this, "ide2"), m_at_spkrdata(0), m_pit_out2(0), m_dma_channel(0), m_cur_eop(false), m_dma_high_byte(0), m_at_speaker(0), m_refresh(false), m_channel_check(0), m_nmi_enabled(0)
+ m_ide2(*this, "ide2"),
+ m_at_spkrdata(0), m_pit_out2(0), m_dma_channel(0), m_cur_eop(false), m_dma_high_byte(0), m_at_speaker(0), m_refresh(false), m_channel_check(0), m_nmi_enabled(0)
{
}
+
/**********************************************************
*
* Init functions
@@ -188,10 +165,7 @@ void southbridge_device::device_start()
spaceio.install_readwrite_handler(0x0000, 0x001f, read8_delegate(FUNC(am9517a_device::read),&(*m_dma8237_1)), write8_delegate(FUNC(am9517a_device::write),&(*m_dma8237_1)), 0xffffffff);
spaceio.install_readwrite_handler(0x0020, 0x003f, read8_delegate(FUNC(pic8259_device::read),&(*m_pic8259_master)), write8_delegate(FUNC(pic8259_device::write),&(*m_pic8259_master)), 0xffffffff);
spaceio.install_readwrite_handler(0x0040, 0x005f, read8_delegate(FUNC(pit8254_device::read),&(*m_pit8254)), write8_delegate(FUNC(pit8254_device::write),&(*m_pit8254)), 0xffffffff);
- spaceio.install_readwrite_handler(0x0060, 0x0063, read8_delegate(FUNC(at_keyboard_controller_device::data_r), &(*m_keybc)), write8_delegate(FUNC(at_keyboard_controller_device::data_w), &(*m_keybc)), 0x000000ff);
spaceio.install_readwrite_handler(0x0060, 0x0063, read8_delegate(FUNC(southbridge_device::at_portb_r), this), write8_delegate(FUNC(southbridge_device::at_portb_w), this), 0x0000ff00);
- spaceio.install_readwrite_handler(0x0064, 0x0067, read8_delegate(FUNC(at_keyboard_controller_device::status_r),&(*m_keybc)), write8_delegate(FUNC(at_keyboard_controller_device::command_w),&(*m_keybc)), 0xffffffff);
- spaceio.install_readwrite_handler(0x0070, 0x007f, read8_delegate(FUNC(ds12885_device::read),&(*m_ds12885)), write8_delegate(FUNC(ds12885_device::write),&(*m_ds12885)), 0xffffffff);
spaceio.install_readwrite_handler(0x0080, 0x009f, read8_delegate(FUNC(southbridge_device::at_page8_r),this), write8_delegate(FUNC(southbridge_device::at_page8_w),this), 0xffffffff);
spaceio.install_readwrite_handler(0x00a0, 0x00bf, read8_delegate(FUNC(pic8259_device::read),&(*m_pic8259_slave)), write8_delegate(FUNC(pic8259_device::write),&(*m_pic8259_slave)), 0xffffffff);
spaceio.install_readwrite_handler(0x00c0, 0x00df, read8_delegate(FUNC(southbridge_device::at_dma8237_2_r),this), write8_delegate(FUNC(southbridge_device::at_dma8237_2_w),this), 0xffffffff);
@@ -328,7 +302,7 @@ WRITE_LINE_MEMBER( southbridge_device::pc_dma_hrq_changed )
{
m_maincpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
- /* Assert HLDA */
+ // Assert HLDA
m_dma8237_2->hack_w( state );
}
@@ -433,15 +407,15 @@ WRITE_LINE_MEMBER( southbridge_device::pc_dack7_w ) { pc_select_dma_channel(7, s
READ8_MEMBER( southbridge_device::at_portb_r )
{
uint8_t data = m_at_speaker;
- data &= ~0xd0; /* AT BIOS don't likes this being set */
+ data &= ~0xd0; // AT BIOS don't likes this being set
- /* 0x10 is the dram refresh line bit on the 5170, just a timer here, 15.085us. */
+ // 0x10 is the dram refresh line bit on the 5170, just a timer here, 15.085us.
data |= m_refresh ? 0x10 : 0;
if (m_pit_out2)
data |= 0x20;
else
- data &= ~0x20; /* ps2m30 wants this */
+ data &= ~0x20; // ps2m30 wants this
return data;
}
@@ -465,7 +439,77 @@ WRITE8_MEMBER( southbridge_device::at_dma8237_2_w )
m_dma8237_2->write( space, offset / 2, data);
}
-WRITE8_MEMBER( southbridge_device::write_rtc )
+/***************************************************************************
+ Extended Southbridge Device
+***************************************************************************/
+
+static SLOT_INTERFACE_START(pc_isa_onboard)
+ SLOT_INTERFACE("comat", ISA8_COM_AT)
+ SLOT_INTERFACE("lpt", ISA8_LPT)
+ SLOT_INTERFACE("fdcsmc", ISA8_FDC_SMC)
+SLOT_INTERFACE_END
+
+//-------------------------------------------------
+// device_add_mconfig - add device configuration
+//-------------------------------------------------
+
+MACHINE_CONFIG_MEMBER(southbridge_extended_device::device_add_mconfig)
+ southbridge_device::device_add_mconfig(config);
+
+ MCFG_DEVICE_ADD("keybc", AT_KEYBOARD_CONTROLLER, XTAL_12MHz)
+ MCFG_AT_KEYBOARD_CONTROLLER_SYSTEM_RESET_CB(INPUTLINE(":maincpu", INPUT_LINE_RESET))
+ MCFG_AT_KEYBOARD_CONTROLLER_GATE_A20_CB(INPUTLINE(":maincpu", INPUT_LINE_A20))
+ MCFG_AT_KEYBOARD_CONTROLLER_INPUT_BUFFER_FULL_CB(DEVWRITELINE("pic8259_master", pic8259_device, ir1_w))
+ MCFG_AT_KEYBOARD_CONTROLLER_KEYBOARD_CLOCK_CB(DEVWRITELINE("pc_kbdc", pc_kbdc_device, clock_write_from_mb))
+ MCFG_AT_KEYBOARD_CONTROLLER_KEYBOARD_DATA_CB(DEVWRITELINE("pc_kbdc", pc_kbdc_device, data_write_from_mb))
+ MCFG_DEVICE_ADD("pc_kbdc", PC_KBDC, 0)
+ MCFG_PC_KBDC_OUT_CLOCK_CB(DEVWRITELINE("keybc", at_keyboard_controller_device, keyboard_clock_w))
+ MCFG_PC_KBDC_OUT_DATA_CB(DEVWRITELINE("keybc", at_keyboard_controller_device, keyboard_data_w))
+ MCFG_PC_KBDC_SLOT_ADD("pc_kbdc", "kbd", pc_at_keyboards, STR_KBD_MICROSOFT_NATURAL)
+
+ MCFG_DS12885_ADD("rtc")
+ MCFG_MC146818_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir0_w))
+ MCFG_MC146818_CENTURY_INDEX(0x32)
+
+ // on board devices
+ MCFG_ISA16_SLOT_ADD("isabus", "board1", pc_isa_onboard, "fdcsmc", true)
+ MCFG_ISA16_SLOT_ADD("isabus", "board2", pc_isa_onboard, "comat", true)
+ MCFG_ISA16_SLOT_ADD("isabus", "board3", pc_isa_onboard, "lpt", true)
+MACHINE_CONFIG_END
+
+southbridge_extended_device::southbridge_extended_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+ : southbridge_device(mconfig, type, tag, owner, clock),
+ m_keybc(*this, "keybc"),
+ m_ds12885(*this, "rtc"),
+ m_pc_kbdc(*this, "pc_kbdc")
+{
+}
+
+//-------------------------------------------------
+// device_start - device-specific startup
+//-------------------------------------------------
+
+void southbridge_extended_device::device_start()
+{
+ address_space& spaceio = machine().device(":maincpu")->memory().space(AS_IO);
+
+ southbridge_device::device_start();
+
+ spaceio.install_readwrite_handler(0x0060, 0x0063, read8_delegate(FUNC(at_keyboard_controller_device::data_r), &(*m_keybc)), write8_delegate(FUNC(at_keyboard_controller_device::data_w), &(*m_keybc)), 0x000000ff);
+ spaceio.install_readwrite_handler(0x0064, 0x0067, read8_delegate(FUNC(at_keyboard_controller_device::status_r), &(*m_keybc)), write8_delegate(FUNC(at_keyboard_controller_device::command_w), &(*m_keybc)), 0xffffffff);
+ spaceio.install_readwrite_handler(0x0070, 0x007f, read8_delegate(FUNC(ds12885_device::read), &(*m_ds12885)), write8_delegate(FUNC(ds12885_device::write), &(*m_ds12885)), 0xffffffff);
+}
+
+//-------------------------------------------------
+// device_reset - device-specific reset
+//-------------------------------------------------
+
+void southbridge_extended_device::device_reset()
+{
+ southbridge_device::device_reset();
+}
+
+WRITE8_MEMBER( southbridge_extended_device::write_rtc )
{
if (offset==0) {
m_nmi_enabled = BIT(data,7);
diff --git a/src/devices/bus/lpci/southbridge.h b/src/devices/bus/lpci/southbridge.h
index 93d116c442b..011f43476ee 100644
--- a/src/devices/bus/lpci/southbridge.h
+++ b/src/devices/bus/lpci/southbridge.h
@@ -58,11 +58,8 @@ protected:
required_device<am9517a_device> m_dma8237_1;
required_device<am9517a_device> m_dma8237_2;
required_device<pit8254_device> m_pit8254;
- required_device<at_keyboard_controller_device> m_keybc;
required_device<isa16_device> m_isabus;
required_device<speaker_sound_device> m_speaker;
- required_device<ds12885_device> m_ds12885;
- required_device<pc_kbdc_device> m_pc_kbdc;
required_device<bus_master_ide_controller_device> m_ide;
required_device<bus_master_ide_controller_device> m_ide2;
@@ -121,11 +118,36 @@ private:
DECLARE_WRITE8_MEMBER(ide2_write_cs1_w);
DECLARE_READ8_MEMBER(at_dma8237_2_r);
DECLARE_WRITE8_MEMBER(at_dma8237_2_w);
- DECLARE_WRITE8_MEMBER(write_rtc);
DECLARE_READ8_MEMBER(pc_dma_read_byte);
DECLARE_WRITE8_MEMBER(pc_dma_write_byte);
DECLARE_READ8_MEMBER(pc_dma_read_word);
DECLARE_WRITE8_MEMBER(pc_dma_write_word);
};
+// ======================> southbridge_extended_device
+
+class southbridge_extended_device :
+ public southbridge_device
+{
+public:
+
+
+protected:
+ // construction/destruction
+ southbridge_extended_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+ // optional information overrides
+ virtual void device_add_mconfig(machine_config &config) override;
+
+ // device-level overrides
+ virtual void device_start() override;
+ virtual void device_reset() override;
+ required_device<at_keyboard_controller_device> m_keybc;
+ required_device<ds12885_device> m_ds12885;
+ required_device<pc_kbdc_device> m_pc_kbdc;
+
+private:
+ DECLARE_WRITE8_MEMBER(write_rtc);
+};
+
#endif // MAME_BUS_LPCI_SOUTHBRIDGE_H