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author | Patrick Mackinlay <pmackinlay@hotmail.com> | 2018-11-19 21:02:48 +0700 |
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committer | Patrick Mackinlay <pmackinlay@hotmail.com> | 2018-11-19 21:02:48 +0700 |
commit | aa186556c434b2786e88867103a78c8c0dcca7bf (patch) | |
tree | 2c53bf8cfdd3b2fb58010b0e6336420ac5f30f51 | |
parent | 18d0fee8ba84ce5864f6d8e2b38aac81f2d4fbc4 (diff) |
mips1: handle no cache (nw)
-rw-r--r-- | src/devices/cpu/mips/mips1.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/devices/cpu/mips/mips1.cpp b/src/devices/cpu/mips/mips1.cpp index 05e3996d96f..57c0c151d55 100644 --- a/src/devices/cpu/mips/mips1.cpp +++ b/src/devices/cpu/mips/mips1.cpp @@ -156,12 +156,14 @@ void mips1core_device_base::device_add_mconfig(machine_config &config) void mips1core_device_base::icache_map(address_map &map) { - map(0, m_icache_size - 1).ram().mirror(~(m_icache_size - 1)); + if (m_icache_size) + map(0, m_icache_size - 1).ram().mirror(~(m_icache_size - 1)); } void mips1core_device_base::dcache_map(address_map &map) { - map(0, m_dcache_size - 1).ram().mirror(~(m_dcache_size - 1)); + if (m_dcache_size) + map(0, m_dcache_size - 1).ram().mirror(~(m_dcache_size - 1)); } void mips1core_device_base::device_start() |