diff options
author | 2013-06-08 15:42:11 +0000 | |
---|---|---|
committer | 2013-06-08 15:42:11 +0000 | |
commit | 9eafc98ed9992e5d2067b2cbfaa53dae582976c8 (patch) | |
tree | aa7f701d25232324d1733425738e15be527a3f5b | |
parent | bac361dd3df9e5744268f3cf91b16855e349697b (diff) |
First pass at tidying up ide interface. It no longer tries to force everything to act as a PC. A copy of the VIA VT83C461 datasheet would be useful to remove some of the hacks added to make the games using it work again. [smf]
46 files changed, 617 insertions, 1065 deletions
diff --git a/src/emu/machine/ataflash.c b/src/emu/machine/ataflash.c index 2397ae57ad0..e175fb19a51 100644 --- a/src/emu/machine/ataflash.c +++ b/src/emu/machine/ataflash.c @@ -41,12 +41,30 @@ void ata_flash_pccard_device::device_reset_after_children() READ16_MEMBER( ata_flash_pccard_device::read_memory ) { - return m_card->ide_controller16_pcmcia_r(space, offset, mem_mask); + if(offset <= 7) + { + return m_card->read_cs0(space, offset, mem_mask); + } + else if(offset <= 15) + { + return m_card->read_cs1(space, offset & 7, mem_mask); + } + else + { + return 0xffff; + } } WRITE16_MEMBER( ata_flash_pccard_device::write_memory ) { - m_card->ide_controller16_pcmcia_w(space, offset, data, mem_mask); + if(offset <= 7) + { + m_card->write_cs0(space, offset, data, mem_mask); + } + else if( offset <= 15) + { + m_card->write_cs1(space, offset, data & 7, mem_mask); + } } READ16_MEMBER( ata_flash_pccard_device::read_reg ) diff --git a/src/emu/machine/idectrl.c b/src/emu/machine/idectrl.c index fb30e24fa18..74b22e1bb26 100644 --- a/src/emu/machine/idectrl.c +++ b/src/emu/machine/idectrl.c @@ -42,22 +42,20 @@ #define IDE_STATUS_DRIVE_READY 0x40 #define IDE_STATUS_BUSY 0x80 -#define BANK(b, v) (((v) << 4) | (b)) +#define IDE_BANK0_DATA 0 +#define IDE_BANK0_ERROR 1 +#define IDE_BANK0_SECTOR_COUNT 2 +#define IDE_BANK0_SECTOR_NUMBER 3 +#define IDE_BANK0_CYLINDER_LSB 4 +#define IDE_BANK0_CYLINDER_MSB 5 +#define IDE_BANK0_HEAD_NUMBER 6 +#define IDE_BANK0_STATUS_COMMAND 7 -#define IDE_BANK0_DATA BANK(0, 0) -#define IDE_BANK0_ERROR BANK(0, 1) -#define IDE_BANK0_SECTOR_COUNT BANK(0, 2) -#define IDE_BANK0_SECTOR_NUMBER BANK(0, 3) -#define IDE_BANK0_CYLINDER_LSB BANK(0, 4) -#define IDE_BANK0_CYLINDER_MSB BANK(0, 5) -#define IDE_BANK0_HEAD_NUMBER BANK(0, 6) -#define IDE_BANK0_STATUS_COMMAND BANK(0, 7) +#define IDE_BANK1_STATUS_CONTROL 6 -#define IDE_BANK1_STATUS_CONTROL BANK(1, 6) - -#define IDE_BANK2_CONFIG_UNK BANK(2, 4) -#define IDE_BANK2_CONFIG_REGISTER BANK(2, 8) -#define IDE_BANK2_CONFIG_DATA BANK(2, 0xc) +#define IDE_BANK2_CONFIG_UNK 4 +#define IDE_BANK2_CONFIG_REGISTER 8 +#define IDE_BANK2_CONFIG_DATA 0xc #define IDE_COMMAND_READ_MULTIPLE 0x20 #define IDE_COMMAND_READ_MULTIPLE_NORETRY 0x21 @@ -226,20 +224,6 @@ INLINE int convert_to_offset_and_size32(offs_t *offset, UINT32 mem_mask) return size; } -INLINE int convert_to_offset_and_size16(offs_t *offset, UINT32 mem_mask) -{ - int size = 2; - - /* determine which real offset */ - if (!ACCESSING_BITS_0_7) - (*offset)++, size = 1; - - if (ACCESSING_BITS_8_15) - return size; - size--; - return size; -} - /************************************* @@ -968,14 +952,61 @@ void ide_controller_device::handle_command(UINT8 _command) * *************************************/ -UINT32 ide_controller_device::ide_controller_read(int bank, offs_t offset, int size) +READ8_MEMBER( ide_controller_device::read_via_config ) { - UINT32 result = 0; + UINT16 result = 0; + + /* logit */ + LOG(("%s:IDE via config read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask)); + + switch(offset) + { + /* unknown config register */ + case IDE_BANK2_CONFIG_UNK: + result = config_unknown; + break; + + /* active config register */ + case IDE_BANK2_CONFIG_REGISTER: + result = config_register_num; + break; + + /* data from active config register */ + case IDE_BANK2_CONFIG_DATA: + if (config_register_num < IDE_CONFIG_REGISTERS) + result = config_register[config_register_num]; + break; + + default: + logerror("%s:unknown IDE via config read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask); + break; + } + +// printf( "read via config %04x %04x %04x\n", offset, result, mem_mask ); + return result; +} + +READ16_MEMBER( ide_controller_device::read_cs0_pc ) +{ + if (mem_mask == 0xffff && offset == 1 ) offset = 0; // hack for 32 bit read of data register + if (mem_mask == 0xff00) + { + return read_cs0(space, (offset * 2) + 1, 0xff) << 8; + } + else + { + return read_cs0(space, offset * 2, mem_mask); + } +} + +READ16_MEMBER( ide_controller_device::read_cs0 ) +{ + UINT16 result = 0; ide_device_interface *dev = slot[cur_drive]->dev(); /* logit */ -// if (BANK(bank, offset) != IDE_BANK0_DATA && BANK(bank, offset) != IDE_BANK0_STATUS_COMMAND && BANK(bank, offset) != IDE_BANK1_STATUS_CONTROL) - LOG(("%s:IDE read at %d:%X, size=%d\n", machine().describe_context(), bank, offset, size)); +// if (offset != IDE_BANK0_DATA && offset != IDE_BANK0_STATUS_COMMAND) + LOG(("%s:IDE cs0 read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask)); if (dev != NULL) { @@ -993,35 +1024,16 @@ UINT32 ide_controller_device::ide_controller_read(int bank, offs_t offset, int s return status; } - switch (BANK(bank, offset)) + switch (offset) { - /* unknown config register */ - case IDE_BANK2_CONFIG_UNK: - return config_unknown; - - /* active config register */ - case IDE_BANK2_CONFIG_REGISTER: - return config_register_num; - - /* data from active config register */ - case IDE_BANK2_CONFIG_DATA: - if (config_register_num < IDE_CONFIG_REGISTERS) - return config_register[config_register_num]; - return 0; - /* read data if there's data to be read */ case IDE_BANK0_DATA: if (status & IDE_STATUS_BUFFER_READY) { /* fetch the correct amount of data */ result = buffer[buffer_offset++]; - if (size > 1) + if (mem_mask == 0xffff) result |= buffer[buffer_offset++] << 8; - if (size > 2) - { - result |= buffer[buffer_offset++] << 16; - result |= buffer[buffer_offset++] << 24; - } /* if we're at the end of the buffer, handle it */ if (buffer_offset >= IDE_DISK_SECTOR_SIZE) @@ -1035,83 +1047,135 @@ UINT32 ide_controller_device::ide_controller_read(int bank, offs_t offset, int s /* return the current error */ case IDE_BANK0_ERROR: - return error; + result = error; + break; /* return the current sector count */ case IDE_BANK0_SECTOR_COUNT: - return sector_count; + result = sector_count; + break; /* return the current sector */ case IDE_BANK0_SECTOR_NUMBER: - return dev->cur_sector; + result = dev->cur_sector; + break; /* return the current cylinder LSB */ case IDE_BANK0_CYLINDER_LSB: - return dev->cur_cylinder & 0xff; + result = dev->cur_cylinder & 0xff; + break; /* return the current cylinder MSB */ case IDE_BANK0_CYLINDER_MSB: - return dev->cur_cylinder >> 8; + result = dev->cur_cylinder >> 8; + break; /* return the current head */ case IDE_BANK0_HEAD_NUMBER: - return dev->cur_head_reg; + result = dev->cur_head_reg; + break; /* return the current status and clear any pending interrupts */ case IDE_BANK0_STATUS_COMMAND: - /* return the current status but don't clear interrupts */ - case IDE_BANK1_STATUS_CONTROL: result = status; if (last_status_timer->elapsed() > TIME_PER_ROTATION) { result |= IDE_STATUS_HIT_INDEX; last_status_timer->adjust(attotime::never); } + if (interrupt_pending) + clear_interrupt(); + break; + + /* log anything else */ + default: + logerror("%s:unknown IDE cs0 read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask); + break; + } + +// printf( "read cs0 %04x %04x %04x\n", offset, result, mem_mask ); + + /* return the result */ + return result; +} + + +READ16_MEMBER( ide_controller_device::read_cs1_pc ) +{ + if (mem_mask == 0xff00) + { + return read_cs1(space, (offset * 2) + 1, 0xff) << 8; + } + else + { + return read_cs1(space, offset * 2, mem_mask); + } +} + +READ16_MEMBER( ide_controller_device::read_cs1 ) +{ + UINT16 result = 0; + ide_device_interface *dev = slot[cur_drive]->dev(); + + if (dev != NULL) + { + if (dev->is_ready()) { + status |= IDE_STATUS_DRIVE_READY; + } else { + status &= ~IDE_STATUS_DRIVE_READY; + } + } + else + { + /* even a do-nothing operation should take a little time */ + + status ^= IDE_STATUS_BUSY; + return status; + } + + /* logit */ +// if (offset != IDE_BANK1_STATUS_CONTROL) + LOG(("%s:IDE cs1 read at %X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask)); + /* return the current status but don't clear interrupts */ - /* clear interrutps only when reading the real status */ - if (BANK(bank, offset) == IDE_BANK0_STATUS_COMMAND) + switch (offset) + { + case IDE_BANK1_STATUS_CONTROL: + result = status; + if (last_status_timer->elapsed() > TIME_PER_ROTATION) { - if (interrupt_pending) - clear_interrupt(); + result |= IDE_STATUS_HIT_INDEX; + last_status_timer->adjust(attotime::never); } break; /* log anything else */ default: - logerror("%s:unknown IDE read at %03X, size=%d\n", machine().describe_context(), offset, size); + logerror("%s:unknown IDE cs1 read at %03X, mem_mask=%d\n", machine().describe_context(), offset, mem_mask); break; } +// printf( "read cs1 %04x %04x %04x\n", offset, result, mem_mask ); + /* return the result */ return result; } - /************************************* * * IDE controller write * *************************************/ -void ide_controller_device::ide_controller_write(int bank, offs_t offset, int size, UINT32 data) +WRITE8_MEMBER( ide_controller_device::write_via_config ) { - switch (BANK(bank, offset)) - { - case IDE_BANK0_HEAD_NUMBER: - cur_drive = (data & 0x10) >> 4; - break; - } - - ide_device_interface *dev = slot[cur_drive]->dev(); - if (dev == NULL) - return; +// printf( "write via config %04x %04x %04x\n", offset, data, mem_mask ); /* logit */ - if (BANK(bank, offset) != IDE_BANK0_DATA) - LOG(("%s:IDE write to %d:%X = %08X, size=%d\n", machine().describe_context(), bank, offset, data, size)); - // fprintf(stderr, "ide write %03x %02x size=%d\n", offset, data, size); - switch (BANK(bank, offset)) + LOG(("%s:IDE via config write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask)); + + switch (offset) { /* unknown config register */ case IDE_BANK2_CONFIG_UNK: @@ -1128,20 +1192,51 @@ void ide_controller_device::ide_controller_write(int bank, offs_t offset, int si if (config_register_num < IDE_CONFIG_REGISTERS) config_register[config_register_num] = data; break; + } +} + +WRITE16_MEMBER( ide_controller_device::write_cs0_pc ) +{ + if (mem_mask == 0xffff && offset == 1 ) offset = 0; // hack for 32 bit write to data register + if (mem_mask == 0xff00) + { + return write_cs0(space, (offset * 2) + 1, data >> 8, 0xff); + } + else + { + return write_cs0(space, offset * 2, data, mem_mask); + } +} + +WRITE16_MEMBER( ide_controller_device::write_cs0 ) +{ +// printf( "write cs0 %04x %04x %04x\n", offset, data, mem_mask ); + switch (offset) + { + case IDE_BANK0_HEAD_NUMBER: + cur_drive = (data & 0x10) >> 4; + break; + } + + ide_device_interface *dev = slot[cur_drive]->dev(); + if (dev == NULL) + return; + + /* logit */ + if (offset != IDE_BANK0_DATA) + LOG(("%s:IDE cs0 write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask)); + // fprintf(stderr, "ide write %03x %02x mem_mask=%d\n", offset, data, size); + switch (offset) + { /* write data */ case IDE_BANK0_DATA: if (status & IDE_STATUS_BUFFER_READY) { /* store the correct amount of data */ buffer[buffer_offset++] = data; - if (size > 1) + if (mem_mask == 0xffff) buffer[buffer_offset++] = data >> 8; - if (size > 2) - { - buffer[buffer_offset++] = data >> 16; - buffer[buffer_offset++] = data >> 24; - } /* if we're at the end of the buffer, handle it */ if (buffer_offset >= IDE_DISK_SECTOR_SIZE) @@ -1245,7 +1340,30 @@ void ide_controller_device::ide_controller_write(int bank, offs_t offset, int si case IDE_BANK0_STATUS_COMMAND: handle_command(data); break; + } +} + +WRITE16_MEMBER( ide_controller_device::write_cs1_pc ) +{ + if (mem_mask == 0xff00) + { + return write_cs1(space, (offset * 2) + 1, data >> 8, 0xff); + } + else + { + return write_cs1(space, offset * 2, data, mem_mask); + } +} + +WRITE16_MEMBER( ide_controller_device::write_cs1 ) +{ +// printf( "write cs1 %04x %04x %04x\n", offset, data, mem_mask ); + + /* logit */ + LOG(("%s:IDE cs1 write to %X = %08X, mem_mask=%d\n", machine().describe_context(), offset, data, mem_mask)); + switch (offset) + { /* adapter control */ case IDE_BANK1_STATUS_CONTROL: adapter_control = data; @@ -1263,7 +1381,6 @@ void ide_controller_device::ide_controller_write(int bank, offs_t offset, int si } - /************************************* * * Bus master read @@ -1354,126 +1471,6 @@ void ide_controller_device::ide_bus_master_write(offs_t offset, int size, UINT32 bus_master_descriptor = data & 0xfffffffc; } - - -/************************************* - * - * IDE direct handlers (16-bit) - * - *************************************/ - -/* - ide_bus_r() - - Read a 16-bit word from the IDE bus directly. - - select: 0->CS1Fx active, 1->CS3Fx active - offset: register offset (state of DA2-DA0) -*/ -int ide_controller_device::ide_bus_r(int select, int offset) -{ - return ide_controller_read(select ? 1 : 0, offset, select == 0 && offset == 0 ? 2 : 1); -} - -/* - ide_bus_w() - - Write a 16-bit word to the IDE bus directly. - - select: 0->CS1Fx active, 1->CS3Fx active - offset: register offset (state of DA2-DA0) - data: data written (state of D0-D15 or D0-D7) -*/ -void ide_controller_device::ide_bus_w(int select, int offset, int data) -{ - if (select == 0 && offset == 0) - ide_controller_write(0, 0, 2, data); - else - ide_controller_write(select ? 1 : 0, offset, 1, data & 0xff); -} - -UINT32 ide_controller_device::ide_controller_r(int reg, int size) -{ - if (reg >= 0x1f0 && reg < 0x1f8) - return ide_controller_read(0, reg & 7, size); - if (reg >= 0x3f0 && reg < 0x3f8) - return ide_controller_read(1, reg & 7, size); - if (reg >= 0x030 && reg < 0x040) - return ide_controller_read(2, reg & 0xf, size); - return 0xffffffff; -} - -void ide_controller_device::ide_controller_w(int reg, int size, UINT32 data) -{ - if (reg >= 0x1f0 && reg < 0x1f8) - ide_controller_write(0, reg & 7, size, data); - if (reg >= 0x3f0 && reg < 0x3f8) - ide_controller_write(1, reg & 7, size, data); - if (reg >= 0x030 && reg < 0x040) - ide_controller_write(2, reg & 0xf, size, data); -} - - -/************************************* - * - * 32-bit IDE handlers - * - *************************************/ - -READ32_MEMBER( ide_controller_device::ide_controller32_r ) -{ - int size; - - offset *= 4; - size = convert_to_offset_and_size32(&offset, mem_mask); - - return ide_controller_r(offset, size) << ((offset & 3) * 8); -} - - -WRITE32_MEMBER( ide_controller_device::ide_controller32_w ) -{ - int size; - - offset *= 4; - size = convert_to_offset_and_size32(&offset, mem_mask); - data = data >> ((offset & 3) * 8); - - ide_controller_w(offset, size, data); -} - - -READ16_MEMBER( ide_controller_device::ide_controller16_pcmcia_r ) -{ - int size; - UINT32 res = 0xffff; - - offset *= 2; - size = convert_to_offset_and_size16(&offset, mem_mask); - - if (offset < 0x008) - res = ide_controller_read(0, offset & 7, size); - if (offset >= 0x008 && offset < 0x010) - res = ide_controller_read(1, offset & 7, size); - - return res << ((offset & 1) * 8); -} - - -WRITE16_MEMBER( ide_controller_device::ide_controller16_pcmcia_w ) -{ - int size; - - offset *= 2; - size = convert_to_offset_and_size16(&offset, mem_mask); - data = data >> ((offset & 1) * 8); - - if (offset < 0x008) - ide_controller_write(0, offset & 7, size, data); - if (offset >= 0x008 && offset < 0x010) - ide_controller_write(1, offset & 7, size, data); -} - READ32_MEMBER( ide_controller_device::ide_bus_master32_r ) { int size; @@ -1496,34 +1493,6 @@ WRITE32_MEMBER( ide_controller_device::ide_bus_master32_w ) } - -/************************************* - * - * 16-bit IDE handlers - * - *************************************/ - -READ16_MEMBER( ide_controller_device::ide_controller16_r ) -{ - int size; - - offset *= 2; - size = convert_to_offset_and_size16(&offset, mem_mask); - - return ide_controller_r(offset, size) << ((offset & 1) * 8); -} - - -WRITE16_MEMBER( ide_controller_device::ide_controller16_w ) -{ - int size; - - offset *= 2; - size = convert_to_offset_and_size16(&offset, mem_mask); - - ide_controller_w(offset, size, data >> ((offset & 1) * 8)); -} - SLOT_INTERFACE_START(ide_devices) SLOT_INTERFACE("hdd", IDE_HARDDISK) SLOT_INTERFACE_END diff --git a/src/emu/machine/idectrl.h b/src/emu/machine/idectrl.h index 016d3854637..91bf0cca397 100644 --- a/src/emu/machine/idectrl.h +++ b/src/emu/machine/idectrl.h @@ -90,24 +90,21 @@ public: void ide_set_master_password(const UINT8 *password); void ide_set_user_password(const UINT8 *password); - int ide_bus_r(int select, int offset); - void ide_bus_w(int select, int offset, int data); - - UINT32 ide_controller_r(int reg, int size); - void ide_controller_w(int reg, int size, UINT32 data); - - DECLARE_READ32_MEMBER( ide_controller32_r ); - DECLARE_WRITE32_MEMBER( ide_controller32_w ); - DECLARE_READ16_MEMBER( ide_controller16_pcmcia_r ); - DECLARE_WRITE16_MEMBER( ide_controller16_pcmcia_w ); + DECLARE_READ8_MEMBER(read_via_config); + DECLARE_WRITE8_MEMBER(write_via_config); + DECLARE_READ16_MEMBER(read_cs0); + DECLARE_READ16_MEMBER(read_cs1); + DECLARE_WRITE16_MEMBER(write_cs0); + DECLARE_WRITE16_MEMBER(write_cs1); + + DECLARE_READ16_MEMBER(read_cs0_pc); + DECLARE_READ16_MEMBER(read_cs1_pc); + DECLARE_WRITE16_MEMBER(write_cs0_pc); + DECLARE_WRITE16_MEMBER(write_cs1_pc); + DECLARE_READ32_MEMBER( ide_bus_master32_r ); DECLARE_WRITE32_MEMBER( ide_bus_master32_w ); - DECLARE_READ16_MEMBER( ide_controller16_r ); - DECLARE_WRITE16_MEMBER( ide_controller16_w ); - - UINT32 ide_controller_read(int bank, offs_t offset, int size); - void ide_controller_write(int bank, offs_t offset, int size, UINT32 data); UINT32 ide_bus_master_read(offs_t offset, int size); void ide_bus_master_write(offs_t offset, int size, UINT32 data); void signal_interrupt(); diff --git a/src/emu/machine/rf5c296.c b/src/emu/machine/rf5c296.c index dccf32d0d61..6e303c1812a 100644 --- a/src/emu/machine/rf5c296.c +++ b/src/emu/machine/rf5c296.c @@ -41,40 +41,61 @@ UINT8 rf5c296_device::reg_r(ATTR_UNUSED UINT8 reg) WRITE16_MEMBER(rf5c296_device::io_w) { - if(offset < 4) + /// TODO: find out if this should be done here. + offset *= 2; + if (mem_mask == 0xff00) { - m_pccard->write_memory(space, offset, data, mem_mask); + mem_mask >>= 8; + data >>= 8; + offset++; } - if(offset == 0x3e0/2) + switch(offset) { - if(ACCESSING_BITS_0_7) - m_rf5c296_reg = data; - if(ACCESSING_BITS_8_15) - reg_w(m_rf5c296_reg, data >> 8); + case 0x3e0: + m_rf5c296_reg = data; + break; + + case 0x3e1: + reg_w(m_rf5c296_reg, data); + break; + + default: + m_pccard->write_memory(space, offset, data, mem_mask); + break; } } READ16_MEMBER(rf5c296_device::io_r) { - if(offset < 4) + /// TODO: find out if this should be done here. + offset *= 2; + int shift = 0; + if (mem_mask == 0xff00) { - return m_pccard->read_memory(space, offset, mem_mask); + shift = 8; + mem_mask >>= 8; + offset++; } - offset *= 2; + UINT16 data; - if(offset == 0x3e0/2) + switch( offset ) { - UINT32 res = 0x0000; - if(ACCESSING_BITS_0_7) - res |= m_rf5c296_reg; - if(ACCESSING_BITS_8_15) - res |= reg_r(m_rf5c296_reg) << 8; - return res; + case 0x3e0: + data = m_rf5c296_reg; + break; + + case 0x3e1: + data = reg_r(m_rf5c296_reg); + break; + + default: + data = m_pccard->read_memory(space, offset, mem_mask); + break; } - return 0xffff; + return data << shift; } // Hardcoded to reach the pcmcia CIS diff --git a/src/mame/drivers/calchase.c b/src/mame/drivers/calchase.c index e7b71cdc135..6570dbd5ce0 100644 --- a/src/mame/drivers/calchase.c +++ b/src/mame/drivers/calchase.c @@ -127,9 +127,9 @@ public: calchase_state(const machine_config &mconfig, device_type type, const char *tag) : pcat_base_state(mconfig, type, tag), m_dac_l(*this, "dac_l"), - m_dac_r(*this, "dac_r"), - m_ide(*this, "ide") - { } + m_dac_r(*this, "dac_r") + { + } UINT32 *m_bios_ram; UINT32 *m_bios_ext_ram; @@ -149,16 +149,11 @@ public: DECLARE_WRITE16_MEMBER(calchase_dac_l_w); DECLARE_WRITE16_MEMBER(calchase_dac_r_w); DECLARE_DRIVER_INIT(calchase); - DECLARE_READ32_MEMBER(ide_r); - DECLARE_WRITE32_MEMBER(ide_w); - DECLARE_READ32_MEMBER(fdc_r); - DECLARE_WRITE32_MEMBER(fdc_w); virtual void machine_start(); virtual void machine_reset(); void intel82439tx_init(); required_device<dac_device> m_dac_l; required_device<dac_device> m_dac_r; - required_device<ide_controller_device> m_ide; }; // Intel 82439TX System Controller (MXTC) @@ -374,27 +369,6 @@ WRITE16_MEMBER(calchase_state::calchase_dac_r_w) m_dac_r->write_unsigned16((data & 0xfff) << 4); } -READ32_MEMBER(calchase_state::ide_r) -{ - return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(calchase_state::ide_w) -{ - m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask); -} - -READ32_MEMBER(calchase_state::fdc_r) -{ - return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(calchase_state::fdc_w) -{ - //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask); - m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask); -} - static ADDRESS_MAP_START( calchase_map, AS_PROGRAM, 32, calchase_state ) AM_RANGE(0x00000000, 0x0009ffff) AM_RAM AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", trident_vga_device, mem_r, mem_w, 0xffffffff) // VGA VRAM @@ -435,7 +409,7 @@ static ADDRESS_MAP_START( calchase_io, AS_IO, 32, calchase_state ) //AM_RANGE(0x00e8, 0x00eb) AM_NOP AM_RANGE(0x00e8, 0x00ef) AM_NOP //AMI BIOS write to this ports as delays between I/O ports operations sending al value -> NEWIODELAY AM_RANGE(0x0170, 0x0177) AM_NOP //To debug - AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x0200, 0x021f) AM_NOP //To debug AM_RANGE(0x0260, 0x026f) AM_NOP //To debug AM_RANGE(0x0278, 0x027b) AM_WRITENOP//AM_WRITE(pnp_config_w) @@ -454,7 +428,7 @@ static ADDRESS_MAP_START( calchase_io, AS_IO, 32, calchase_state ) AM_RANGE(0x0378, 0x037f) AM_NOP //To debug // AM_RANGE(0x0300, 0x03af) AM_NOP // AM_RANGE(0x03b0, 0x03df) AM_NOP - AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w) + AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) AM_RANGE(0x03f8, 0x03ff) AM_NOP // To debug Serial Port COM1: AM_RANGE(0x0a78, 0x0a7b) AM_WRITENOP//AM_WRITE(pnp_data_w) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) diff --git a/src/mame/drivers/chihiro.c b/src/mame/drivers/chihiro.c index 89a594fc865..6a532e491eb 100644 --- a/src/mame/drivers/chihiro.c +++ b/src/mame/drivers/chihiro.c @@ -394,8 +394,6 @@ public: DECLARE_WRITE32_MEMBER( geforce_w ); DECLARE_READ32_MEMBER( usbctrl_r ); DECLARE_WRITE32_MEMBER( usbctrl_w ); - DECLARE_READ32_MEMBER( ide_r ); - DECLARE_WRITE32_MEMBER( ide_w ); DECLARE_READ32_MEMBER( smbus_r ); DECLARE_WRITE32_MEMBER( smbus_w ); DECLARE_READ32_MEMBER( dummy_r ); @@ -2648,58 +2646,6 @@ WRITE32_MEMBER( chihiro_state::dummy_w ) { } -/* - * IDE - */ - -INLINE int convert_to_offset_and_size32(offs_t *offset, UINT32 mem_mask) -{ - int size = 4; - - /* determine which real offset */ - if (!ACCESSING_BITS_0_7) - { - (*offset)++, size = 3; - if (!ACCESSING_BITS_8_15) - { - (*offset)++, size = 2; - if (!ACCESSING_BITS_16_23) - (*offset)++, size = 1; - } - } - - /* determine the real size */ - if (ACCESSING_BITS_24_31) - return size; - size--; - if (ACCESSING_BITS_16_23) - return size; - size--; - if (ACCESSING_BITS_8_15) - return size; - size--; - return size; -} - -READ32_MEMBER( chihiro_state::ide_r ) -{ - int size; - - offset *= 4; - size = convert_to_offset_and_size32(&offset, mem_mask); - return chihiro_devs.ide->ide_controller_r(offset+0x01f0, size) << ((offset & 3) * 8); -} - -WRITE32_MEMBER( chihiro_state::ide_w ) -{ - int size; - - offset *= 4; - size = convert_to_offset_and_size32(&offset, mem_mask); - data = data >> ((offset & 3) * 8); - chihiro_devs.ide->ide_controller_w(offset+0x01f0, size, data); -} - // ======================> ide_baseboard_device class ide_baseboard_device : public ide_hdd_device @@ -2999,7 +2945,7 @@ static ADDRESS_MAP_START(xbox_map_io, AS_IO, 32, chihiro_state ) AM_RANGE(0x0020, 0x0023) AM_DEVREADWRITE8("pic8259_1", pic8259_device, read, write, 0xffffffff) AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff) AM_RANGE(0x00a0, 0x00a3) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff) - AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w) AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w) diff --git a/src/mame/drivers/cobra.c b/src/mame/drivers/cobra.c index 5a4c7a418bd..1b3385cb20f 100644 --- a/src/mame/drivers/cobra.c +++ b/src/mame/drivers/cobra.c @@ -610,7 +610,8 @@ public: m_gfx_pagetable(*this, "pagetable"), m_k001604(*this, "k001604"), m_ide(*this, "ide") - { } + { + } required_device<cpu_device> m_maincpu; required_device<cpu_device> m_subcpu; @@ -638,10 +639,10 @@ public: DECLARE_WRITE32_MEMBER(sub_config_w); DECLARE_READ32_MEMBER(sub_mainbd_r); DECLARE_WRITE32_MEMBER(sub_mainbd_w); - DECLARE_READ32_MEMBER(sub_ata0_r); - DECLARE_WRITE32_MEMBER(sub_ata0_w); - DECLARE_READ32_MEMBER(sub_ata1_r); - DECLARE_WRITE32_MEMBER(sub_ata1_w); + DECLARE_READ16_MEMBER(sub_ata0_r); + DECLARE_WRITE16_MEMBER(sub_ata0_w); + DECLARE_READ16_MEMBER(sub_ata1_r); + DECLARE_WRITE16_MEMBER(sub_ata1_w); DECLARE_READ32_MEMBER(sub_psac2_r); DECLARE_WRITE32_MEMBER(sub_psac2_w); DECLARE_WRITE32_MEMBER(sub_psac_palette_w); @@ -1814,68 +1815,39 @@ WRITE32_MEMBER(cobra_state::sub_config_w) { } -READ32_MEMBER(cobra_state::sub_ata0_r) +READ16_MEMBER(cobra_state::sub_ata0_r) { - UINT32 r = 0; + mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 ); - if (ACCESSING_BITS_16_31) - { - UINT16 v = m_ide->ide_bus_r(0, (offset << 1) + 0); - r |= ((v << 8) | (v >> 8)) << 16; - } - if (ACCESSING_BITS_0_15) - { - UINT16 v = m_ide->ide_bus_r(0, (offset << 1) + 1); - r |= ((v << 8) | (v >> 8)) << 0; - } + UINT32 data = m_ide->read_cs0(space, offset, mem_mask); + data = ( data << 8 ) | ( data >> 8 ); - return r; + return data; } -WRITE32_MEMBER(cobra_state::sub_ata0_w) +WRITE16_MEMBER(cobra_state::sub_ata0_w) { - if (ACCESSING_BITS_16_31) - { - UINT16 d = ((data >> 24) & 0xff) | ((data >> 8) & 0xff00); - m_ide->ide_bus_w(0, (offset << 1) + 0, d); - } - if (ACCESSING_BITS_0_15) - { - UINT16 d = ((data >> 8) & 0xff) | ((data << 8) & 0xff00); - m_ide->ide_bus_w(0, (offset << 1) + 1, d); - } + mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 ); + data = ( data << 8 ) | ( data >> 8 ); + + m_ide->write_cs0(space, offset, data, mem_mask); } -READ32_MEMBER(cobra_state::sub_ata1_r) +READ16_MEMBER(cobra_state::sub_ata1_r) { - UINT32 r = 0; + mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 ); - if (ACCESSING_BITS_16_31) - { - UINT16 v = m_ide->ide_bus_r(1, (offset << 1) + 0); - r |= ((v << 8) | (v >> 8)) << 16; - } - if (ACCESSING_BITS_0_15) - { - UINT16 v = m_ide->ide_bus_r(1, (offset << 1) + 1); - r |= ((v << 8) | (v >> 8)) << 0; - } + UINT32 data = m_ide->read_cs1(space, offset, mem_mask); - return r; + return ( data << 8 ) | ( data >> 8 ); } -WRITE32_MEMBER(cobra_state::sub_ata1_w) +WRITE16_MEMBER(cobra_state::sub_ata1_w) { - if (ACCESSING_BITS_16_31) - { - UINT16 d = ((data >> 24) & 0xff) | ((data >> 8) & 0xff00); - m_ide->ide_bus_w(1, (offset << 1) + 0, d); - } - if (ACCESSING_BITS_0_15) - { - UINT16 d = ((data >> 8) & 0xff) | ((data << 8) & 0xff00); - m_ide->ide_bus_w(1, (offset << 1) + 1, d); - } + mem_mask = ( mem_mask << 8 ) | ( mem_mask >> 8 ); + data = ( data << 8 ) | ( data >> 8 ); + + m_ide->write_cs1(space, offset, data, mem_mask); } READ32_MEMBER(cobra_state::sub_comram_r) @@ -1983,8 +1955,8 @@ static ADDRESS_MAP_START( cobra_sub_map, AS_PROGRAM, 32, cobra_state ) AM_RANGE(0x70000000, 0x7003ffff) AM_MIRROR(0x80000000) AM_READWRITE(sub_comram_r, sub_comram_w) // Double buffered shared RAM between Main and Sub // AM_RANGE(0x78000000, 0x780000ff) AM_MIRROR(0x80000000) AM_NOP // SCSI controller (unused) AM_RANGE(0x78040000, 0x7804ffff) AM_MIRROR(0x80000000) AM_DEVREADWRITE16("rfsnd", rf5c400_device, rf5c400_r, rf5c400_w, 0xffffffff) - AM_RANGE(0x78080000, 0x7808000f) AM_MIRROR(0x80000000) AM_READWRITE(sub_ata0_r, sub_ata0_w) - AM_RANGE(0x780c0010, 0x780c001f) AM_MIRROR(0x80000000) AM_READWRITE(sub_ata1_r, sub_ata1_w) + AM_RANGE(0x78080000, 0x7808000f) AM_MIRROR(0x80000000) AM_READWRITE16(sub_ata0_r, sub_ata0_w, 0xffffffff) + AM_RANGE(0x780c0010, 0x780c001f) AM_MIRROR(0x80000000) AM_READWRITE16(sub_ata1_r, sub_ata1_w, 0xffffffff) AM_RANGE(0x78200000, 0x782000ff) AM_MIRROR(0x80000000) AM_DEVREADWRITE_LEGACY("k001604", k001604_reg_r, k001604_reg_w) // PSAC registers AM_RANGE(0x78210000, 0x78217fff) AM_MIRROR(0x80000000) AM_RAM_WRITE(sub_psac_palette_w) AM_SHARE("paletteram") // PSAC palette RAM AM_RANGE(0x78220000, 0x7823ffff) AM_MIRROR(0x80000000) AM_DEVREADWRITE_LEGACY("k001604", k001604_tile_r, k001604_tile_w) // PSAC tile RAM diff --git a/src/mame/drivers/djmain.c b/src/mame/drivers/djmain.c index 8792fc74672..fe8f1c1b34f 100644 --- a/src/mame/drivers/djmain.c +++ b/src/mame/drivers/djmain.c @@ -271,40 +271,6 @@ WRITE32_MEMBER(djmain_state::turntable_select_w) //--------- -READ32_MEMBER(djmain_state::ide_std_r) -{ - if (ACCESSING_BITS_0_7) - return m_ide->ide_controller16_r(space, 0x1f0/2 + offset, 0xff00) >> 8; - else - return m_ide->ide_controller16_r(space, 0x1f0/2 + offset, 0xffff) << 16; -} - -WRITE32_MEMBER(djmain_state::ide_std_w) -{ - if (ACCESSING_BITS_0_7) - m_ide->ide_controller16_w(space, 0x1f0/2 + offset, data << 8, 0xff00); - else - m_ide->ide_controller16_w(space, 0x1f0/2 + offset, data >> 16, 0xffff); -} - - -READ32_MEMBER(djmain_state::ide_alt_r) -{ - if (offset == 0) - return m_ide->ide_controller16_r(space, 0x3f6/2, 0x00ff) << 24; - - return 0; -} - -WRITE32_MEMBER(djmain_state::ide_alt_w) -{ - if (offset == 0 && ACCESSING_BITS_16_23) - m_ide->ide_controller16_w(space, 0x3f6/2, data >> 24, 0x00ff); -} - - -//--------- - // light/coin blocker control /* @@ -450,11 +416,11 @@ static ADDRESS_MAP_START( memory_map, AS_PROGRAM, 32, djmain_state ) AM_RANGE(0x803800, 0x803fff) AM_READ(obj_rom_r) // OBJECT ROM readthrough (for POST) AM_RANGE(0xc00000, 0xc01fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_long_r, k056832_ram_long_w) // VIDEO RAM (tilemap) (beatmania) AM_RANGE(0xc02000, 0xc02047) AM_WRITE(unknownc02000_w) // ?? - AM_RANGE(0xd00000, 0xd0000f) AM_READWRITE(ide_std_r, ide_std_w) // IDE control regs (hiphopmania) - AM_RANGE(0xd4000c, 0xd4000f) AM_READWRITE(ide_alt_r, ide_alt_w) // IDE status control reg (hiphopmania) + AM_RANGE(0xd00000, 0xd0000f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff) // IDE control regs (hiphopmania) + AM_RANGE(0xd40000, 0xd4000f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff) // IDE status control reg (hiphopmania) AM_RANGE(0xe00000, 0xe01fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_long_r, k056832_ram_long_w) // VIDEO RAM (tilemap) (hiphopmania) - AM_RANGE(0xf00000, 0xf0000f) AM_READWRITE(ide_std_r, ide_std_w) // IDE control regs (beatmania) - AM_RANGE(0xf4000c, 0xf4000f) AM_READWRITE(ide_alt_r, ide_alt_w) // IDE status control reg (beatmania) + AM_RANGE(0xf00000, 0xf0000f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff) // IDE control regs (beatmania) + AM_RANGE(0xf40000, 0xf4000f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff) // IDE status control reg (beatmania) ADDRESS_MAP_END diff --git a/src/mame/drivers/fruitpc.c b/src/mame/drivers/fruitpc.c index b25a4ed5bc6..a20d3dd7988 100644 --- a/src/mame/drivers/fruitpc.c +++ b/src/mame/drivers/fruitpc.c @@ -25,15 +25,12 @@ class fruitpc_state : public pcat_base_state public: fruitpc_state(const machine_config &mconfig, device_type type, const char *tag) : pcat_base_state(mconfig, type, tag), - m_ide(*this, "ide"), m_inp1(*this, "INP1"), m_inp2(*this, "INP2"), m_inp3(*this, "INP3"), m_inp4(*this, "INP4") { } - required_device<ide_controller_device> m_ide; - required_ioport m_inp1; required_ioport m_inp2; required_ioport m_inp3; @@ -43,10 +40,6 @@ public: DECLARE_READ8_MEMBER(fruit_inp_r); virtual void machine_start(); virtual void machine_reset(); - DECLARE_READ32_MEMBER(ide_r); - DECLARE_WRITE32_MEMBER(ide_w); - DECLARE_READ32_MEMBER(fdc_r); - DECLARE_WRITE32_MEMBER(fdc_w); }; READ8_MEMBER(fruitpc_state::fruit_inp_r) @@ -65,27 +58,6 @@ READ8_MEMBER(fruitpc_state::fruit_inp_r) return 0; } -READ32_MEMBER(fruitpc_state::ide_r) -{ - return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(fruitpc_state::ide_w) -{ - m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask); -} - -READ32_MEMBER(fruitpc_state::fdc_r) -{ - return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(fruitpc_state::fdc_w) -{ - //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask); - m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask); -} - static ADDRESS_MAP_START( fruitpc_map, AS_PROGRAM, 32, fruitpc_state ) AM_RANGE(0x00000000, 0x0009ffff) AM_RAM AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff) // VGA VRAM @@ -98,12 +70,12 @@ ADDRESS_MAP_END static ADDRESS_MAP_START( fruitpc_io, AS_IO, 32, fruitpc_state ) AM_IMPORT_FROM(pcat32_io_common) - AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x0310, 0x0313) AM_READ8(fruit_inp_r, 0xffffffff) AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff) AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff) AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff) - AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w) + AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) ADDRESS_MAP_END #define AT_KEYB_HELPER(bit, text, key1) \ diff --git a/src/mame/drivers/funkball.c b/src/mame/drivers/funkball.c index d643f169147..8105cfc09fc 100644 --- a/src/mame/drivers/funkball.c +++ b/src/mame/drivers/funkball.c @@ -125,8 +125,6 @@ public: DECLARE_READ32_MEMBER(biu_ctrl_r); DECLARE_WRITE32_MEMBER(biu_ctrl_w); DECLARE_WRITE8_MEMBER(bios_ram_w); - DECLARE_READ32_MEMBER(ide_r); - DECLARE_WRITE32_MEMBER(ide_w); DECLARE_READ32_MEMBER(fdc_r); DECLARE_WRITE32_MEMBER(fdc_w); DECLARE_READ8_MEMBER(io20_r); @@ -212,29 +210,6 @@ static void cx5510_pci_w(device_t *busdevice, device_t *device, int function, in COMBINE_DATA(state->m_cx5510_regs + (reg/4)); } -#if 0 -READ32_MEMBER(funkball_state::ide_r) -{ - return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(funkball_state::ide_w) -{ - m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask); -} - -READ32_MEMBER(funkball_state::fdc_r) -{ - return m-ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(funkball_state::fdc_w) -{ - //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask); - m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask); -} -#endif - READ8_MEMBER( funkball_state::fdc_r ) { //printf("%02x\n",offset); @@ -434,8 +409,8 @@ static ADDRESS_MAP_START(funkball_io, AS_IO, 32, funkball_state) AM_RANGE(0x0020, 0x003f) AM_READWRITE8(io20_r, io20_w, 0xffffffff) AM_RANGE(0x00e8, 0x00ef) AM_NOP -// AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w) -// AM_RANGE(0x03f0, 0x03ff) AM_READWRITE(fdc_r, fdc_w) +// AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) +// AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) AM_RANGE(0x03f0, 0x03ff) AM_READWRITE8(fdc_r,fdc_w,0xffffffff) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) diff --git a/src/mame/drivers/gamecstl.c b/src/mame/drivers/gamecstl.c index 0038bf7892c..5c05c06a0cf 100644 --- a/src/mame/drivers/gamecstl.c +++ b/src/mame/drivers/gamecstl.c @@ -75,10 +75,8 @@ class gamecstl_state : public pcat_base_state public: gamecstl_state(const machine_config &mconfig, device_type type, const char *tag) : pcat_base_state(mconfig, type, tag), - m_ide(*this, "ide"), m_cga_ram(*this, "cga_ram") { } - required_device<ide_controller_device> m_ide; required_shared_ptr<UINT32> m_cga_ram; UINT32 *m_bios_ram; UINT8 m_mxtc_config_reg[256]; @@ -87,10 +85,6 @@ public: DECLARE_WRITE32_MEMBER(pnp_config_w); DECLARE_WRITE32_MEMBER(pnp_data_w); DECLARE_WRITE32_MEMBER(bios_ram_w); - DECLARE_READ32_MEMBER(ide_r); - DECLARE_WRITE32_MEMBER(ide_w); - DECLARE_READ32_MEMBER(fdc_r); - DECLARE_WRITE32_MEMBER(fdc_w); DECLARE_DRIVER_INIT(gamecstl); virtual void machine_start(); virtual void machine_reset(); @@ -326,29 +320,6 @@ WRITE32_MEMBER(gamecstl_state::pnp_data_w) -READ32_MEMBER(gamecstl_state::ide_r) -{ - return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(gamecstl_state::ide_w) -{ - m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask); -} - -READ32_MEMBER(gamecstl_state::fdc_r) -{ - return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(gamecstl_state::fdc_w) -{ - //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask); - m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask); -} - - - WRITE32_MEMBER(gamecstl_state::bios_ram_w) { if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled @@ -374,11 +345,11 @@ static ADDRESS_MAP_START(gamecstl_io, AS_IO, 32, gamecstl_state ) AM_IMPORT_FROM(pcat32_io_common) AM_RANGE(0x00e8, 0x00eb) AM_NOP AM_RANGE(0x00ec, 0x00ef) AM_NOP - AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x0300, 0x03af) AM_NOP AM_RANGE(0x03b0, 0x03df) AM_NOP AM_RANGE(0x0278, 0x027b) AM_WRITE(pnp_config_w) - AM_RANGE(0x03f0, 0x03ff) AM_READWRITE(fdc_r, fdc_w) + AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) ADDRESS_MAP_END diff --git a/src/mame/drivers/jaguar.c b/src/mame/drivers/jaguar.c index 4ac8979baa2..99141c522cd 100644 --- a/src/mame/drivers/jaguar.c +++ b/src/mame/drivers/jaguar.c @@ -1077,6 +1077,57 @@ static ADDRESS_MAP_START( jaguar_map, AS_PROGRAM, 16, jaguar_state ) AM_RANGE(0xf1d000, 0xf1dfff) AM_READWRITE(wave_rom_r16, wave_rom_w16 ) ADDRESS_MAP_END +/// hack for 32 big endian bus talking to 16 bit little endian ide +READ32_MEMBER(jaguar_state::vt83c461_r) +{ + UINT32 data = 0; + + if(offset >= 0x30/4 && offset < 0x40/4) + { + if (ACCESSING_BITS_0_7) + data = m_ide->read_via_config(space, (offset * 4) & 0xf, mem_mask); + } + else if( offset >= 0x1f0/4 && offset < 0x1f8/4 ) + { + if (ACCESSING_BITS_0_15) + data |= m_ide->read_cs0_pc(space, (offset * 2) & 7, mem_mask); + if (ACCESSING_BITS_16_31) + data |= m_ide->read_cs0_pc(space, ((offset * 2) & 7) + 1, mem_mask >> 16) << 16; + } + else if( offset >= 0x3f0/4 && offset < 0x3f8/4 ) + { + if (ACCESSING_BITS_0_15) + data |= m_ide->read_cs1_pc(space, (offset * 2) & 7, mem_mask); + if (ACCESSING_BITS_16_31) + data |= m_ide->read_cs1_pc(space, ((offset * 2) & 7) + 1, mem_mask >> 16) << 16; + } + + return data; +} + +WRITE32_MEMBER(jaguar_state::vt83c461_w) +{ + if(offset >= 0x30/4 && offset < 0x40/4) + { + if (ACCESSING_BITS_0_7) + m_ide->write_via_config(space, (offset * 4) & 0xf, data, mem_mask); + } + else if( offset >= 0x1f0/4 && offset < 0x1f8/4 ) + { + if (ACCESSING_BITS_0_15) + m_ide->write_cs0_pc(space, (offset * 2) & 7, data, mem_mask); + if (ACCESSING_BITS_16_31) + m_ide->write_cs0_pc(space, ((offset * 2) & 7) + 1, data >> 16, mem_mask >> 16); + } + else if( offset >= 0x3f0/4 && offset < 0x3f8/4 ) + { + if (ACCESSING_BITS_0_15) + m_ide->write_cs1_pc(space, (offset * 2) & 7, data, mem_mask); + if (ACCESSING_BITS_16_31) + m_ide->write_cs1_pc(space, ((offset * 2) & 7) + 1, data >> 16, mem_mask >> 16); + } +} + /************************************* @@ -1089,7 +1140,7 @@ static ADDRESS_MAP_START( r3000_map, AS_PROGRAM, 32, jaguar_state ) AM_RANGE(0x04000000, 0x047fffff) AM_RAM AM_SHARE("sharedram") AM_RANGE(0x04800000, 0x04bfffff) AM_ROMBANK("maingfxbank") AM_RANGE(0x04c00000, 0x04dfffff) AM_ROMBANK("mainsndbank") - AM_RANGE(0x04e00000, 0x04e003ff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w) + AM_RANGE(0x04e00000, 0x04e003ff) AM_READWRITE(vt83c461_r, vt83c461_w) AM_RANGE(0x04f00000, 0x04f003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff) AM_RANGE(0x04f00400, 0x04f007ff) AM_RAM AM_SHARE("gpuclut") AM_RANGE(0x04f02100, 0x04f021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w) @@ -1123,7 +1174,7 @@ static ADDRESS_MAP_START( m68020_map, AS_PROGRAM, 32, jaguar_state ) AM_RANGE(0xa40000, 0xa40003) AM_WRITE(eeprom_enable_w) AM_RANGE(0xb70000, 0xb70003) AM_READWRITE(misc_control_r, misc_control_w) AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK("mainsndbank") - AM_RANGE(0xe00000, 0xe003ff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w) + AM_RANGE(0xe00000, 0xe003ff) AM_READWRITE(vt83c461_r, vt83c461_w) AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff) AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE("gpuclut") AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w) @@ -1151,7 +1202,7 @@ static ADDRESS_MAP_START( gpu_map, AS_PROGRAM, 32, jaguar_state ) AM_RANGE(0x000000, 0x7fffff) AM_RAM AM_SHARE("sharedram") AM_RANGE(0x800000, 0xbfffff) AM_ROMBANK("gpugfxbank") AM_RANGE(0xc00000, 0xdfffff) AM_ROMBANK("dspsndbank") - AM_RANGE(0xe00000, 0xe003ff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w) + AM_RANGE(0xe00000, 0xe003ff) AM_READWRITE(vt83c461_r, vt83c461_w) AM_RANGE(0xf00000, 0xf003ff) AM_READWRITE16(tom_regs_r, tom_regs_w, 0xffffffff) AM_RANGE(0xf00400, 0xf007ff) AM_RAM AM_SHARE("gpuclut") AM_RANGE(0xf02100, 0xf021ff) AM_READWRITE(gpuctrl_r, gpuctrl_w) diff --git a/src/mame/drivers/kinst.c b/src/mame/drivers/kinst.c index cf414f87f31..e4350fc7072 100644 --- a/src/mame/drivers/kinst.c +++ b/src/mame/drivers/kinst.c @@ -325,25 +325,25 @@ WRITE_LINE_MEMBER(kinst_state::ide_interrupt) READ32_MEMBER(kinst_state::kinst_ide_r) { - return midway_ide_asic_r(m_ide, space, offset / 2, mem_mask); + return m_ide->read_cs0(space, offset / 2, mem_mask); } WRITE32_MEMBER(kinst_state::kinst_ide_w) { - midway_ide_asic_w(m_ide, space, offset / 2, data, mem_mask); + m_ide->write_cs0(space, offset / 2, data, mem_mask); } READ32_MEMBER(kinst_state::kinst_ide_extra_r) { - return m_ide->ide_controller32_r(space, 0x3f6/4, 0x00ff0000) >> 16; + return m_ide->read_cs1(space, 6, 0xff); } WRITE32_MEMBER(kinst_state::kinst_ide_extra_w) { - m_ide->ide_controller32_w(space, 0x3f6/4, data << 16, 0x00ff0000); + m_ide->write_cs1(space, 6, data, 0xff); } diff --git a/src/mame/drivers/mediagx.c b/src/mame/drivers/mediagx.c index 283dbc9df2a..110c141e963 100644 --- a/src/mame/drivers/mediagx.c +++ b/src/mame/drivers/mediagx.c @@ -149,10 +149,6 @@ public: DECLARE_WRITE32_MEMBER(parallel_port_w); DECLARE_READ32_MEMBER(ad1847_r); DECLARE_WRITE32_MEMBER(ad1847_w); - DECLARE_READ32_MEMBER(ide_r); - DECLARE_WRITE32_MEMBER(ide_w); - DECLARE_READ32_MEMBER(fdc_r); - DECLARE_WRITE32_MEMBER(fdc_w); DECLARE_READ8_MEMBER(io20_r); DECLARE_WRITE8_MEMBER(io20_w); DECLARE_DRIVER_INIT(a51site4); @@ -414,28 +410,6 @@ WRITE32_MEMBER(mediagx_state::disp_ctrl_w) } -READ32_MEMBER(mediagx_state::ide_r) -{ - return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(mediagx_state::ide_w) -{ - m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask); -} - -READ32_MEMBER(mediagx_state::fdc_r) -{ - return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(mediagx_state::fdc_w) -{ - m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask); -} - - - READ32_MEMBER(mediagx_state::memory_ctrl_r) { return m_memory_ctrl_reg[offset]; @@ -784,9 +758,9 @@ static ADDRESS_MAP_START(mediagx_io, AS_IO, 32, mediagx_state ) AM_IMPORT_FROM(pcat32_io_common) AM_RANGE(0x0020, 0x003f) AM_READWRITE8(io20_r, io20_w, 0xffffffff) AM_RANGE(0x00e8, 0x00eb) AM_NOP // I/O delay port - AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w) - AM_RANGE(0x03f0, 0x03ff) AM_READWRITE(fdc_r, fdc_w) + AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) AM_RANGE(0x0400, 0x04ff) AM_READWRITE(ad1847_r, ad1847_w) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) ADDRESS_MAP_END diff --git a/src/mame/drivers/midqslvr.c b/src/mame/drivers/midqslvr.c index fd1baf25230..a875f67a5bd 100644 --- a/src/mame/drivers/midqslvr.c +++ b/src/mame/drivers/midqslvr.c @@ -34,11 +34,9 @@ class midqslvr_state : public pcat_base_state { public: midqslvr_state(const machine_config &mconfig, device_type type, const char *tag) - : pcat_base_state(mconfig, type, tag), - m_ide(*this, "ide") - { } - - required_device<ide_controller_device> m_ide; + : pcat_base_state(mconfig, type, tag) + { + } UINT32 *m_bios_ram; UINT32 *m_bios_ext1_ram; @@ -59,10 +57,6 @@ public: DECLARE_WRITE32_MEMBER( bios_ext4_ram_w ); DECLARE_WRITE32_MEMBER( bios_ram_w ); - DECLARE_READ32_MEMBER(ide_r); - DECLARE_WRITE32_MEMBER(ide_w); - DECLARE_READ32_MEMBER(fdc_r); - DECLARE_WRITE32_MEMBER(fdc_w); virtual void machine_start(); virtual void machine_reset(); void intel82439tx_init(); @@ -360,27 +354,6 @@ WRITE32_MEMBER(midqslvr_state::bios_ram_w) } } -READ32_MEMBER(midqslvr_state::ide_r) -{ - return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(midqslvr_state::ide_w) -{ - m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask); -} - -READ32_MEMBER(midqslvr_state::fdc_r) -{ - return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(midqslvr_state::fdc_w) -{ - //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask); - m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask); -} - static ADDRESS_MAP_START(midqslvr_map, AS_PROGRAM, 32, midqslvr_state) AM_RANGE(0x00000000, 0x0009ffff) AM_RAM AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff) @@ -399,11 +372,11 @@ static ADDRESS_MAP_START(midqslvr_io, AS_IO, 32, midqslvr_state) AM_IMPORT_FROM(pcat32_io_common) AM_RANGE(0x00e8, 0x00ef) AM_NOP - AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff) AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff) AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff) - AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w) + AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) ADDRESS_MAP_END diff --git a/src/mame/drivers/midvunit.c b/src/mame/drivers/midvunit.c index 04308e6b883..9bd8197d136 100644 --- a/src/mame/drivers/midvunit.c +++ b/src/mame/drivers/midvunit.c @@ -508,7 +508,7 @@ static ADDRESS_MAP_START( midvplus_map, AS_PROGRAM, 32, midvunit_state ) AM_RANGE(0x990000, 0x99000f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w) AM_RANGE(0x994000, 0x994000) AM_WRITE(midvunit_control_w) AM_RANGE(0x995020, 0x995020) AM_WRITE(midvunit_cmos_protect_w) - AM_RANGE(0x9a0000, 0x9a0007) AM_DEVREADWRITE_LEGACY("ide", midway_ide_asic_r, midway_ide_asic_w) + AM_RANGE(0x9a0000, 0x9a0007) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0x0000ffff) AM_RANGE(0x9c0000, 0x9c7fff) AM_RAM_WRITE(midvunit_paletteram_w) AM_SHARE("paletteram") AM_RANGE(0x9d0000, 0x9d000f) AM_READWRITE(midvplus_misc_r, midvplus_misc_w) AM_SHARE("midvplus_misc") AM_RANGE(0xa00000, 0xbfffff) AM_READWRITE(midvunit_textureram_r, midvunit_textureram_w) AM_SHARE("textureram") diff --git a/src/mame/drivers/photoply.c b/src/mame/drivers/photoply.c index 0a6fa7b5616..272539cd883 100644 --- a/src/mame/drivers/photoply.c +++ b/src/mame/drivers/photoply.c @@ -21,44 +21,18 @@ class photoply_state : public pcat_base_state { public: photoply_state(const machine_config &mconfig, device_type type, const char *tag) - : pcat_base_state(mconfig, type, tag), - m_ide(*this, "ide") { } + : pcat_base_state(mconfig, type, tag) + { + } UINT8 m_vga_address; - DECLARE_READ32_MEMBER(ide_r); - DECLARE_WRITE32_MEMBER(ide_w); - DECLARE_READ32_MEMBER(fdc_r); - DECLARE_WRITE32_MEMBER(fdc_w); DECLARE_DRIVER_INIT(photoply); virtual void machine_start(); - - required_device<ide_controller_device> m_ide; }; -READ32_MEMBER(photoply_state::ide_r) -{ - return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(photoply_state::ide_w) -{ - m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask); -} - -READ32_MEMBER(photoply_state::fdc_r) -{ - return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(photoply_state::fdc_w) -{ - //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask); - m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask); -} - static ADDRESS_MAP_START( photoply_map, AS_PROGRAM, 32, photoply_state ) AM_RANGE(0x00000000, 0x0009ffff) AM_RAM AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff) // VGA RAM @@ -74,14 +48,14 @@ ADDRESS_MAP_END static ADDRESS_MAP_START( photoply_io, AS_IO, 32, photoply_state ) AM_IMPORT_FROM(pcat32_io_common) AM_RANGE(0x00e8, 0x00eb) AM_NOP - AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x0278, 0x027f) AM_RAM //parallel port 2 AM_RANGE(0x0378, 0x037f) AM_RAM //parallel port //AM_RANGE(0x03bc, 0x03bf) AM_RAM //parallel port 3 AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff) AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff) AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff) - AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w) + AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) ADDRESS_MAP_END #define AT_KEYB_HELPER(bit, text, key1) \ diff --git a/src/mame/drivers/qdrmfgp.c b/src/mame/drivers/qdrmfgp.c index a4418495645..1819d424e0a 100644 --- a/src/mame/drivers/qdrmfgp.c +++ b/src/mame/drivers/qdrmfgp.c @@ -181,62 +181,25 @@ WRITE16_MEMBER(qdrmfgp_state::sndram_w) /*************/ -READ16_MEMBER(qdrmfgp_state::ide_std_r) -{ - if (offset & 0x01) - return m_ide->ide_controller16_r(space, 0x1f0/2 + offset/2, 0xff00) >> 8; - else - return m_ide->ide_controller16_r(space, 0x1f0/2 + offset/2, 0xffff); -} - -WRITE16_MEMBER(qdrmfgp_state::ide_std_w) -{ - if (offset & 0x01) - m_ide->ide_controller16_w(space, 0x1f0/2 + offset/2, data << 8, 0xff00); - else - m_ide->ide_controller16_w(space, 0x1f0/2 + offset/2, data, 0xffff); -} - -READ16_MEMBER(qdrmfgp_state::ide_alt_r) -{ - if (offset == 0) - return m_ide->ide_controller16_r(space, 0x3f6/2, 0x00ff); - - return 0; -} - -WRITE16_MEMBER(qdrmfgp_state::ide_alt_w) -{ - if (offset == 0) - m_ide->ide_controller16_w(space, 0x3f6/2, data, 0x00ff); -} - READ16_MEMBER(qdrmfgp_state::gp2_ide_std_r) { - if (offset & 0x01) + if (offset == 0x07) { - if (offset == 0x07) + switch (space.device().safe_pcbase()) { - switch (space.device().safe_pcbase()) - { - case 0xdb4c: - if ((m_workram[0x5fa4/2] - space.device().state().state_int(M68K_D0)) <= 0x10) - m_gp2_irq_control = 1; - break; - case 0xdec2: + case 0xdb4c: + if ((m_workram[0x5fa4/2] - space.device().state().state_int(M68K_D0)) <= 0x10) m_gp2_irq_control = 1; - default: - break; - } + break; + case 0xdec2: + m_gp2_irq_control = 1; + default: + break; } - - return m_ide->ide_controller16_r(space, 0x1f0/2 + offset/2, 0xff00) >> 8; - } - else - { - return m_ide->ide_controller16_r(space, 0x1f0/2 + offset/2, 0xffff); } + + return m_ide->read_cs0(space, offset, mem_mask); } @@ -328,8 +291,8 @@ static ADDRESS_MAP_START( qdrmfgp_map, AS_PROGRAM, 16, qdrmfgp_state ) AM_RANGE(0x880000, 0x881fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_word_r, k056832_ram_word_w) /* vram */ AM_RANGE(0x882000, 0x883fff) AM_DEVREADWRITE_LEGACY("k056832", k056832_ram_word_r, k056832_ram_word_w) /* vram (mirror) */ AM_RANGE(0x900000, 0x901fff) AM_READ(v_rom_r) /* gfxrom through */ - AM_RANGE(0xa00000, 0xa0000f) AM_READWRITE(ide_std_r,ide_std_w) /* IDE control regs */ - AM_RANGE(0xa4000c, 0xa4000f) AM_READWRITE(ide_alt_r,ide_alt_w) /* IDE status control reg */ + AM_RANGE(0xa00000, 0xa0000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0) /* IDE control regs */ + AM_RANGE(0xa40000, 0xa4000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs1, write_cs1) /* IDE status control reg */ AM_RANGE(0xc00000, 0xcbffff) AM_READWRITE(sndram_r, sndram_w) /* sound ram */ ADDRESS_MAP_END @@ -351,8 +314,8 @@ static ADDRESS_MAP_START( qdrmfgp2_map, AS_PROGRAM, 16, qdrmfgp_state ) AM_RANGE(0x880000, 0x881fff) AM_READWRITE(gp2_vram_r, gp2_vram_w) /* vram */ AM_RANGE(0x89f000, 0x8a0fff) AM_READWRITE(gp2_vram_mirror_r, gp2_vram_mirror_w) /* vram (mirror) */ AM_RANGE(0x900000, 0x901fff) AM_READ(v_rom_r) /* gfxrom through */ - AM_RANGE(0xa00000, 0xa0000f) AM_READ(gp2_ide_std_r) AM_WRITE(ide_std_w) /* IDE control regs */ - AM_RANGE(0xa4000c, 0xa4000f) AM_READWRITE(ide_alt_r,ide_alt_w) /* IDE status control reg */ + AM_RANGE(0xa00000, 0xa0000f) AM_READ(gp2_ide_std_r) AM_DEVWRITE("ide", ide_controller_device, write_cs0) /* IDE control regs */ + AM_RANGE(0xa40000, 0xa4000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs1, write_cs1) /* IDE status control reg */ AM_RANGE(0xc00000, 0xcbffff) AM_READWRITE(sndram_r,sndram_w) /* sound ram */ ADDRESS_MAP_END diff --git a/src/mame/drivers/quakeat.c b/src/mame/drivers/quakeat.c index c11d0f2c431..20ac096a7ee 100644 --- a/src/mame/drivers/quakeat.c +++ b/src/mame/drivers/quakeat.c @@ -92,11 +92,11 @@ ADDRESS_MAP_END static ADDRESS_MAP_START( quake_io, AS_IO, 32, quakeat_state ) AM_IMPORT_FROM(pcat32_io_common) AM_RANGE(0x00e8, 0x00eb) AM_NOP -// AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE_LEGACY("ide", ide_r, ide_w) +// AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x0300, 0x03af) AM_NOP AM_RANGE(0x03b0, 0x03df) AM_NOP // AM_RANGE(0x0278, 0x027b) AM_WRITE(pnp_config_w) -// AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE_LEGACY("ide", fdc_r, fdc_w) +// AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) // AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w) // AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_device, read, write) ADDRESS_MAP_END diff --git a/src/mame/drivers/queen.c b/src/mame/drivers/queen.c index e6b5799f02e..571b2b1d115 100644 --- a/src/mame/drivers/queen.c +++ b/src/mame/drivers/queen.c @@ -37,25 +37,18 @@ class queen_state : public pcat_base_state { public: queen_state(const machine_config &mconfig, device_type type, const char *tag) - : pcat_base_state(mconfig, type, tag), - m_ide(*this, "ide") - { } + : pcat_base_state(mconfig, type, tag) + { + } UINT32 *m_bios_ram; UINT32 *m_bios_ext_ram; UINT8 m_mxtc_config_reg[256]; UINT8 m_piix4_config_reg[4][256]; - // devices - required_device<ide_controller_device> m_ide; - DECLARE_WRITE32_MEMBER( bios_ext_ram_w ); DECLARE_WRITE32_MEMBER( bios_ram_w ); - DECLARE_READ32_MEMBER(ide_r); - DECLARE_WRITE32_MEMBER(ide_w); - DECLARE_READ32_MEMBER(fdc_r); - DECLARE_WRITE32_MEMBER(fdc_w); virtual void machine_start(); virtual void machine_reset(); void intel82439tx_init(); @@ -230,27 +223,6 @@ WRITE32_MEMBER(queen_state::bios_ram_w) } } -READ32_MEMBER(queen_state::ide_r) -{ - return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(queen_state::ide_w) -{ - m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask); -} - -READ32_MEMBER(queen_state::fdc_r) -{ - return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(queen_state::fdc_w) -{ - //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask); - m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask); -} - static ADDRESS_MAP_START( queen_map, AS_PROGRAM, 32, queen_state ) AM_RANGE(0x00000000, 0x0009ffff) AM_RAM AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff) @@ -264,11 +236,11 @@ static ADDRESS_MAP_START( queen_io, AS_IO, 32, queen_state ) AM_IMPORT_FROM(pcat32_io_common) AM_RANGE(0x00e8, 0x00ef) AM_NOP - AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff) AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff) AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff) - AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w) + AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) ADDRESS_MAP_END diff --git a/src/mame/drivers/savquest.c b/src/mame/drivers/savquest.c index 6f7fe9889fe..19cf3b8026b 100644 --- a/src/mame/drivers/savquest.c +++ b/src/mame/drivers/savquest.c @@ -40,9 +40,9 @@ class savquest_state : public pcat_base_state { public: savquest_state(const machine_config &mconfig, device_type type, const char *tag) - : pcat_base_state(mconfig, type, tag), - m_ide(*this, "ide") - { } + : pcat_base_state(mconfig, type, tag) + { + } UINT32 *m_bios_f0000_ram; UINT32 *m_bios_e0000_ram; @@ -67,9 +67,6 @@ public: UINT8 m_mxtc_config_reg[256]; UINT8 m_piix4_config_reg[8][256]; - // devices - required_device<ide_controller_device> m_ide; - DECLARE_WRITE32_MEMBER( bios_f0000_ram_w ); DECLARE_WRITE32_MEMBER( bios_e0000_ram_w ); DECLARE_WRITE32_MEMBER( bios_e4000_ram_w ); @@ -85,10 +82,6 @@ protected: // driver_device overrides // virtual void video_start(); public: - DECLARE_READ32_MEMBER(ide_r); - DECLARE_WRITE32_MEMBER(ide_w); - DECLARE_READ32_MEMBER(fdc_r); - DECLARE_WRITE32_MEMBER(fdc_w); virtual void machine_start(); virtual void machine_reset(); void intel82439tx_init(); @@ -535,27 +528,6 @@ WRITE32_MEMBER(savquest_state::parallel_port_w) } } -READ32_MEMBER(savquest_state::ide_r) -{ - return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(savquest_state::ide_w) -{ - m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask); -} - -READ32_MEMBER(savquest_state::fdc_r) -{ - return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(savquest_state::fdc_w) -{ - //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask); - m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask); -} - static ADDRESS_MAP_START(savquest_map, AS_PROGRAM, 32, savquest_state) AM_RANGE(0x00000000, 0x0009ffff) AM_RAM AM_RANGE(0x000a0000, 0x000bffff) AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff) @@ -575,12 +547,12 @@ static ADDRESS_MAP_START(savquest_io, AS_IO, 32, savquest_state) AM_RANGE(0x00e8, 0x00ef) AM_NOP - AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w) AM_RANGE(0x03b0, 0x03bf) AM_DEVREADWRITE8("vga", vga_device, port_03b0_r, port_03b0_w, 0xffffffff) AM_RANGE(0x03c0, 0x03cf) AM_DEVREADWRITE8("vga", vga_device, port_03c0_r, port_03c0_w, 0xffffffff) AM_RANGE(0x03d0, 0x03df) AM_DEVREADWRITE8("vga", vga_device, port_03d0_r, port_03d0_w, 0xffffffff) - AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w) + AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) diff --git a/src/mame/drivers/seattle.c b/src/mame/drivers/seattle.c index a20a0a3e699..89190f2aeda 100644 --- a/src/mame/drivers/seattle.c +++ b/src/mame/drivers/seattle.c @@ -482,7 +482,7 @@ public: DECLARE_WRITE32_MEMBER(ethernet_w); DECLARE_READ32_MEMBER(widget_r); DECLARE_WRITE32_MEMBER(widget_w); - DECLARE_READ32_MEMBER(seattle_ide_r); + DECLARE_READ16_MEMBER(seattle_ide_r); DECLARE_WRITE_LINE_MEMBER(ide_interrupt); DECLARE_WRITE_LINE_MEMBER(vblank_assert); DECLARE_WRITE_LINE_MEMBER(voodoo_stall); @@ -1773,19 +1773,20 @@ PCI Mem = 08000000-09FFFFFF */ -READ32_MEMBER(seattle_state::seattle_ide_r) +READ16_MEMBER(seattle_state::seattle_ide_r) { /* note that blitz times out if we don't have this cycle stealing */ - if (offset == 0x3f6/4) + if (offset == 6/2) m_maincpu->eat_cycles(100); - return m_ide->ide_controller32_r(space, offset, mem_mask); + return m_ide->read_cs1_pc(space, offset, mem_mask); } static ADDRESS_MAP_START( seattle_map, AS_PROGRAM, 32, seattle_state ) ADDRESS_MAP_UNMAP_HIGH AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rambase") // wg3dh only has 4MB; sfrush, blitz99 8MB AM_RANGE(0x08000000, 0x08ffffff) AM_DEVREAD_LEGACY("voodoo", voodoo_r) AM_WRITE(seattle_voodoo_w) - AM_RANGE(0x0a000000, 0x0a0003ff) AM_READ(seattle_ide_r) AM_DEVWRITE("ide", ide_controller_device, ide_controller32_w) + AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) + AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ16(seattle_ide_r, 0xffffffff) AM_DEVWRITE16("ide", ide_controller_device, write_cs1_pc, 0xffffffff) AM_RANGE(0x0a00040c, 0x0a00040f) AM_NOP // IDE-related, but annoying AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", ide_controller_device, ide_bus_master32_r, ide_bus_master32_w) AM_RANGE(0x0c000000, 0x0c000fff) AM_READWRITE(galileo_r, galileo_w) diff --git a/src/mame/drivers/taitotz.c b/src/mame/drivers/taitotz.c index b79774bc15f..c132ea651f5 100644 --- a/src/mame/drivers/taitotz.c +++ b/src/mame/drivers/taitotz.c @@ -613,6 +613,9 @@ public: UINT8 m_rtcdata[8]; + UINT16 ide_cs0_latch_r; + UINT16 ide_cs0_latch_w; + UINT16 ide_cs1_latch_w; UINT32 m_reg105; @@ -2109,19 +2112,18 @@ WRITE8_MEMBER(taitotz_state::tlcs_rtc_w) READ8_MEMBER(taitotz_state::tlcs_ide0_r) { - static UINT16 ide_reg_latch; int reg = offset >> 1; if (reg == 0) { if ((offset & 1) == 0) { - ide_reg_latch = m_ide->ide_bus_r(0, reg); - return (ide_reg_latch & 0xff); + ide_cs0_latch_r = m_ide->read_cs0(space, reg, 0xffff); + return (ide_cs0_latch_r & 0xff); } else { - return (ide_reg_latch >> 8) & 0xff; + return (ide_cs0_latch_r >> 8) & 0xff; } } else @@ -2129,7 +2131,7 @@ READ8_MEMBER(taitotz_state::tlcs_ide0_r) if (offset & 1) fatalerror("tlcs_ide0_r: %02X, odd offset\n", offset); - UINT8 d = m_ide->ide_bus_r(0, reg); + UINT8 d = m_ide->read_cs0(space, reg, 0xff); if (reg == 7) d &= ~0x2; // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up... // The status check explicitly checks for 0x50 (drive ready, seek complete). @@ -2139,34 +2141,32 @@ READ8_MEMBER(taitotz_state::tlcs_ide0_r) WRITE8_MEMBER(taitotz_state::tlcs_ide0_w) { - static UINT16 ide_reg_latch; int reg = offset >> 1; if (reg == 7 || reg == 0) { if ((offset & 1) == 0) { - ide_reg_latch &= 0xff00; - ide_reg_latch |= data; + ide_cs0_latch_w &= 0xff00; + ide_cs0_latch_w |= data; } else { - ide_reg_latch &= 0x00ff; - ide_reg_latch |= (UINT16)(data) << 8; - m_ide->ide_bus_w(0, reg, ide_reg_latch); + ide_cs0_latch_w &= 0x00ff; + ide_cs0_latch_w |= (UINT16)(data) << 8; + m_ide->write_cs0(space, reg, ide_cs0_latch_w, 0xffff); } } else { if (offset & 1) fatalerror("tlcs_ide0_w: %02X, %02X, odd offset\n", offset, data); - m_ide->ide_bus_w(0, reg, data); + m_ide->write_cs0(space, reg, data, 0xff); } } READ8_MEMBER(taitotz_state::tlcs_ide1_r) { - //static UINT16 ide_reg_latch; int reg = offset >> 1; if (reg != 6) @@ -2174,7 +2174,7 @@ READ8_MEMBER(taitotz_state::tlcs_ide1_r) if ((offset & 1) == 0) { - UINT8 d = m_ide->ide_bus_r(1, reg); + UINT8 d = m_ide->read_cs1(space, reg, 0xff); d &= ~0x2; // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up... // The status check explicitly checks for 0x50 (drive ready, seek complete). return d; @@ -2182,7 +2182,7 @@ READ8_MEMBER(taitotz_state::tlcs_ide1_r) else { //fatalerror("tlcs_ide1_r: %02X, odd offset\n", offset); - UINT8 d = m_ide->ide_bus_r(1, reg); + UINT8 d = m_ide->read_cs1(space, reg, 0xff); d &= ~0x2; return d; } @@ -2190,7 +2190,6 @@ READ8_MEMBER(taitotz_state::tlcs_ide1_r) WRITE8_MEMBER(taitotz_state::tlcs_ide1_w) { - static UINT16 ide_reg_latch; int reg = offset >> 1; if (reg != 6) @@ -2198,14 +2197,14 @@ WRITE8_MEMBER(taitotz_state::tlcs_ide1_w) if ((offset & 1) == 0) { - ide_reg_latch &= 0xff00; - ide_reg_latch |= data; + ide_cs1_latch_w &= 0xff00; + ide_cs1_latch_w |= data; } else { - ide_reg_latch &= 0x00ff; - ide_reg_latch |= (UINT16)(data) << 16; - m_ide->ide_bus_w(1, reg, ide_reg_latch); + ide_cs1_latch_w &= 0x00ff; + ide_cs1_latch_w |= (UINT16)(data) << 16; + m_ide->write_cs1(space, reg, ide_cs1_latch_w, 0xffff); } } @@ -2527,23 +2526,16 @@ static INPUT_PORTS_START( pwrshovl ) INPUT_PORTS_END -static void set_ide_drive_serial_number(device_t *device, int drive, const char *serial) -{ - ide_controller_device *ide = (ide_controller_device *) device; - UINT8 *ide_features = ide->ide_get_features(drive); - - for (int i=0; i < 20; i++) - { - ide_features[10*2+(i^1)] = serial[i]; - } -} - - void taitotz_state::machine_reset() { if (m_hdd_serial_number != NULL) { - set_ide_drive_serial_number(m_ide, 0, m_hdd_serial_number); + UINT8 *ide_features = m_ide->ide_get_features(0); + + for (int i=0; i < 20; i++) + { + ide_features[10*2+(i^1)] = m_hdd_serial_number[i]; + } } } diff --git a/src/mame/drivers/twinkle.c b/src/mame/drivers/twinkle.c index a8edf8ae3e8..7a064dd6527 100644 --- a/src/mame/drivers/twinkle.c +++ b/src/mame/drivers/twinkle.c @@ -247,8 +247,7 @@ public: : driver_device(mconfig, type, tag), m_am53cf96(*this, "scsi:am53cf96"), m_maincpu(*this, "maincpu"), - m_audiocpu(*this, "audiocpu"), - m_ide(*this, "ide") + m_audiocpu(*this, "audiocpu") { } @@ -273,13 +272,10 @@ public: DECLARE_WRITE16_MEMBER(twinkle_waveram_w); DECLARE_READ16_MEMBER(shared_68k_r); DECLARE_WRITE16_MEMBER(shared_68k_w); - DECLARE_READ16_MEMBER(twinkle_ide_r); - DECLARE_WRITE16_MEMBER(twinkle_ide_w); DECLARE_WRITE_LINE_MEMBER(ide_interrupt); DECLARE_DRIVER_INIT(twinkle); required_device<cpu_device> m_maincpu; required_device<cpu_device> m_audiocpu; - required_device<ide_controller_device> m_ide; }; /* RTC */ @@ -647,23 +643,6 @@ WRITE_LINE_MEMBER(twinkle_state::ide_interrupt) } } -READ16_MEMBER(twinkle_state::twinkle_ide_r) -{ - if (offset == 0) - { - return m_ide->ide_controller_r(0x1f0 + offset, 2); - } - else - { - return m_ide->ide_controller_r(0x1f0 + offset, 1); - } -} - -WRITE16_MEMBER(twinkle_state::twinkle_ide_w) -{ - m_ide->ide_controller_w(0x1f0 + offset, 1, data); -} - /* System control register (Konami always has one) @@ -734,7 +713,7 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 16, twinkle_state ) // 250000 = write to initiate DMA? // 260000 = ??? AM_RANGE(0x280000, 0x280fff) AM_READWRITE(shared_68k_r, shared_68k_w ) - AM_RANGE(0x300000, 0x30000f) AM_READWRITE(twinkle_ide_r, twinkle_ide_w) + AM_RANGE(0x300000, 0x30000f) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0, write_cs0) // 34000E = ??? AM_RANGE(0x400000, 0x400fff) AM_DEVREADWRITE("rfsnd", rf5c400_device, rf5c400_r, rf5c400_w) AM_RANGE(0x800000, 0xffffff) AM_READWRITE(twinkle_waveram_r, twinkle_waveram_w ) // 8 MB window wave RAM diff --git a/src/mame/drivers/vegas.c b/src/mame/drivers/vegas.c index fb2d3aab409..85eadf2a329 100644 --- a/src/mame/drivers/vegas.c +++ b/src/mame/drivers/vegas.c @@ -1459,28 +1459,50 @@ static WRITE32_HANDLER( asic_fifo_w ) static READ32_DEVICE_HANDLER( ide_main_r ) { ide_controller_device *ide = (ide_controller_device *) device; - return ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask); + + UINT32 data = 0; + if (ACCESSING_BITS_0_15) + data |= ide->read_cs0_pc(space, offset * 2, mem_mask); + if (ACCESSING_BITS_16_31) + data |= ide->read_cs0_pc(space, (offset * 2) + 1, mem_mask >> 16) << 16; + + return data; } static WRITE32_DEVICE_HANDLER( ide_main_w ) { ide_controller_device *ide = (ide_controller_device *) device; - ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask); + + if (ACCESSING_BITS_0_15) + ide->write_cs0_pc(space, offset * 2, data, mem_mask); + if (ACCESSING_BITS_16_31) + ide->write_cs0_pc(space, (offset * 2) + 1, data >> 16, mem_mask >> 16); } static READ32_DEVICE_HANDLER( ide_alt_r ) { ide_controller_device *ide = (ide_controller_device *) device; - return ide->ide_controller32_r(space, 0x3f4/4 + offset, mem_mask); + + UINT32 data = 0; + if (ACCESSING_BITS_0_15) + data |= ide->read_cs1_pc(space, (4/2) + (offset * 2), mem_mask); + if (ACCESSING_BITS_16_31) + data |= ide->read_cs1_pc(space, (4/2) + (offset * 2) + 1, mem_mask >> 16) << 16; + + return data; } static WRITE32_DEVICE_HANDLER( ide_alt_w ) { ide_controller_device *ide = (ide_controller_device *) device; - ide->ide_controller32_w(space, 0x3f4/4 + offset, data, mem_mask); + + if (ACCESSING_BITS_0_15) + ide->write_cs1_pc(space, 6/2 + offset * 2, data, mem_mask); + if (ACCESSING_BITS_16_31) + ide->write_cs1_pc(space, 6/2 + (offset * 2) + 1, data >> 16, mem_mask >> 16); } diff --git a/src/mame/drivers/viper.c b/src/mame/drivers/viper.c index 6114596a87e..4e23d208e74 100644 --- a/src/mame/drivers/viper.c +++ b/src/mame/drivers/viper.c @@ -1266,7 +1266,7 @@ READ64_MEMBER(viper_state::cf_card_data_r) { case 0x8: // Duplicate Even RD Data { - r |= m_ide->ide_bus_r(0, 0) << 16; + r |= m_ide->read_cs0(space, 0, mem_mask >> 16) << 16; break; } @@ -1287,7 +1287,7 @@ WRITE64_MEMBER(viper_state::cf_card_data_w) { case 0x8: // Duplicate Even RD Data { - m_ide->ide_bus_w(0, 0, (data >> 16) & 0xffff); + m_ide->write_cs0(space, 0, data >> 16, mem_mask >> 16); break; } @@ -1318,7 +1318,7 @@ READ64_MEMBER(viper_state::cf_card_r) case 0x6: // Select Card/Head case 0x7: // Status { - r |= m_ide->ide_bus_r(0, offset & 7) << 16; + r |= m_ide->read_cs0(space, offset & 7, mem_mask >> 16) << 16; break; } @@ -1327,13 +1327,13 @@ READ64_MEMBER(viper_state::cf_card_r) case 0xd: // Duplicate Error { - r |= m_ide->ide_bus_r(0, 1) << 16; + r |= m_ide->read_cs0(space, 1, mem_mask >> 16) << 16; break; } case 0xe: // Alt Status case 0xf: // Drive Address { - r |= m_ide->ide_bus_r(1, offset & 7) << 16; + r |= m_ide->read_cs1(space, offset & 7, mem_mask >> 16) << 16; break; } @@ -1383,7 +1383,7 @@ WRITE64_MEMBER(viper_state::cf_card_w) case 0x6: // Select Card/Head case 0x7: // Command { - m_ide->ide_bus_w(0, offset & 7, (data >> 16) & 0xffff); + m_ide->write_cs0(space, offset & 7, data >> 16, mem_mask >> 16); break; } @@ -1392,13 +1392,13 @@ WRITE64_MEMBER(viper_state::cf_card_w) case 0xd: // Duplicate Features { - m_ide->ide_bus_w(0, 1, (data >> 16) & 0xffff); + m_ide->write_cs0(space, 1, data >> 16, mem_mask >> 16); break; } case 0xe: // Device Ctl case 0xf: // Reserved { - m_ide->ide_bus_w(1, offset & 7, (data >> 16) & 0xffff); + m_ide->write_cs1(space, offset & 7, data >> 16, mem_mask >> 16); break; } @@ -1424,12 +1424,12 @@ WRITE64_MEMBER(viper_state::cf_card_w) // cylinder low register is set to 0x00 // cylinder high register is set to 0x00 - m_ide->ide_bus_w(1, 6, 0x04); + m_ide->write_cs1(space, 6, 0x04, 0xff); - m_ide->ide_bus_w(0, 2, 0x01); - m_ide->ide_bus_w(0, 3, 0x01); - m_ide->ide_bus_w(0, 4, 0x00); - m_ide->ide_bus_w(0, 5, 0x00); + m_ide->write_cs0(space, 2, 0x01, 0xff); + m_ide->write_cs0(space, 3, 0x01, 0xff); + m_ide->write_cs0(space, 4, 0x00, 0xff); + m_ide->write_cs0(space, 5, 0x00, 0xff); } break; } @@ -1461,7 +1461,15 @@ READ64_MEMBER(viper_state::ata_r) { int reg = (offset >> 4) & 0x7; - r |= m_ide->ide_bus_r((offset & 0x80) ? 1 : 0, reg) << 16; + switch(offset & 0x80) + { + case 0x00: + r |= m_ide->read_cs0(space, reg, mem_mask >> 16) << 16; + break; + case 0x80: + r |= m_ide->read_cs1(space, reg, mem_mask >> 16) << 16; + break; + } } return r; @@ -1473,7 +1481,15 @@ WRITE64_MEMBER(viper_state::ata_w) { int reg = (offset >> 4) & 0x7; - m_ide->ide_bus_w((offset & 0x80) ? 1 : 0, reg, (UINT16)(data >> 16)); + switch(offset & 0x80) + { + case 0x00: + m_ide->write_cs0(space, reg, data >> 16, mem_mask >> 16); + break; + case 0x80: + m_ide->write_cs1(space, reg, data >> 16, mem_mask >> 16); + break; + } } } diff --git a/src/mame/drivers/voyager.c b/src/mame/drivers/voyager.c index fb8d0687aa2..3b8f7a5858f 100644 --- a/src/mame/drivers/voyager.c +++ b/src/mame/drivers/voyager.c @@ -24,22 +24,16 @@ class voyager_state : public pcat_base_state { public: voyager_state(const machine_config &mconfig, device_type type, const char *tag) - : pcat_base_state(mconfig, type, tag), - m_ide(*this, "ide") - { } + : pcat_base_state(mconfig, type, tag) + { + } UINT32 *m_bios_ram; UINT8 m_mxtc_config_reg[256]; UINT8 m_piix4_config_reg[4][256]; - required_device<ide_controller_device> m_ide; - UINT32 m_idle_skip_ram; DECLARE_WRITE32_MEMBER(bios_ram_w); - DECLARE_READ32_MEMBER(ide_r); - DECLARE_WRITE32_MEMBER(ide_w); - DECLARE_READ32_MEMBER(fdc_r); - DECLARE_WRITE32_MEMBER(fdc_w); DECLARE_DRIVER_INIT(voyager); virtual void machine_start(); virtual void machine_reset(); @@ -47,28 +41,6 @@ public: }; -READ32_MEMBER(voyager_state::ide_r) -{ - return m_ide->ide_controller32_r(space, 0x1f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(voyager_state::ide_w) -{ - m_ide->ide_controller32_w(space, 0x1f0/4 + offset, data, mem_mask); -} - -READ32_MEMBER(voyager_state::fdc_r) -{ - return m_ide->ide_controller32_r(space, 0x3f0/4 + offset, mem_mask); -} - -WRITE32_MEMBER(voyager_state::fdc_w) -{ - //mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask); - m_ide->ide_controller32_w(space, 0x3f0/4 + offset, data, mem_mask); -} - - // Intel 82439TX System Controller (MXTC) static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg) @@ -276,7 +248,7 @@ static ADDRESS_MAP_START( voyager_io, AS_IO, 32, voyager_state ) //AM_RANGE(0x00e8, 0x00eb) AM_NOP AM_RANGE(0x00e8, 0x00ef) AM_NOP //AMI BIOS write to this ports as delays between I/O ports operations sending al value -> NEWIODELAY AM_RANGE(0x0170, 0x0177) AM_NOP //To debug - AM_RANGE(0x01f0, 0x01f7) AM_READWRITE(ide_r, ide_w) + AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x0200, 0x021f) AM_NOP //To debug AM_RANGE(0x0260, 0x026f) AM_NOP //To debug AM_RANGE(0x0278, 0x027b) AM_WRITENOP//AM_WRITE(pnp_config_w) @@ -295,7 +267,7 @@ static ADDRESS_MAP_START( voyager_io, AS_IO, 32, voyager_state ) AM_RANGE(0x0378, 0x037f) AM_NOP //To debug // AM_RANGE(0x0300, 0x03af) AM_NOP // AM_RANGE(0x03b0, 0x03df) AM_NOP - AM_RANGE(0x03f0, 0x03f7) AM_READWRITE(fdc_r, fdc_w) + AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) AM_RANGE(0x03f8, 0x03ff) AM_NOP // To debug Serial Port COM1: AM_RANGE(0x0a78, 0x0a7b) AM_WRITENOP//AM_WRITE(pnp_data_w) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) diff --git a/src/mame/drivers/zn.c b/src/mame/drivers/zn.c index ccae218bbfb..cb306a1adff 100644 --- a/src/mame/drivers/zn.c +++ b/src/mame/drivers/zn.c @@ -82,9 +82,6 @@ public: DECLARE_WRITE8_MEMBER(coh1002m_bank_w); DECLARE_READ8_MEMBER(cbaj_sound_main_status_r); DECLARE_READ8_MEMBER(cbaj_sound_z80_status_r); - DECLARE_READ8_MEMBER(jdredd_idestat_r); - DECLARE_READ16_MEMBER(jdredd_ide_r); - DECLARE_WRITE16_MEMBER(jdredd_ide_w); DECLARE_DRIVER_INIT(coh1000ta); DECLARE_DRIVER_INIT(coh1000tb); DECLARE_DRIVER_INIT(coh1000c); @@ -109,8 +106,8 @@ protected: private: inline void ATTR_PRINTF(3,4) verboselog( int n_level, const char *s_fmt, ... ); - inline UINT8 psxreadbyte( UINT32 *p_n_psxram, UINT32 n_address ); - inline void psxwritebyte( UINT32 *p_n_psxram, UINT32 n_address, UINT8 n_data ); + inline UINT16 psxreadword( UINT32 *p_n_psxram, UINT32 n_address ); + inline void psxwriteword( UINT32 *p_n_psxram, UINT32 n_address, UINT16 n_data ); UINT8 m_n_znsecsel; @@ -147,15 +144,15 @@ inline void ATTR_PRINTF(3,4) zn_state::verboselog( int n_level, const char *s_fm } #ifdef UNUSED_FUNCTION -inline UINT8 zn_state::psxreadbyte( UINT32 *p_n_psxram, UINT32 n_address ) +inline UINT16 zn_state::psxreadword( UINT32 *p_n_psxram, UINT32 n_address ) { - return *( (UINT8 *)p_n_psxram + BYTE4_XOR_LE( n_address ) ); + return *( (UINT16 *)( (UINT8 *)p_n_psxram + WORD_XOR_LE( n_address ) ) ); } #endif -inline void zn_state::psxwritebyte( UINT32 *p_n_psxram, UINT32 n_address, UINT8 n_data ) +inline void zn_state::psxwriteword( UINT32 *p_n_psxram, UINT32 n_address, UINT16 n_data ) { - *( (UINT8 *)p_n_psxram + BYTE4_XOR_LE( n_address ) ) = n_data; + *( (UINT16 *)( (UINT8 *)p_n_psxram + WORD_XOR_LE( n_address ) ) ) = n_data; } static const UINT8 ac01[ 8 ] = { 0x80, 0x1c, 0xe2, 0xfa, 0xf9, 0xf1, 0x30, 0xc0 }; @@ -1341,15 +1338,19 @@ void zn_state::atpsx_dma_read( UINT32 *p_n_psxram, UINT32 n_address, INT32 n_siz return; } - /* dma size is in 32-bit words, convert to bytes */ - n_size <<= 2; +// printf( "%08x %08x %08x\n", n_address, n_size * 4, n_address + n_size * 4 ); + + /* dma size is in 32-bit words, convert to words */ + n_size <<= 1; address_space &space = machine().firstcpu->space(AS_PROGRAM); while( n_size > 0 ) { - psxwritebyte( p_n_psxram, n_address, m_ide->ide_controller32_r( space, 0x1f0 / 4, 0x000000ff ) ); - n_address++; + psxwriteword( p_n_psxram, n_address, m_ide->read_cs0( space, 0, 0xffff ) ); + n_address += 2; n_size--; } + +// printf( "%08x\n", n_address ); } void zn_state::atpsx_dma_write( UINT32 *p_n_psxram, UINT32 n_address, INT32 n_size ) @@ -1361,8 +1362,11 @@ static ADDRESS_MAP_START(coh1000w_map, AS_PROGRAM, 32, zn_state) AM_RANGE(0x1f000000, 0x1f1fffff) AM_ROM AM_REGION("roms", 0) AM_RANGE(0x1f000000, 0x1f000003) AM_WRITENOP AM_RANGE(0x1f7e8000, 0x1f7e8003) AM_NOP - AM_RANGE(0x1f7e4000, 0x1f7e4fff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w ) - AM_RANGE(0x1f7f4000, 0x1f7f4fff) AM_DEVREADWRITE("ide", ide_controller_device, ide_controller32_r, ide_controller32_w ) + AM_RANGE(0x1f7e4030, 0x1f7e403f) AM_DEVREADWRITE8("ide", ide_controller_device, read_via_config, write_via_config, 0xffffffff) + AM_RANGE(0x1f7e41f0, 0x1f7e41f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) + AM_RANGE(0x1f7e43f0, 0x1f7e43f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) + AM_RANGE(0x1f7f41f0, 0x1f7f41f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) + AM_RANGE(0x1f7f43f0, 0x1f7f43f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, 0xffffffff) AM_IMPORT_FROM(zn_map) ADDRESS_MAP_END @@ -1874,39 +1878,6 @@ Notes: * - Unpopulated DIP42 socket */ -READ8_MEMBER(zn_state::jdredd_idestat_r) -{ - return m_ide->ide_controller_r( 0x1f7, 1 ); -} - -READ16_MEMBER(zn_state::jdredd_ide_r) -{ - UINT16 data = 0; - - if( ACCESSING_BITS_0_7 ) - { - data |= m_ide->ide_controller_r( 0x1f0 + offset, 1 ) << 0; - } - if( ACCESSING_BITS_8_15 ) - { - data |= m_ide->ide_controller_r( 0x1f0 + offset, 1 ) << 8; - } - - return data; -} - -WRITE16_MEMBER(zn_state::jdredd_ide_w) -{ - if( ACCESSING_BITS_0_7 ) - { - m_ide->ide_controller_w( 0x1f0 + offset, 1, data >> 0 ); - } - if( ACCESSING_BITS_8_15 ) - { - m_ide->ide_controller_w( 0x1f0 + offset, 1, data >> 8 ); - } -} - CUSTOM_INPUT_MEMBER(zn_state::jdredd_gun_mux_read) { return m_jdredd_gun_mux; @@ -1988,8 +1959,8 @@ static ADDRESS_MAP_START(nbajamex_map, AS_PROGRAM, 32, zn_state) ADDRESS_MAP_END static ADDRESS_MAP_START(jdredd_map, AS_PROGRAM, 32, zn_state) - AM_RANGE(0x1fbfff8c, 0x1fbfff8f) AM_READ8(jdredd_idestat_r, 0x000000ff) AM_WRITENOP - AM_RANGE(0x1fbfff90, 0x1fbfff9f) AM_READWRITE16(jdredd_ide_r, jdredd_ide_w, 0xffffffff) + AM_RANGE(0x1fbfff80, 0x1fbfff8f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1, write_cs1, 0xffffffff) + AM_RANGE(0x1fbfff90, 0x1fbfff9f) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0, write_cs0, 0xffffffff) AM_IMPORT_FROM(coh1000a_map) ADDRESS_MAP_END diff --git a/src/mame/includes/djmain.h b/src/mame/includes/djmain.h index 550660677e7..30a9a62d5a9 100644 --- a/src/mame/includes/djmain.h +++ b/src/mame/includes/djmain.h @@ -42,10 +42,6 @@ public: DECLARE_WRITE32_MEMBER(unknown590000_w); DECLARE_WRITE32_MEMBER(unknown802000_w); DECLARE_WRITE32_MEMBER(unknownc02000_w); - DECLARE_READ32_MEMBER(ide_std_r); - DECLARE_WRITE32_MEMBER(ide_std_w); - DECLARE_READ32_MEMBER(ide_alt_r); - DECLARE_WRITE32_MEMBER(ide_alt_w); DECLARE_DRIVER_INIT(bm7thmix); DECLARE_DRIVER_INIT(bm6thmix); DECLARE_DRIVER_INIT(hmcompmx); diff --git a/src/mame/includes/jaguar.h b/src/mame/includes/jaguar.h index 505eb805c38..275939e406a 100644 --- a/src/mame/includes/jaguar.h +++ b/src/mame/includes/jaguar.h @@ -8,6 +8,7 @@ #include "machine/nvram.h" #include "sound/dac.h" #include "machine/eeprom.h" +#include "machine/idectrl.h" #include "imagedev/snapquik.h" #ifndef ENABLE_SPEEDUP_HACKS @@ -54,7 +55,10 @@ public: m_joystick_data(0), m_eeprom_bit_count(0), m_protection_check(0) , - m_eeprom(*this, "eeprom") { } + m_eeprom(*this, "eeprom"), + m_ide(*this, "ide") + { + } // devices required_device<cpu_device> m_maincpu; @@ -207,6 +211,8 @@ public: DECLARE_WRITE32_MEMBER( blitter_w ); DECLARE_READ16_MEMBER( tom_regs_r ); DECLARE_WRITE16_MEMBER( tom_regs_w ); + DECLARE_READ32_MEMBER( vt83c461_r ); + DECLARE_WRITE32_MEMBER( vt83c461_w ); DECLARE_READ32_MEMBER( cojag_gun_input_r ); UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); @@ -319,4 +325,5 @@ protected: void jaguar_nvram_load(); void jaguar_nvram_save(); optional_device<eeprom_device> m_eeprom; + optional_device<ide_controller_device> m_ide; }; diff --git a/src/mame/includes/qdrmfgp.h b/src/mame/includes/qdrmfgp.h index 651e7a2c827..d91c4a279ea 100644 --- a/src/mame/includes/qdrmfgp.h +++ b/src/mame/includes/qdrmfgp.h @@ -37,10 +37,6 @@ public: DECLARE_READ16_MEMBER(gp2_ide_std_r); DECLARE_CUSTOM_INPUT_MEMBER(inputs_r); DECLARE_CUSTOM_INPUT_MEMBER(battery_sensor_r); - DECLARE_READ16_MEMBER(ide_std_r); - DECLARE_WRITE16_MEMBER(ide_std_w); - DECLARE_READ16_MEMBER(ide_alt_r); - DECLARE_WRITE16_MEMBER(ide_alt_w); DECLARE_WRITE_LINE_MEMBER(qdrmfgp_irq3_ack_w); DECLARE_WRITE_LINE_MEMBER(qdrmfgp_irq4_ack_w); virtual void machine_reset(); diff --git a/src/mame/machine/midwayic.c b/src/mame/machine/midwayic.c index d8d101e10a8..290163d4094 100644 --- a/src/mame/machine/midwayic.c +++ b/src/mame/machine/midwayic.c @@ -1047,50 +1047,3 @@ WRITE32_HANDLER( midway_ioasic_w ) break; } } - - - -/************************************* - * - * The IDE ASIC was used on War Gods - * and Killer Instinct to map the IDE - * registers - * - *************************************/ - -READ32_DEVICE_HANDLER( midway_ide_asic_r ) -{ - /* convert to standard IDE offsets */ - offs_t ideoffs = 0x1f0/4 + (offset >> 2); - UINT8 shift = 8 * (offset & 3); - UINT32 result; - - ide_controller_device *ide = (ide_controller_device *) device; - - /* offset 0 is a special case */ - if (offset == 0) - result = ide->ide_controller32_r(space, ideoffs, 0x0000ffff); - - /* everything else is byte-sized */ - else - result = ide->ide_controller32_r(space, ideoffs, 0xff << shift) >> shift; - return result; -} - - -WRITE32_DEVICE_HANDLER( midway_ide_asic_w ) -{ - /* convert to standard IDE offsets */ - offs_t ideoffs = 0x1f0/4 + (offset >> 2); - UINT8 shift = 8 * (offset & 3); - - ide_controller_device *ide = (ide_controller_device *) device; - - /* offset 0 is a special case */ - if (offset == 0) - ide->ide_controller32_w(space, ideoffs, data, 0x0000ffff); - - /* everything else is byte-sized */ - else - ide->ide_controller32_w(space, ideoffs, data << shift, 0xff << shift); -} diff --git a/src/mame/machine/midwayic.h b/src/mame/machine/midwayic.h index a004d21c639..8a8fafa6ede 100644 --- a/src/mame/machine/midwayic.h +++ b/src/mame/machine/midwayic.h @@ -47,9 +47,3 @@ enum MIDWAY_IOASIC_SFRUSHRK, MIDWAY_IOASIC_HYPRDRIV }; - - - -/* IDE ASIC maps the IDE registers */ -DECLARE_READ32_DEVICE_HANDLER( midway_ide_asic_r ); -DECLARE_WRITE32_DEVICE_HANDLER( midway_ide_asic_w ); diff --git a/src/mess/drivers/bebox.c b/src/mess/drivers/bebox.c index 51d88f3c096..aa32e5fb565 100644 --- a/src/mess/drivers/bebox.c +++ b/src/mess/drivers/bebox.c @@ -53,14 +53,14 @@ static ADDRESS_MAP_START( bebox_mem, AS_PROGRAM, 64, bebox_state ) AM_RANGE(0x80000080, 0x8000009F) AM_READWRITE8(bebox_page_r, bebox_page_w, U64(0xffffffffffffffff) ) AM_RANGE(0x800000A0, 0x800000BF) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, U64(0xffffffffffffffff) ) AM_RANGE(0x800000C0, 0x800000DF) AM_READWRITE8(at_dma8237_1_r, at_dma8237_1_w, U64(0xffffffffffffffff)) - AM_RANGE(0x800001F0, 0x800001F7) AM_READWRITE8(bebox_800001F0_r, bebox_800001F0_w, U64(0xffffffffffffffff) ) + AM_RANGE(0x800001F0, 0x800001F7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, U64(0xffffffffffffffff) ) AM_RANGE(0x800002F8, 0x800002FF) AM_DEVREADWRITE8( "ns16550_1", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) ) AM_RANGE(0x80000380, 0x80000387) AM_DEVREADWRITE8( "ns16550_2", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) ) AM_RANGE(0x80000388, 0x8000038F) AM_DEVREADWRITE8( "ns16550_3", ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) ) AM_RANGE(0x800003b0, 0x800003bf) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03b0_r, port_03b0_w, U64(0xffffffffffffffff)) AM_RANGE(0x800003c0, 0x800003cf) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03c0_r, port_03c0_w, U64(0xffffffffffffffff)) AM_RANGE(0x800003d0, 0x800003df) AM_DEVREADWRITE8("vga", cirrus_vga_device, port_03d0_r, port_03d0_w, U64(0xffffffffffffffff)) - AM_RANGE(0x800003F0, 0x800003F7) AM_READWRITE(bebox_800003F0_r, bebox_800003F0_w ) + AM_RANGE(0x800003F0, 0x800003F7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs1_pc, write_cs1_pc, U64(0xffffffffffffffff) ) AM_RANGE(0x800003F0, 0x800003F7) AM_DEVICE8( "smc37c78", smc37c78_device, map, U64(0xffffffffffffffff) ) AM_RANGE(0x800003F8, 0x800003FF) AM_DEVREADWRITE8( "ns16550_0",ns16550_device, ins8250_r, ins8250_w, U64(0xffffffffffffffff) ) AM_RANGE(0x80000480, 0x8000048F) AM_READWRITE8(bebox_80000480_r, bebox_80000480_w, U64(0xffffffffffffffff) ) diff --git a/src/mess/includes/bebox.h b/src/mess/includes/bebox.h index 90bd82a3400..ccf7d092655 100644 --- a/src/mess/includes/bebox.h +++ b/src/mess/includes/bebox.h @@ -37,8 +37,7 @@ public: m_pic8259_1(*this, "pic8259_1"), m_pic8259_2(*this, "pic8259_2"), m_pit8254(*this, "pit8254"), - m_ram(*this, RAM_TAG), - m_ide(*this, "ide") + m_ram(*this, RAM_TAG) { } @@ -51,7 +50,6 @@ public: required_device<pic8259_device> m_pic8259_2; required_device<pit8254_device> m_pit8254; required_device<ram_device> m_ram; - required_device<ide_controller_device> m_ide; UINT32 m_cpu_imask[2]; UINT32 m_interrupts; UINT32 m_crossproc_interrupts; @@ -78,8 +76,6 @@ public: DECLARE_READ64_MEMBER(bebox_cpu1_imask_r); DECLARE_READ64_MEMBER(bebox_interrupt_sources_r); DECLARE_READ64_MEMBER(bebox_crossproc_interrupts_r); - DECLARE_READ8_MEMBER(bebox_800001F0_r); - DECLARE_READ64_MEMBER(bebox_800003F0_r); DECLARE_READ64_MEMBER(bebox_interrupt_ack_r); DECLARE_READ8_MEMBER(bebox_page_r); DECLARE_READ8_MEMBER(bebox_80000480_r); diff --git a/src/mess/machine/a2cffa.c b/src/mess/machine/a2cffa.c index e3d6c426981..0c7c0dd30d6 100644 --- a/src/mess/machine/a2cffa.c +++ b/src/mess/machine/a2cffa.c @@ -143,7 +143,7 @@ UINT8 a2bus_cffa2000_device::read_c0nx(address_space &space, UINT8 offset) break; case 8: - m_lastdata = m_ide->ide_controller_r(0x1f0+offset-8, 2); + m_lastdata = m_ide->read_cs0(space, offset-8, 0xffff); return m_lastdata & 0xff; case 9: @@ -153,7 +153,7 @@ UINT8 a2bus_cffa2000_device::read_c0nx(address_space &space, UINT8 offset) case 0xd: case 0xe: case 0xf: - return m_ide->ide_controller_r(0x1f0+offset-8, 1); + return m_ide->read_cs0(space, offset-8, 0xff); } return 0xff; @@ -184,7 +184,7 @@ void a2bus_cffa2000_device::write_c0nx(address_space &space, UINT8 offset, UINT8 case 8: m_lastdata &= 0xff00; m_lastdata |= data; - m_ide->ide_controller_w(0x1f0+offset-8, 2, m_lastdata); + m_ide->write_cs0(space, offset-8, m_lastdata, 0xffff); break; case 9: @@ -194,7 +194,7 @@ void a2bus_cffa2000_device::write_c0nx(address_space &space, UINT8 offset, UINT8 case 0xd: case 0xe: case 0xf: - m_ide->ide_controller_w(0x1f0+offset-8, 1, data); + m_ide->write_cs0(space, offset-8, data, 0xff); break; } } diff --git a/src/mess/machine/a2vulcan.c b/src/mess/machine/a2vulcan.c index 963014f2b41..93b3b1cf41d 100644 --- a/src/mess/machine/a2vulcan.c +++ b/src/mess/machine/a2vulcan.c @@ -151,7 +151,7 @@ UINT8 a2bus_vulcanbase_device::read_c0nx(address_space &space, UINT8 offset) switch (offset) { case 0: - m_lastdata = m_ide->ide_controller_r(0x1f0+offset, 2); + m_lastdata = m_ide->read_cs0(space, offset, 0xffff); // printf("IDE: read %04x\n", m_lastdata); m_last_read_was_0 = true; return m_lastdata&0xff; @@ -164,7 +164,7 @@ UINT8 a2bus_vulcanbase_device::read_c0nx(address_space &space, UINT8 offset) } else { - return m_ide->ide_controller_r(0x1f0+offset, 1); + return m_ide->read_cs0(space, offset, 0xff); } break; @@ -174,7 +174,7 @@ UINT8 a2bus_vulcanbase_device::read_c0nx(address_space &space, UINT8 offset) case 5: case 6: case 7: - return m_ide->ide_controller_r(0x1f0+offset, 1); + return m_ide->read_cs0(space, offset, 0xff); default: // printf("Read @ C0n%x\n", offset); @@ -206,11 +206,11 @@ void a2bus_vulcanbase_device::write_c0nx(address_space &space, UINT8 offset, UIN m_lastdata &= 0x00ff; m_lastdata |= (data << 8); // printf("IDE: write %04x\n", m_lastdata); - m_ide->ide_controller_w(0x1f0, 2, m_lastdata); + m_ide->write_cs0(space, offset, m_lastdata, 0xffff); } else { - m_ide->ide_controller_w(0x1f0+offset, 1, data); + m_ide->write_cs0(space, offset, data, 0xff); } break; @@ -221,7 +221,7 @@ void a2bus_vulcanbase_device::write_c0nx(address_space &space, UINT8 offset, UIN case 6: case 7: // printf("%02x to IDE controller @ %x\n", data, offset); - m_ide->ide_controller_w(0x1f0+offset, 1, data); + m_ide->write_cs0(space, offset, data, 0xff); break; case 9: // ROM bank diff --git a/src/mess/machine/a2zipdrive.c b/src/mess/machine/a2zipdrive.c index d68cfb8369b..171dfa710fa 100644 --- a/src/mess/machine/a2zipdrive.c +++ b/src/mess/machine/a2zipdrive.c @@ -116,10 +116,10 @@ UINT8 a2bus_zipdrivebase_device::read_c0nx(address_space &space, UINT8 offset) case 5: case 6: case 7: - return m_ide->ide_controller_r(0x1f0+offset, 1); + return m_ide->read_cs0(space, offset, 0xff); case 8: // data port - m_lastdata = m_ide->ide_controller_r(0x1f0, 2); + m_lastdata = m_ide->read_cs0(space, offset, 0xffff); // printf("%04x @ IDE data\n", m_lastdata); return m_lastdata&0xff; @@ -152,7 +152,7 @@ void a2bus_zipdrivebase_device::write_c0nx(address_space &space, UINT8 offset, U case 6: case 7: // printf("%02x to IDE controller @ %x\n", data, offset); - m_ide->ide_controller_w(0x1f0+offset, 1, data); + m_ide->write_cs0(space, offset, data, 0xff); break; case 8: @@ -164,7 +164,7 @@ void a2bus_zipdrivebase_device::write_c0nx(address_space &space, UINT8 offset, U // printf("%02x to IDE data hi\n", data); m_lastdata &= 0x00ff; m_lastdata |= (data << 8); - m_ide->ide_controller_w(0x1f0, 2, m_lastdata); + m_ide->write_cs0(space, offset, m_lastdata, 0xffff); break; default: diff --git a/src/mess/machine/adam_ide.c b/src/mess/machine/adam_ide.c index ee4274014ce..33f8366463e 100644 --- a/src/mess/machine/adam_ide.c +++ b/src/mess/machine/adam_ide.c @@ -121,7 +121,7 @@ UINT8 powermate_ide_device::adam_bd_r(address_space &space, offs_t offset, UINT8 case 0x05: case 0x06: case 0x07: - data = m_ide->ide_bus_r(0, offset & 0x07) & 0xff; + data = m_ide->read_cs0(space, offset & 0x07, 0xff); break; case 0x40: // Printer status @@ -142,7 +142,7 @@ UINT8 powermate_ide_device::adam_bd_r(address_space &space, offs_t offset, UINT8 break; case 0x58: - m_ide_data = m_ide->ide_bus_r(0, 0); + m_ide_data = m_ide->read_cs0(space, 0, 0xffff); data = m_ide_data & 0xff; break; @@ -152,7 +152,7 @@ UINT8 powermate_ide_device::adam_bd_r(address_space &space, offs_t offset, UINT8 break; case 0x5a: - data = m_ide->ide_bus_r(1, 6) & 0xff; + data = m_ide->read_cs1(space, 6, 0xff); break; case 0x5b: // Digital Input Register @@ -181,7 +181,7 @@ void powermate_ide_device::adam_bd_w(address_space &space, offs_t offset, UINT8 case 0x05: case 0x06: case 0x07: - m_ide->ide_bus_w(0, offset & 0x07, data); + m_ide->write_cs0(space, offset & 0x07, data, 0xff); break; case 0x40: @@ -193,7 +193,7 @@ void powermate_ide_device::adam_bd_w(address_space &space, offs_t offset, UINT8 case 0x58: m_ide_data |= data; - m_ide->ide_bus_w(0, 0, m_ide_data); + m_ide->write_cs0(space, 0, m_ide_data, 0xffff); break; case 0x59: diff --git a/src/mess/machine/bebox.c b/src/mess/machine/bebox.c index 3def7cf8a19..4663c59e618 100644 --- a/src/mess/machine/bebox.c +++ b/src/mess/machine/bebox.c @@ -504,28 +504,6 @@ READ8_MEMBER(bebox_state::get_slave_ack) * *************************************/ -READ8_MEMBER(bebox_state::bebox_800001F0_r ) { return m_ide->ide_controller_r(offset + 0x1F0, 1); } -WRITE8_MEMBER(bebox_state::bebox_800001F0_w ) { m_ide->ide_controller_w(offset + 0x1F0, 1, data); } - -READ64_MEMBER(bebox_state::bebox_800003F0_r ) -{ - UINT64 result = 0; - - if (((mem_mask >> 8) & 0xFF) == 0) - { - result |= m_ide->ide_controller_r(0x3F6, 1) << 8; - } - return result; -} - - -WRITE64_MEMBER(bebox_state::bebox_800003F0_w ) -{ - if (((mem_mask >> 8) & 0xFF) == 0) - m_ide->ide_controller_w(0x3F6, 1, (data >> 8) & 0xFF); -} - - WRITE_LINE_MEMBER(bebox_state::bebox_ide_interrupt) { bebox_set_irq_bit(machine(), 7, state); diff --git a/src/mess/machine/c64_ide64.c b/src/mess/machine/c64_ide64.c index 3615ad0d1f0..8cbce178076 100644 --- a/src/mess/machine/c64_ide64.c +++ b/src/mess/machine/c64_ide64.c @@ -179,9 +179,15 @@ UINT8 c64_ide64_cartridge_device::c64_cd_r(address_space &space, offs_t offset, UINT8 io1_offset = offset & 0xff; - if (io1_offset >= 0x20 && io1_offset < 0x30) + if (io1_offset >= 0x20 && io1_offset < 0x28) { - m_ide_data = m_ide->ide_bus_r(BIT(offset, 3), offset & 0x07); + m_ide_data = m_ide->read_cs0(space, offset & 0x07, 0xffff); + + data = m_ide_data & 0xff; + } + else if (io1_offset >= 0x28 && io1_offset < 0x30) + { + m_ide_data = m_ide->read_cs1(space, offset & 0x07, 0xffff); data = m_ide_data & 0xff; } @@ -274,11 +280,17 @@ void c64_ide64_cartridge_device::c64_cd_w(address_space &space, offs_t offset, U UINT8 io1_offset = offset & 0xff; - if (io1_offset >= 0x20 && io1_offset < 0x30) + if (io1_offset >= 0x20 && io1_offset < 0x28) + { + m_ide_data = (m_ide_data & 0xff00) | data; + + m_ide->write_cs0(space, offset & 0x07, m_ide_data, 0xffff); + } + else if (io1_offset >= 0x28 && io1_offset < 0x30) { m_ide_data = (m_ide_data & 0xff00) | data; - m_ide->ide_bus_w(BIT(offset, 3), offset & 0x07, m_ide_data); + m_ide->write_cs1(space, offset & 0x07, m_ide_data, 0xffff); } else if (io1_offset == 0x31) { diff --git a/src/mess/machine/isa_ide.c b/src/mess/machine/isa_ide.c index 80c5cd8784f..b2158196ada 100644 --- a/src/mess/machine/isa_ide.c +++ b/src/mess/machine/isa_ide.c @@ -9,28 +9,18 @@ #include "machine/idectrl.h" #include "imagedev/harddriv.h" -READ16_MEMBER(isa16_ide_device::ide16_r) -{ - return m_ide->ide_controller16_r(space, 0x1f0/2 + offset, mem_mask); -} - -WRITE16_MEMBER(isa16_ide_device::ide16_w) -{ - m_ide->ide_controller16_w(space, 0x1f0/2 + offset, data, mem_mask); -} - READ8_MEMBER(isa16_ide_device::ide16_alt_r ) { - return m_ide->ide_controller16_r(space, 0x3f6/2, 0x00ff); + return m_ide->read_cs1_pc(space, 6/2, 0xff); } WRITE8_MEMBER(isa16_ide_device::ide16_alt_w ) { - m_ide->ide_controller16_w(space, 0x3f6/2, data, 0x00ff); + m_ide->write_cs1_pc(space, 6/2, data, 0xff); } DEVICE_ADDRESS_MAP_START(map, 16, isa16_ide_device) - AM_RANGE(0x0, 0x7) AM_READWRITE(ide16_r, ide16_w) + AM_RANGE(0x0, 0x7) AM_DEVREADWRITE("ide", ide_controller_device, read_cs0_pc, write_cs0_pc) ADDRESS_MAP_END DEVICE_ADDRESS_MAP_START(alt_map, 8, isa16_ide_device) diff --git a/src/mess/machine/isa_ide.h b/src/mess/machine/isa_ide.h index 6b3a5ee5ced..31d0637b6d0 100644 --- a/src/mess/machine/isa_ide.h +++ b/src/mess/machine/isa_ide.h @@ -28,8 +28,6 @@ public: DECLARE_WRITE_LINE_MEMBER(ide_interrupt); DECLARE_ADDRESS_MAP(map, 16); DECLARE_ADDRESS_MAP(alt_map, 8); - READ16_MEMBER(ide16_r); - WRITE16_MEMBER(ide16_w); READ8_MEMBER(ide16_alt_r); WRITE8_MEMBER(ide16_alt_w); protected: diff --git a/src/mess/machine/isa_ide8.c b/src/mess/machine/isa_ide8.c index 42bd80ddeaf..adf14db7701 100644 --- a/src/mess/machine/isa_ide8.c +++ b/src/mess/machine/isa_ide8.c @@ -62,15 +62,16 @@ static READ8_DEVICE_HANDLER( ide8_r ) if(offset == 0) { // Data register transfer low byte and latch high - result=ide->ide_controller_read(0, (offset & 0x07), 1); - ide8_d->set_latch_in(ide->ide_controller_read(0, (offset & 0x07), 1)); + UINT16 data16 = ide->read_cs0(space, (offset & 0x07), 0xffff); + result = data16 & 0xff; + ide8_d->set_latch_in(data16>>8); } else if((offset > 0) && (offset < 8)) - result=ide->ide_controller_read(0, (offset & 0x07), 1); + result=ide->read_cs0(space, (offset & 0x07), 0xff); else if(offset == 8) result=ide8_d->get_latch_in(); else if(offset == 14) - result=ide->ide_controller_read(1, (offset & 0x07), 1); + result=ide->read_cs1(space, (offset & 0x07), 0xff); // logerror("%s ide8_r: offset=%d, result=%2X\n",device->machine().describe_context(),offset,result); @@ -87,15 +88,15 @@ static WRITE8_DEVICE_HANDLER( ide8_w ) if(offset == 0) { // Data register transfer low byte and latched high - ide->ide_controller_write(0, (offset & 7), 1, data); - ide->ide_controller_write(0, (offset & 7), 1, ide8_d->get_latch_out()); + UINT16 data16 = (ide8_d->get_latch_out() << 8) | data; + ide->write_cs0(space, (offset & 7), data16, 0xffff); } else if((offset > 0) && (offset < 8)) - ide->ide_controller_write(0, (offset & 7), 1, data); + ide->write_cs0(space, (offset & 7), data, 0xff); else if(offset == 8) ide8_d->set_latch_out(data); else if(offset == 14) - ide->ide_controller_write(1, (offset & 7), 1, data); + ide->write_cs1(space, (offset & 7), data, 0xff); } diff --git a/src/mess/machine/kc_d004.c b/src/mess/machine/kc_d004.c index e72bd603d2a..83810272830 100644 --- a/src/mess/machine/kc_d004.c +++ b/src/mess/machine/kc_d004.c @@ -454,7 +454,16 @@ READ8_MEMBER(kc_d004_gide_device::gide_r) data_shift = 8; if (io_addr == 0x06 || io_addr == 0x07 || io_addr > 0x08 || (io_addr == 0x08 && !m_lh)) - m_ide_data = m_ide->ide_bus_r(ide_cs, io_addr & 0x07); + { + if (ide_cs == 0 ) + { + m_ide_data = m_ide->read_cs0(space, io_addr & 0x07, 0xffff); + } + else + { + m_ide_data = m_ide->read_cs1(space, io_addr & 0x07, 0xffff); + } + } data = (m_ide_data >> data_shift) & 0xff; } @@ -494,7 +503,16 @@ WRITE8_MEMBER(kc_d004_gide_device::gide_w) m_ide_data = (data << data_shift) | (m_ide_data & (0xff00 >> data_shift)); if (io_addr == 0x06 || io_addr == 0x07 || io_addr > 0x08 || (io_addr == 0x08 && m_lh)) - m_ide->ide_bus_w(ide_cs, io_addr & 0x07, m_ide_data); + { + if (ide_cs == 0) + { + m_ide->write_cs0(space, io_addr & 0x07, m_ide_data, 0xffff); + } + else + { + m_ide->write_cs1(space, io_addr & 0x07, m_ide_data, 0xffff); + } + } } m_lh = (io_addr == 0x08) ? !m_lh : ((io_addr > 0x08) ? 0 : m_lh); diff --git a/src/mess/machine/ti99/tn_ide.c b/src/mess/machine/ti99/tn_ide.c index 1906e61f7e6..bcff6a2b708 100644 --- a/src/mess/machine/ti99/tn_ide.c +++ b/src/mess/machine/ti99/tn_ide.c @@ -151,7 +151,7 @@ READ8Z_MEMBER(nouspikel_ide_interface_device::readz) case 2: /* IDE registers set 1 (CS1Fx) */ if (m_tms9995_mode ? (!(addr & 1)) : (addr & 1)) { /* first read triggers 16-bit read cycle */ - m_input_latch = (! (addr & 0x10)) ? m_ide->ide_bus_r(0, (addr >> 1) & 0x7) : 0; + m_input_latch = (! (addr & 0x10)) ? m_ide->read_cs0(space, (addr >> 1) & 0x7, 0xffff) : 0; } /* return latched input */ @@ -162,7 +162,7 @@ READ8Z_MEMBER(nouspikel_ide_interface_device::readz) case 3: /* IDE registers set 2 (CS3Fx) */ if (m_tms9995_mode ? (!(addr & 1)) : (addr & 1)) { /* first read triggers 16-bit read cycle */ - m_input_latch = (! (addr & 0x10)) ? m_ide->ide_bus_r(1, (addr >> 1) & 0x7) : 0; + m_input_latch = (! (addr & 0x10)) ? m_ide->read_cs1(space, (addr >> 1) & 0x7, 0xffff) : 0; } /* return latched input */ @@ -232,7 +232,7 @@ WRITE8_MEMBER(nouspikel_ide_interface_device::write) if (m_tms9995_mode ? (addr & 1) : (!(addr & 1))) { /* second write triggers 16-bit write cycle */ - m_ide->ide_bus_w(0, (addr >> 1) & 0x7, m_output_latch); + m_ide->write_cs0(space, (addr >> 1) & 0x7, m_output_latch, 0xffff); } break; case 3: /* IDE registers set 2 (CS3Fx) */ @@ -250,7 +250,7 @@ WRITE8_MEMBER(nouspikel_ide_interface_device::write) if (m_tms9995_mode ? (addr & 1) : (!(addr & 1))) { /* second write triggers 16-bit write cycle */ - m_ide->ide_bus_w(1, (addr >> 1) & 0x7, m_output_latch); + m_ide->write_cs1(space, (addr >> 1) & 0x7, m_output_latch, 0xffff); } break; } |