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author hap <happppp@users.noreply.github.com>2023-05-19 14:45:27 +0200
committer hap <happppp@users.noreply.github.com>2023-05-19 14:45:27 +0200
commit945c5034f543c25f0279eaf9f0890b959673cbf0 (patch)
tree6181a0a65e8edfe46fb1eb5a80de40c82ef44728
parent4890c043184eb0b4c61982c50dc96e25aa9625f3 (diff)
atirage: fix -Wmaybe-uninitialized issue
-rw-r--r--src/devices/video/atirage.cpp15
1 files changed, 6 insertions, 9 deletions
diff --git a/src/devices/video/atirage.cpp b/src/devices/video/atirage.cpp
index cc1022e376c..ff481f736ef 100644
--- a/src/devices/video/atirage.cpp
+++ b/src/devices/video/atirage.cpp
@@ -233,7 +233,7 @@ u8 atirage_device::regs_0_read(offs_t offset)
case CRTC_DAC_BASE + 1:
{
- u8 result;
+ u8 result = 0;
switch (m_dac_state)
{
case 0: // red
@@ -400,17 +400,10 @@ void atirage_device::update_mode()
m_format = m_regs0[CRTC_GEN_CNTL+1] & 7;
LOGMASKED(LOG_CRTC, "Setting mode (%d x %d), total (%d x %d) format %d\n", m_hres, m_vres, m_htotal, m_vtotal, m_format);
- int vclk_source = (m_pll_regs[PLL_VCLK_CNTL] & 3);
- if ((vclk_source != 0) && (vclk_source != 3))
- {
- LOGMASKED(LOG_CRTC, "VCLK source (%d) is not VPLL, can't calculate dot clock\n", m_pll_regs[PLL_VCLK_CNTL] & 3);
- return;
- }
-
double vpll_frequency;
int clk_source = m_regs0[CLOCK_CNTL] & 3;
- switch (vclk_source)
+ switch (m_pll_regs[PLL_VCLK_CNTL] & 3)
{
case 0: // CPUCLK (the PCI bus clock, not to exceed 33 MHz)
vpll_frequency = (33000000.0 * m_pll_regs[VCLK0_FB_DIV + clk_source]) / m_pll_regs[PLL_REF_DIV];
@@ -419,6 +412,10 @@ void atirage_device::update_mode()
case 3: // PLLVCLK
vpll_frequency = ((clock() * 2.0) * m_pll_regs[VCLK0_FB_DIV + clk_source]) / m_pll_regs[PLL_REF_DIV];
break;
+
+ default:
+ LOGMASKED(LOG_CRTC, "VCLK source (%d) is not VPLL, can't calculate dot clock\n", m_pll_regs[PLL_VCLK_CNTL] & 3);
+ return;
}
LOGMASKED(LOG_CRTC, "VPLL freq %f\n", vpll_frequency);