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author ClawGrip <clawgrip@hotmail.com>2019-07-06 22:20:06 +0200
committer GitHub <noreply@github.com>2019-07-06 22:20:06 +0200
commit923aaf620c5af6e7e94d2887cf0b740d1b712d9c (patch)
tree3214374056d1fde17d04d3769bf0b652f996435f
parent173962bf18acf20ada60d1b592bf798be28a32a5 (diff)
mpu5.hxx: Add some game hardware info (nw)
-rw-r--r--src/mame/drivers/mpu5.hxx73
1 files changed, 73 insertions, 0 deletions
diff --git a/src/mame/drivers/mpu5.hxx b/src/mame/drivers/mpu5.hxx
index 2cbae586c06..6d784869a2f 100644
--- a/src/mame/drivers/mpu5.hxx
+++ b/src/mame/drivers/mpu5.hxx
@@ -2,6 +2,79 @@
// copyright-holders:David Haywood
/* for MPU5 hardware emulation see mpu5hw.c, this just contains the set listing and per machine configs */
+/* Example MPU5 game cart layout:
+
+Barcrest Gold Strike V.1.0 game cart for MPU5 (distributed on Spain by Bilso / Servimatic)
+ _________________________________________________
+| ___ |
+| | | ____ |
+| CPUBUS |IC| |SW ||
+| __ |1 | |2__||
+| __________ __________ | | |__| ___ |
+| | P7 | | P8 EMPTY| | | |SW||
+| |_________| |_________| | | |1 ||
+| __________ __________ | | |__||
+| | C5 EMPTY| | C6 EMPTY| | | ________ ____ |
+| |_________| |_________| | | |__IC3__| |CON||
+| __________ __________ | | | 1 ||
+| | C3 | | C4 | | | |___||
+| |_________| |_________| | | _______ ____ |
+| __________ __________ | | |__IC2__| |CON||
+| | C1 | | C2 | | | | 2 ||
+| |_________| |_________| | | |___||
+| HIGH BYTE LOW BYTE |_| |
+| CBA |
+|_________________________________________________|
+
+P7 = ST M48T02-150PC1 NVRAM labeled as BILSO S.A. B-14 GOLD STRIKE V 1.0 CVB-0200A / 11-1562 [may be RAM (P7B) or PROM (P7A)]
+C1 = 27C4001 labeled as BILSO S.A. B-14 P4 GOLD STRIKE V 1.0 CVB-0200A / 11-1562
+C2 = 27C4001 labeled as BILSO S.A. B-14 P3 GOLD STRIKE V 1.0 CVB-0200A / 11-1562
+C3 = 27C4001 labeled as BILSO S.A. B-14 P1 GOLD STRIKE V 1.0 CVB-0200A / 11-1562
+C4 = 27C4001 labeled as BILSO S.A. B-14 P1 GOLD STRIKE V 1.0 CVB-0200A / 11-1562
+IC1 = PIC16C54C labeled as 105RGSG (may be PIC or Z8)
+IC2 = GAL16V8 labeled as 105ICI1E
+IC3 = GAL16V8 labeled as 105ICI2A
+SW1 = 8 dipswitches for options
+SW2 = Test switch
+CON1 = Female DB9 for percentage
+CON2 = Male DB9 for stake/jackpot
+
+ CPUBUS
+ __
+ DREC2 | | DONE2
+ IRQ5 | | SER_INT
+ IRQ7 | | TIN1
+ CPUCLK | | INTX
+ BERR | | GND
+ TOUT2 | | 5V
+ DSACK1 | | GND
+ TOUT1 | | GND
+ FC3 | | GND
+ BDS | | GND
+ SIZ1 | | GND
+ EXT_IO | | 5V
+ A1 | | GND
+ A3 | | GND
+ A5 | | GND
+ A7 | | GND
+ A9 | | GND
+ A11 | | 5V
+ A13 | | GND
+ A15 | | 24V
+ A17 | | GND
+ A19 | | -12V
+ A21 | | GND
+ A23 | | 5V
+ D1 | | GND
+ D3 | | GND
+ D5 | | 12V
+ D7 | | 12V
+ D9 | | 12V
+ D11 | | 12V
+ D13 | | 12V
+ D15 |_| 12V
+*/
+
INPUT_PORTS_EXTERN( mpu5 );