diff options
author | 2018-04-07 18:43:39 -0400 | |
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committer | 2018-04-07 18:43:58 -0400 | |
commit | 7a3a0a42438c45188a19466f3c9b9dbc8bd5b03a (patch) | |
tree | 35a40dab7aa67998eb2d84ee484591f1b6f11335 | |
parent | 1a0fae9b4cdb8a5eb0835bb798952f5ba7f7e357 (diff) |
arm: Eliminate spurious LSL #32 shifts from disassembly (nw)
-rw-r--r-- | src/devices/cpu/arm/armdasm.cpp | 46 | ||||
-rw-r--r-- | src/devices/cpu/arm/armdasm.h | 8 |
2 files changed, 31 insertions, 23 deletions
diff --git a/src/devices/cpu/arm/armdasm.cpp b/src/devices/cpu/arm/armdasm.cpp index 657ceb43550..81bd4c8dc6e 100644 --- a/src/devices/cpu/arm/armdasm.cpp +++ b/src/devices/cpu/arm/armdasm.cpp @@ -21,7 +21,7 @@ void arm_disassembler::WriteImmediateOperand( std::ostream &stream, uint32_t opc util::stream_format( stream, ", #$%x", imm ); } -void arm_disassembler::WriteDataProcessingOperand( std::ostream &stream, uint32_t opcode, int printOp0, int printOp1, int printOp2 ) const +void arm_disassembler::WriteDataProcessingOperand( std::ostream &stream, uint32_t opcode, bool printOp0, bool printOp1) const { /* ccccctttmmmm */ static const char *const pRegOp[4] = { "LSL","LSR","ASR","ROR" }; @@ -40,20 +40,23 @@ void arm_disassembler::WriteDataProcessingOperand( std::ostream &stream, uint32_ } /* Register Op2 */ - if (printOp2) - util::stream_format(stream, "R%d, ", (opcode>>0)&0xf); - - util::stream_format(stream, "%s ", pRegOp[(opcode>>5)&3]); + util::stream_format(stream, "R%d", (opcode>>0)&0xf); + int shiftop = (opcode >> 5) & 3; if( opcode&0x10 ) /* Shift amount specified in bottom bits of RS */ { - util::stream_format( stream, "R%d", (opcode>>8)&0xf ); + util::stream_format(stream, ", %s R%d", pRegOp[shiftop], (opcode >> 8) & 0xf); } else /* Shift amount immediate 5 bit unsigned integer */ { - int c=(opcode>>7)&0x1f; - if( c==0 ) c = 32; - util::stream_format( stream, "#%d", c ); + int c = (opcode >> 7) & 0x1f; + if (c == 0) + { + if (shiftop == 0) + return; + c = 32; + } + util::stream_format( stream, ", %s #%d", pRegOp[shiftop], c); } } @@ -62,21 +65,26 @@ void arm_disassembler::WriteRegisterOperand1( std::ostream &stream, uint32_t opc /* ccccctttmmmm */ static const char *const pRegOp[4] = { "LSL","LSR","ASR","ROR" }; + int shiftop = (opcode >> 5) & 3; util::stream_format( stream, - ", R%d %s ", /* Operand 1 register, Operand 2 register, shift type */ - (opcode>> 0)&0xf, - pRegOp[(opcode>>5)&3]); + ", R%d", /* Operand 1 register, Operand 2 register */ + (opcode >> 0) & 0xf); if( opcode&0x10 ) /* Shift amount specified in bottom bits of RS */ { - util::stream_format( stream, "R%d", (opcode>>7)&0xf ); + util::stream_format(stream, " %s R%d", pRegOp[shiftop], (opcode >> 7) & 0xf); } else /* Shift amount immediate 5 bit unsigned integer */ { - int c=(opcode>>7)&0x1f; - if( c==0 ) c = 32; - util::stream_format( stream, "#%d", c ); + int c = (opcode >> 7) & 0x1f; + if (c == 0) + { + if (shiftop == 0) + return; + c = 32; + } + util::stream_format(stream, " %s #%d", pRegOp[shiftop], c); } } /* WriteRegisterOperand */ @@ -184,20 +192,20 @@ offs_t arm_disassembler::disassemble(std::ostream &stream, offs_t pc, const data case 0x07: case 0x0c: case 0x0e: - WriteDataProcessingOperand(stream, opcode, 1, 1, 1); + WriteDataProcessingOperand(stream, opcode, true, true); break; case 0x08: case 0x09: case 0x0a: case 0x0b: - WriteDataProcessingOperand(stream, opcode, 0, 1, 1); + WriteDataProcessingOperand(stream, opcode, false, true); break; case 0x0d: /* look for mov pc,lr */ if (((opcode >> 12) & 0x0f) == 15 && ((opcode >> 0) & 0x0f) == 14 && (opcode & 0x02000000) == 0) dasmflags = STEP_OUT; case 0x0f: - WriteDataProcessingOperand(stream, opcode, 1, 0, 1); + WriteDataProcessingOperand(stream, opcode, true, false); break; } } diff --git a/src/devices/cpu/arm/armdasm.h b/src/devices/cpu/arm/armdasm.h index 1e2ed19f394..4b20e7b79fb 100644 --- a/src/devices/cpu/arm/armdasm.h +++ b/src/devices/cpu/arm/armdasm.h @@ -12,10 +12,10 @@ public: virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) override; private: - void WriteImmediateOperand( std::ostream &stream, uint32_t opcode ) const; - void WriteDataProcessingOperand( std::ostream &stream, uint32_t opcode, int printOp0, int printOp1, int printOp2 ) const; - void WriteRegisterOperand1( std::ostream &stream, uint32_t opcode ) const; - void WriteBranchAddress( std::ostream &stream, uint32_t pc, uint32_t opcode ) const; + void WriteImmediateOperand(std::ostream &stream, uint32_t opcode) const; + void WriteDataProcessingOperand(std::ostream &stream, uint32_t opcode, bool printOp0, bool printOp1) const; + void WriteRegisterOperand1(std::ostream &stream, uint32_t opcode) const; + void WriteBranchAddress(std::ostream &stream, uint32_t pc, uint32_t opcode) const; void WritePadding(std::ostream &stream, std::streampos start_position) const; }; |