diff options
author | MooglyGuy <therealmogminer@gmail.com> | 2019-06-16 18:24:57 +0200 |
---|---|---|
committer | MooglyGuy <therealmogminer@gmail.com> | 2019-06-16 18:25:13 +0200 |
commit | 76f92529d7a930ace0d3038ba6f3d078d142830f (patch) | |
tree | fea6b40ef59dfe173850bb067da28f901ce995b4 | |
parent | 7080aa92fddce0dc1c81dec36a9dabb0c200ac0b (diff) |
-dpb7000: Added additional logging for Brush Address Card and Store Address Card accesses, nw
-rw-r--r-- | src/mame/drivers/dpb7000.cpp | 210 |
1 files changed, 192 insertions, 18 deletions
diff --git a/src/mame/drivers/dpb7000.cpp b/src/mame/drivers/dpb7000.cpp index 5bfe206b324..44eefee7d25 100644 --- a/src/mame/drivers/dpb7000.cpp +++ b/src/mame/drivers/dpb7000.cpp @@ -21,18 +21,22 @@ #include "screen.h" #include <deque> -#define LOG_UNKNOWN (1 << 0) -#define LOG_UCODE (1 << 2) -#define LOG_MORE_UCODE (1 << 3) -#define LOG_CSR (1 << 4) -#define LOG_CTRLBUS (1 << 5) -#define LOG_SYS_CTRL (1 << 6) -#define LOG_FDC_CTRL (1 << 7) -#define LOG_FDC_PORT (1 << 8) -#define LOG_FDC_CMD (1 << 9) -#define LOG_ALL (LOG_UNKNOWN | LOG_UCODE | LOG_MORE_UCODE | LOG_CSR | LOG_CTRLBUS | LOG_SYS_CTRL | LOG_FDC_CTRL | LOG_FDC_PORT | LOG_FDC_CMD) - -#define VERBOSE (LOG_ALL &~ LOG_FDC_CTRL) +#define LOG_UNKNOWN (1 << 0) +#define LOG_UCODE (1 << 1) +#define LOG_MORE_UCODE (1 << 2) +#define LOG_CSR (1 << 3) +#define LOG_CTRLBUS (1 << 4) +#define LOG_SYS_CTRL (1 << 5) +#define LOG_FDC_CTRL (1 << 6) +#define LOG_FDC_PORT (1 << 7) +#define LOG_FDC_CMD (1 << 8) +#define LOG_OUTPUT_TIMING (1 << 9) +#define LOG_STORE_ADDR (1 << 10) +#define LOG_BRUSH_ADDR (1 << 11) +#define LOG_ALL (LOG_UNKNOWN | LOG_UCODE | LOG_MORE_UCODE | LOG_CSR | LOG_CTRLBUS | LOG_SYS_CTRL | LOG_FDC_CTRL | LOG_FDC_PORT | LOG_FDC_CMD | \ + LOG_OUTPUT_TIMING | LOG_STORE_ADDR | LOG_BRUSH_ADDR) + +#define VERBOSE (LOG_ALL &~ LOG_FDC_CTRL) #include "logmacro.h" class dpb7000_state : public driver_device @@ -175,8 +179,11 @@ private: DSEQ_CTRLOUT_DISC_CLEAR = (1 << 7), // S55 }; + // Computer Card uint8_t m_csr; uint16_t m_sys_ctrl; + + // Disc Sequencer Card int m_diskseq_cp; bool m_diskseq_reset; bool m_diskseq_halt; @@ -191,6 +198,15 @@ private: uint8_t m_diskseq_status_out; // BC uint8_t m_diskseq_ucode_latch[7]; // GG/GF/GE/GD/GC/GB/GA uint8_t m_diskseq_cc_inputs[4]; // Inputs to FE/FD/FC/FB + + // Output Timing Card + uint16_t m_cursor_origin_x; + uint16_t m_cursor_origin_y; + uint16_t m_cursor_size_x; + uint16_t m_cursor_size_y; + + // Brush Address Card + uint16_t m_brush_addr_func; }; void dpb7000_state::main_map(address_map &map) @@ -346,8 +362,17 @@ INPUT_PORTS_END void dpb7000_state::machine_start() { + // Computer Card save_item(NAME(m_csr)); save_item(NAME(m_sys_ctrl)); + + m_field_in_clk = timer_alloc(TIMER_FIELD_IN); + m_field_in_clk->adjust(attotime::never); + + m_field_out_clk = timer_alloc(TIMER_FIELD_OUT); + m_field_out_clk->adjust(attotime::never); + + // Disc Sequencer Card save_item(NAME(m_diskseq_cp)); save_item(NAME(m_diskseq_reset)); save_item(NAME(m_diskseq_halt)); @@ -372,18 +397,27 @@ void dpb7000_state::machine_start() m_diskseq_clk = timer_alloc(TIMER_DISKSEQ); m_diskseq_clk->adjust(attotime::never); - m_field_in_clk = timer_alloc(TIMER_FIELD_IN); - m_field_in_clk->adjust(attotime::never); + // Output Timing Card + save_item(NAME(m_cursor_origin_x)); + save_item(NAME(m_cursor_origin_y)); + save_item(NAME(m_cursor_size_x)); + save_item(NAME(m_cursor_size_y)); - m_field_out_clk = timer_alloc(TIMER_FIELD_OUT); - m_field_out_clk->adjust(attotime::never); + // Brush Address Card + save_item(NAME(m_brush_addr_func)); } void dpb7000_state::machine_reset() { + // Computer Card m_brg->stt_w(m_baud_dip->read()); m_csr = 0; m_sys_ctrl = SYSCTRL_REQ_B_IN; + + m_field_in_clk->adjust(attotime::from_hz(59.94), 0, attotime::from_hz(59.94)); + m_field_out_clk->adjust(attotime::from_hz(59.94) + attotime::from_hz(15734.0 / 1.0), 0, attotime::from_hz(59.94)); + + // Disc Sequencer Card m_diskseq_cp = 0; m_diskseq_reset = false; m_diskseq_halt = true; @@ -400,9 +434,8 @@ void dpb7000_state::machine_reset() memset(m_diskseq_cc_inputs, 0, 4); m_diskseq_clk->adjust(attotime::from_hz(1000000), 0, attotime::from_hz(1000000)); - m_field_in_clk->adjust(attotime::from_hz(59.94), 0, attotime::from_hz(59.94)); - m_field_out_clk->adjust(attotime::from_hz(59.94) + attotime::from_hz(15734.0 / 1.0), 0, attotime::from_hz(59.94)); + // Floppy Disc Controller m_fdd_debug_rx_bits.clear(); m_fdd_debug_rx_bit_count = 0; m_fdd_debug_rx_byte_count = 0; @@ -410,6 +443,15 @@ void dpb7000_state::machine_reset() m_fdd_ctrl = 0; m_fdd_port1 = 0; m_fdd_track = 20; + + // Output Timing Card + m_cursor_origin_x = 0; + m_cursor_origin_y = 0; + m_cursor_size_x = 0; + m_cursor_size_y = 0; + + // Brush Address Card + m_brush_addr_func = 0; } void dpb7000_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) @@ -668,6 +710,10 @@ READ16_MEMBER(dpb7000_state::cpu_ctrlbus_r) uint16_t ret = 0; switch (m_csr) { + case 0: + LOGMASKED(LOG_CTRLBUS, "%s: CPU read from Control Bus, Brush Address Card status: %04x\n", machine().describe_context(), m_brush_addr_func); + ret = m_brush_addr_func; + break; case 1: LOGMASKED(LOG_CTRLBUS, "%s: CPU read from Control Bus, Disk Sequencer Card status: %02x\n", machine().describe_context(), m_diskseq_status_out); ret = m_diskseq_status_out; @@ -691,6 +737,31 @@ WRITE16_MEMBER(dpb7000_state::cpu_ctrlbus_w) { switch (m_csr) { + case 0: // Brush Address Card, function select + { + static const char* const s_func_names[16] = + { + "Live Video", "Brush Store Read", "Brush Store Write", "Framestore Read", + "Framestore Write", "Fast Wipe Video", "Fast Wipe Brush Store", "Fast Wipe Framestore", + "Draw", "Draw with Stencil I", "Draw with Stencil II", "Copy to Framestore", + "Copy to Brush Store", "Paste with Stencil I", "Paste with Stencil II", "Copy to same Framestore (Invert)" + }; + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, "%s: Brush Address Card, Function Select: %04x\n", machine().describe_context(), data); + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, " Function: %s\n", s_func_names[(data >> 1) & 0xf]); + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, " /Store I: %d\n", BIT(data, 5)); + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, " /Store II: %d\n", BIT(data, 6)); + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, " Luma Enable: %d\n", BIT(data, 7)); + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, " Chroma Enable: %d\n", BIT(data, 8)); + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, " Brush Select: %d\n", BIT(data, 9)); + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, " Disc Enable: %d\n", BIT(data, 10)); + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, " /Brush Invert: %d\n", BIT(data, 11)); + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, " Brush Zero: %d\n", BIT(data, 12)); + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, " Fixed Color Select: %d\n", BIT(data, 13)); + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, " Go: %d\n", BIT(data, 0)); + m_brush_addr_func = data & ~1; + break; + } + case 1: // Disk Sequencer Card, disc access { const uint8_t hi_nybble = data >> 12; @@ -712,6 +783,109 @@ WRITE16_MEMBER(dpb7000_state::cpu_ctrlbus_w) } break; } + + case 2: // Store Address Card + switch ((data >> 12) & 7) + { + case 0: + LOGMASKED(LOG_CTRLBUS | LOG_STORE_ADDR, "%s: CPU write to Store Address Card (%s), set RHSCR: %03x\n", machine().describe_context(), BIT(data, 15) ? "II" : "Both", data & 0xfff); + break; + case 1: + LOGMASKED(LOG_CTRLBUS | LOG_STORE_ADDR, "%s: CPU write to Store Address Card (%s), set RVSCR: %03x\n", machine().describe_context(), BIT(data, 15) ? "II" : "Both", data & 0xfff); + break; + case 2: + LOGMASKED(LOG_CTRLBUS | LOG_STORE_ADDR, "%s: CPU write to Store Address Card (%s), set R ZOOM: %03x\n", machine().describe_context(), BIT(data, 15) ? "II" : "Both", data & 0xfff); + break; + case 3: + LOGMASKED(LOG_CTRLBUS | LOG_STORE_ADDR, "%s: CPU write to Store Address Card (%s), set FLDSEL: %03x\n", machine().describe_context(), BIT(data, 15) ? "II" : "Both", data & 0xfff); + break; + case 4: + LOGMASKED(LOG_CTRLBUS | LOG_STORE_ADDR, "%s: CPU write to Store Address Card (%s), set CXPOS: %03x\n", machine().describe_context(), BIT(data, 15) ? "II" : "Both", data & 0xfff); + break; + case 5: + LOGMASKED(LOG_CTRLBUS | LOG_STORE_ADDR, "%s: CPU write to Store Address Card (%s), set CYPOS: %03x\n", machine().describe_context(), BIT(data, 15) ? "II" : "Both", data & 0xfff); + break; + default: + LOGMASKED(LOG_CTRLBUS | LOG_STORE_ADDR, "%s: CPU write to Store Address Card (%s), unknown register: %04x\n", machine().describe_context(), BIT(data, 15) ? "II" : "Both", data); + break; + } + break; + + case 8: // Brush Address Card, "Select 8" signal to PAL 16L8, BE + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, "%s: Brush Address Card, Select 8\n", machine().describe_context()); + break; + + case 9: // Brush Address Card, register write/select + switch (data >> 12) + { + case 1: + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, "%s: Brush Address Card, Register Write: BIF = %02x\n", machine().describe_context(), data & 0xff); + break; + case 2: + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, "%s: Brush Address Card, Register Write: BIXOS = %d\n", machine().describe_context(), data & 0x7); + break; + case 3: + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, "%s: Brush Address Card, Register Write: BIYOS = %d\n", machine().describe_context(), data & 0x7); + break; + case 4: + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, "%s: Brush Address Card, Register Write: BXLEN = %02x\n", machine().describe_context(), data & 0x3f); + break; + case 5: + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, "%s: Brush Address Card, Register Write: BYLEN = %02x\n", machine().describe_context(), data & 0x3f); + break; + case 6: + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, "%s: Brush Address Card, Register Write: PLUM = %03x(?)\n", machine().describe_context(), data & 0xfff); + break; + case 7: + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, "%s: Brush Address Card, Register Write: PCHR = %03x(?)\n", machine().describe_context(), data & 0xfff); + break; + default: + LOGMASKED(LOG_CTRLBUS | LOG_BRUSH_ADDR, "%s: Brush Address Card, Register Write: Unknown (%04x)\n", machine().describe_context(), data); + break; + } + break; + + case 10: // Output Timing Card, cursor registers + { + const uint8_t hi_bits = (data >> 14) & 3; + if (hi_bits == 0) // Cursor Parameters + { + static const char* const s_reg_names[4] = { "Cursor X Origin", "Cursor Y Origin", "Cursor X Size", "Cursor Y Size" }; + const uint8_t reg = (data >> 12) & 3; + LOGMASKED(LOG_CTRLBUS | LOG_OUTPUT_TIMING, "%s: CPU write to Output Timing Card: %s = %03x\n", machine().describe_context, s_reg_names[reg], data & 0xfff); + switch (reg) + { + case 0: // Cursor X Origin + m_cursor_origin_x = data & 0xfff; + break; + case 1: // Cursor Y Origin + m_cursor_origin_y = data & 0xfff; + break; + case 2: // Cursor X Size + m_cursor_size_x = data & 0xfff; + break; + case 3: // Cursor Y Size + m_cursor_size_y = data & 0xfff; + break; + } + } + else if (hi_bits == 3) // Cursor Misc. + { + if ((data & 0x2c00) == 0) + { + } + else + { + LOGMASKED(LOG_CTRLBUS | LOG_OUTPUT_TIMING | LOG_UNKNOWN, "%s: CPU write to Output Timing Card, unknown Cursor Misc. value: %04x\n", machine().describe_context(), data); + } + } + else + { + LOGMASKED(LOG_CTRLBUS | LOG_OUTPUT_TIMING | LOG_UNKNOWN, "%s: CPU write to Output Timing Card, unknown select value: %04x\n", machine().describe_context(), data); + } + break; + } + case 15: // Disk Sequencer Card, panic reset LOGMASKED(LOG_CTRLBUS, "%s: CPU write to Control Bus, Disk Sequencer Card, panic reset\n", machine().describe_context()); m_diskseq_reset = true; |