summaryrefslogtreecommitdiffstatshomepage
diff options
context:
space:
mode:
author yz70s <yz70s@users.noreply.github.com>2019-04-05 11:13:05 +0200
committer yz70s <yz70s@users.noreply.github.com>2019-04-05 12:16:57 +0200
commit7638df70ad6178351129d01d6439d6aae4f9793b (patch)
treeebc98184c73e3fba55b9e5873c83962cd63c61c2
parent551eb4328c5969733997eb7aa597a501e9561d15 (diff)
nforcepc.cpp: add pci device to handle ddr ram memory (nw)
This will allow the bios to go through the ddr ram initialization procedure.
-rw-r--r--src/mame/drivers/nforcepc.cpp93
-rw-r--r--src/mame/includes/nforcepc.h34
2 files changed, 106 insertions, 21 deletions
diff --git a/src/mame/drivers/nforcepc.cpp b/src/mame/drivers/nforcepc.cpp
index 3bb38d17b8b..e933f52c3d3 100644
--- a/src/mame/drivers/nforcepc.cpp
+++ b/src/mame/drivers/nforcepc.cpp
@@ -28,13 +28,29 @@
#include "includes/xbox_pci.h"
#include "includes/nforcepc.h"
+#if 1
// for now let's use this as the contents of the spd chip in the ddr dimm memory module
static const uint8_t test_spd_data[] = {
- 0x80,0x08,0x07,0x0D,0x0A,0x01,0x40,0x00,0x04,0x75,0x75,0x00,0x82,0x10,0x00,0x01,0x0E,0x04,0x0C,0x01,0x02,0x20,0xC0,0xA0,0x75,0x00,
- 0x00,0x50,0x3C,0x50,0x2D,0x40,0x90,0x90,0x50,0x50,0x00,0x00,0x00,0x00,0x00,0x41,0x4B,0x30,0x32,0x75,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xEA,0xAD,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x48,0x59,0x4D,0x44,0x35,
- 0x33,0x32,0x4D,0x36,0x34,0x36,0x43,0x36,0x2D,0x48,0x20,0x20,0x20
+ 0x80,0x08,0x07,0x0D,0x0A,0x01,0x40,0x00,0x04,0x75,0x75,0x00,0x82,0x10,0x00,0x01,
+ 0x0E,0x04,0x0C,0x01,0x02,0x20,0xC0,0xA0,0x75,0x00,0x00,0x50,0x3C,0x50,0x2D,0x40,
+ 0x90,0x90,0x50,0x50,0x00,0x00,0x00,0x00,0x00,0x41,0x4B,0x30,0x32,0x75,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xEA,
+ 0xAD,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x48,0x59,0x4D,0x44,0x35,0x33,0x32,
+ 0x4D,0x36,0x34,0x36,0x43,0x36,0x2D,0x48,0x20,0x20,0x20
};
+#else
+// From a HYS72D64320HU-5-C (512MB PC3200 (400mHz) DDR CL3 ECC)
+static const uint8_t test_spd_data[] = {
+ 0x80,0x08,0x07,0x0d,0x0a,0x02,0x48,0x00,0x04,0x50,0x50,0x02,0x82,0x08,0x08,0x01,
+ 0x0e,0x04,0x1c,0x01,0x02,0x20,0xc1,0x60,0x50,0x75,0x50,0x3c,0x28,0x3c,0x28,0x40,
+ 0x60,0x60,0x40,0x40,0x00,0x00,0x00,0x00,0x00,0x37,0x41,0x28,0x28,0x50,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,
+ 0xc1,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x45,0x37,0x32,0x44,0x36,0x34,0x33,0x32,
+ 0x30,0x48,0x55,0x35,0x43,0x20,0x20,0x20,0x20,0x20,0x20,0x02,0x4c,0x05,0x44,0x01,
+ 0x08,0x56,0x26,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+};
+#endif
/*
Pci devices
@@ -56,11 +72,6 @@ crush11_host_device::crush11_host_device(const machine_config &mconfig, const ch
{
}
-void crush11_host_device::set_ram_size(int ram_size)
-{
- ddr_ram_size = ram_size;
-}
-
void crush11_host_device::device_start()
{
pci_host_device::device_start();
@@ -74,8 +85,6 @@ void crush11_host_device::device_start()
io_window_end = 0xffff;
io_offset = 0;
status = 0x0010;
-
- ram.resize(ddr_ram_size / 4);
}
void crush11_host_device::reset_all_mappings()
@@ -93,8 +102,6 @@ void crush11_host_device::map_extra(uint64_t memory_window_start, uint64_t memor
{
io_space->install_device(0, 0xffff, *static_cast<pci_host_device *>(this), &pci_host_device::io_configuration_access_map);
- memory_space->install_ram(0x00000000, 0x0009ffff, &ram[0x00000000 / 4]);
- memory_space->install_ram(0x00100000, ddr_ram_size - 1, &ram[0x00100000 / 4]);
uint32_t mask = m_region->bytes() - 1;
memory_space->install_rom(0x000c0000, 0x000fffff, m_region->base() + (0x000c0000 & mask));
memory_space->install_rom(0xfffc0000, 0xffffffff, m_region->base() + (0x000c0000 & mask));
@@ -110,6 +117,62 @@ WRITE8_MEMBER(crush11_host_device::test_w)
logerror("test = %02x\n", data);
}
+// For ddr ram
+
+DEFINE_DEVICE_TYPE(CRUSH11_MEMORY, crush11_memory_device, "crush11_memory", "nForce memory")
+
+void crush11_memory_device::config_map(address_map &map)
+{
+ pci_device::config_map(map);
+ /*
+ bit 31 of a0,a4,a8,ac,b0 and b4 must be 0
+ bit 0 of c4 and c8 must be 0
+ */
+ map(0xa0, 0xa3).nopr();
+ map(0xa4, 0xa7).nopr();
+ map(0xa8, 0xab).nopr();
+ map(0xac, 0xaf).nopr();
+ map(0xb0, 0xb3).nopr();
+ map(0xb4, 0xb7).nopr();
+ map(0xc4, 0xc7).nopr();
+ map(0xc8, 0xcb).nopr();
+}
+
+crush11_memory_device::crush11_memory_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, int ram_size)
+ : crush11_memory_device(mconfig, tag, owner, clock)
+{
+ set_ram_size(ram_size);
+}
+
+crush11_memory_device::crush11_memory_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : pci_device(mconfig, CRUSH11_MEMORY, tag, owner, clock)
+{
+ set_ids(0x10de01ac, 0, 0, 0);
+}
+
+void crush11_memory_device::device_start()
+{
+ pci_device::device_start();
+ ram.resize(ddr_ram_size * 1024 * 1024 / 4);
+}
+
+void crush11_memory_device::device_reset()
+{
+ pci_device::device_reset();
+}
+
+void crush11_memory_device::set_ram_size(int ram_size)
+{
+ ddr_ram_size = ram_size;
+}
+
+void crush11_memory_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
+ uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space)
+{
+ memory_space->install_ram(0x00000000, 0x0009ffff, &ram[0x00000000 / 4]);
+ memory_space->install_ram(0x00100000, ddr_ram_size * 1024 * 1024 - 1, &ram[0x00100000 / 4]);
+}
+
/*
Ddevices connected to SMBus
*/
@@ -352,8 +415,8 @@ void nforcepc_state::nforcepc(machine_config &config)
maincpu.set_irq_acknowledge_callback(FUNC(nforcepc_state::irq_callback));
PCI_ROOT(config, ":pci", 0);
- CRUSH11(config, ":pci:00.0", 0, "maincpu", 2 * 1024 * 1024); /* 10de:01a4 NVIDIA Corporation nForce CPU bridge
- 10de:01ac NVIDIA Corporation nForce 220/420 Memory Controller
+ CRUSH11(config, ":pci:00.0", 0, "maincpu"); // 10de:01a4 NVIDIA Corporation nForce CPU bridge
+ CRUSH11_MEMORY(config, ":pci:00.1", 0, 2); /* 10de:01ac NVIDIA Corporation nForce 220/420 Memory Controller
10de:01ad NVIDIA Corporation nForce 220/420 Memory Controller
10de:01ab NVIDIA Corporation nForce 420 Memory Controller (DDR)*/
mcpx_isalpc_device &isa(MCPX_ISALPC(config, ":pci:01.0", 0, 0x10430c11)); // 10de:01b2 NVIDIA Corporation nForce ISA Bridge (LPC bus)
diff --git a/src/mame/includes/nforcepc.h b/src/mame/includes/nforcepc.h
index cdc2802ac7a..44f59c755b1 100644
--- a/src/mame/includes/nforcepc.h
+++ b/src/mame/includes/nforcepc.h
@@ -10,17 +10,16 @@
class crush11_host_device : public pci_host_device {
public:
template <typename T>
- crush11_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag, int ram_size)
+ crush11_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag)
: crush11_host_device(mconfig, tag, owner, clock)
{
set_ids_host(0x10de01a4, 0x01, 0x10430c11);
set_cpu_tag(std::forward<T>(cpu_tag));
- set_ram_size(ram_size);
}
crush11_host_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
template <typename T> void set_cpu_tag(T &&tag) { cpu.set_tag(std::forward<T>(tag)); }
- void set_ram_size(int ram_size);
+ const char *get_cpu_tag() { return cpu.finder_tag(); }
protected:
virtual void device_start() override;
@@ -34,9 +33,7 @@ protected:
virtual void config_map(address_map &map) override;
private:
- int ddr_ram_size;
required_device<device_memory_interface> cpu;
- std::vector<uint32_t> ram;
DECLARE_READ8_MEMBER(test_r);
DECLARE_WRITE8_MEMBER(test_w);
@@ -44,6 +41,31 @@ private:
DECLARE_DEVICE_TYPE(CRUSH11, crush11_host_device)
+// For ddr ram
+
+class crush11_memory_device : public pci_device {
+public:
+ crush11_memory_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, int ram_size);
+ crush11_memory_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+ void set_ram_size(int ram_size);
+
+protected:
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
+ uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
+
+ virtual void config_map(address_map &map) override;
+
+private:
+ int ddr_ram_size;
+ std::vector<uint32_t> ram;
+};
+
+DECLARE_DEVICE_TYPE(CRUSH11_MEMORY, crush11_memory_device)
+
// device connected to SMBus
class smbus_logger_device : public device_t, public smbus_interface
@@ -84,7 +106,7 @@ private:
DECLARE_DEVICE_TYPE(SMBUS_ROM, smbus_rom_device)
// Asus AS99127F chip
-// It answerst to three smbus addresses, by default 0x2d 0x48 0x49
+// It answers to three smbus addresses, by default 0x2d 0x48 0x49
class as99127f_device : public device_t, public smbus_interface
{