diff options
author | angelosa <salese_corp_ltd@email.it> | 2016-12-24 22:19:27 +0100 |
---|---|---|
committer | angelosa <salese_corp_ltd@email.it> | 2016-12-24 22:20:06 +0100 |
commit | 7489c09cb802d1dbb67d9eaad201cb8671dd7021 (patch) | |
tree | f93fb590952cad91d3b6ce6a82e773c2e1c6522b | |
parent | fbb8ee0fe89ed8b56a23418fb38621e74d7bab68 (diff) |
archimds.cpp: fixed Vertical Count Register and pixel clock timings, nw
-rw-r--r-- | src/mame/drivers/aa310.cpp | 5 | ||||
-rw-r--r-- | src/mame/machine/archimds.cpp | 7 |
2 files changed, 4 insertions, 8 deletions
diff --git a/src/mame/drivers/aa310.cpp b/src/mame/drivers/aa310.cpp index a31aa0cc2b6..6a3aa2f042f 100644 --- a/src/mame/drivers/aa310.cpp +++ b/src/mame/drivers/aa310.cpp @@ -401,10 +401,7 @@ static MACHINE_CONFIG_START( aa310, aa310_state ) /* video hardware */ MCFG_SCREEN_ADD("screen", RASTER) - MCFG_SCREEN_REFRESH_RATE(60) - MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */ - MCFG_SCREEN_SIZE(1280, 1024) //TODO: default screen size - MCFG_SCREEN_VISIBLE_AREA(0*8, 1280 - 1, 0*16, 1024 - 1) + MCFG_SCREEN_RAW_PARAMS(XTAL_16MHz,1024,0,735,624/2,0,292) // RiscOS 3 default screen settings MCFG_SCREEN_UPDATE_DRIVER(archimedes_state, screen_update) MCFG_PALETTE_ADD("palette", 32768) diff --git a/src/mame/machine/archimds.cpp b/src/mame/machine/archimds.cpp index f8fd709159b..f8546a68c71 100644 --- a/src/mame/machine/archimds.cpp +++ b/src/mame/machine/archimds.cpp @@ -926,9 +926,8 @@ void archimedes_state::vidc_dynamic_res_change() // m_vidc_regs[VIDC_HDER]-m_vidc_regs[VIDC_HDSR],m_vidc_regs[VIDC_VDER]-m_vidc_regs[VIDC_VDSR]+1, // m_vidc_vblank_time); - /* FIXME: pixel clock */ - refresh = HZ_TO_ATTOSECONDS(pixel_rate[m_vidc_pixel_clk]*2) * m_vidc_regs[VIDC_HCR] * m_vidc_regs[VIDC_VCR]; - + refresh = HZ_TO_ATTOSECONDS(pixel_rate[m_vidc_pixel_clk]) * m_vidc_regs[VIDC_HCR] * m_vidc_regs[VIDC_VCR]; + m_screen->configure(m_vidc_regs[VIDC_HCR], m_vidc_regs[VIDC_VCR] * (m_vidc_interlace+1), visarea, refresh); } } @@ -1016,7 +1015,7 @@ WRITE32_MEMBER(archimedes_state::archimedes_vidc_w) case VIDC_HCSR: m_vidc_regs[VIDC_HCSR] = ((val >> 13) & 0x7ff) + 6; break; // #define VIDC_HIR 0x9c - case VIDC_VCR: m_vidc_regs[VIDC_VCR] = ((val >> 14)<<1)+1; break; + case VIDC_VCR: m_vidc_regs[VIDC_VCR] = ((val >> 14))+1; break; // #define VIDC_VSWR 0xa4 case VIDC_VBSR: m_vidc_regs[VIDC_VBSR] = (val >> 14)+1; break; case VIDC_VDSR: m_vidc_regs[VIDC_VDSR] = (val >> 14)+1; break; |