diff options
author | R. Belmont <rb6502@users.noreply.github.com> | 2017-06-20 12:16:05 -0400 |
---|---|---|
committer | GitHub <noreply@github.com> | 2017-06-20 12:16:05 -0400 |
commit | 742bcdc029286440c75f8889e7bc6ffd99512d2f (patch) | |
tree | 555422c0921953b24ef3521bc921cb5a8d1d52f8 | |
parent | 2c96a26af21eceb389b2372ec61723a4d3a9245e (diff) | |
parent | 66d825fc52dd0cb10b4ab217eb02bf6ec48f62c4 (diff) |
Merge pull request #2394 from pmackinlay/interpro
interpro: various small improvements, no breakthroughs
-rw-r--r-- | src/devices/cpu/clipper/clipper.cpp | 22 | ||||
-rw-r--r-- | src/devices/cpu/clipper/clipper.h | 18 | ||||
-rw-r--r-- | src/devices/machine/ncr5390.cpp | 20 | ||||
-rw-r--r-- | src/devices/machine/ncr539x.cpp | 6 | ||||
-rw-r--r-- | src/mame/drivers/interpro.cpp | 286 | ||||
-rw-r--r-- | src/mame/includes/interpro.h | 114 | ||||
-rw-r--r-- | src/mame/machine/interpro_ioga.cpp | 259 | ||||
-rw-r--r-- | src/mame/machine/interpro_ioga.h | 80 | ||||
-rw-r--r-- | src/mame/machine/interpro_mcga.cpp | 23 | ||||
-rw-r--r-- | src/mame/machine/interpro_mcga.h | 75 | ||||
-rw-r--r-- | src/mame/machine/interpro_sga.cpp | 6 | ||||
-rw-r--r-- | src/mame/machine/interpro_sga.h | 39 | ||||
-rw-r--r-- | src/mame/machine/interpro_srarb.cpp | 3 | ||||
-rw-r--r-- | src/mame/machine/interpro_srarb.h | 20 |
14 files changed, 667 insertions, 304 deletions
diff --git a/src/devices/cpu/clipper/clipper.cpp b/src/devices/cpu/clipper/clipper.cpp index 69f00ba1f15..357cd4b3f08 100644 --- a/src/devices/cpu/clipper/clipper.cpp +++ b/src/devices/cpu/clipper/clipper.cpp @@ -28,10 +28,6 @@ #define R1 (m_info.r1) #define R2 (m_info.r2) -// convenience macros for dealing with the psw -#define PSW(mask) (m_psw & PSW_##mask) -#define SSW(mask) (m_ssw & SSW_##mask) - // macros for setting psw condition codes #define FLAGS(C,V,Z,N) \ m_psw = (m_psw & ~(PSW_C | PSW_V | PSW_Z | PSW_N)) | (((C) << 3) | ((V) << 2) | ((Z) << 1) | ((N) << 0)); @@ -57,17 +53,19 @@ DEFINE_DEVICE_TYPE(CLIPPER_C300, clipper_c300_device, "clipper_c300", "C300 CLIP DEFINE_DEVICE_TYPE(CLIPPER_C400, clipper_c400_device, "clipper_c400", "C400 CLIPPER") clipper_c100_device::clipper_c100_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) - : clipper_device(mconfig, CLIPPER_C100, tag, owner, clock) { } + : clipper_device(mconfig, CLIPPER_C100, tag, owner, clock, 0) { } clipper_c300_device::clipper_c300_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) - : clipper_device(mconfig, CLIPPER_C300, tag, owner, clock) { } + : clipper_device(mconfig, CLIPPER_C300, tag, owner, clock, 0) { } clipper_c400_device::clipper_c400_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) - : clipper_device(mconfig, CLIPPER_C400, tag, owner, clock) { } + : clipper_device(mconfig, CLIPPER_C400, tag, owner, clock, SSW_ID_C400R4) { } -clipper_device::clipper_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock) +clipper_device::clipper_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, const u32 cpuid) : cpu_device(mconfig, type, tag, owner, clock), m_pc(0), + m_psw(0), + m_ssw(cpuid), m_r(m_rs), m_insn_config("insn", ENDIANNESS_LITTLE, 32, 32, 0), m_data_config("data", ENDIANNESS_LITTLE, 32, 32, 0), @@ -170,7 +168,7 @@ void clipper_device::device_reset() * ssw: EI, TP, M, U, K, KU, UU, P cleared, ID set from hardware, others undefined */ m_psw = 0; - m_ssw = 0; + set_ssw(0); m_r = SSW(U) ? m_ru : m_rs; @@ -425,7 +423,7 @@ int clipper_device::execute_instruction () m_psw = m_r[R2]; else if (!SSW(U) && (R1 == 1 || R1 == 3)) { - m_ssw = m_r[R2]; + set_ssw(m_r[R2]); m_r = SSW(U) ? m_ru : m_rs; } // FLAGS: CVZN @@ -1272,7 +1270,7 @@ int clipper_device::execute_instruction () (m_info.macro >> 4) & 0xf, m_rs[(m_info.macro >> 4) & 0xf], m_pc, m_data->read_dword(m_rs[(m_info.macro >> 4) & 0xf] + 8)); m_psw = m_data->read_dword(m_rs[(m_info.macro >> 4) & 0xf] + 0); - m_ssw = m_data->read_dword(m_rs[(m_info.macro >> 4) & 0xf] + 4); + set_ssw(m_data->read_dword(m_rs[(m_info.macro >> 4) & 0xf] + 4)); next_pc = m_data->read_dword(m_rs[(m_info.macro >> 4) & 0xf] + 8); m_rs[(m_info.macro >> 4) & 0xf] += 12; @@ -1348,7 +1346,7 @@ u32 clipper_device::intrap(u32 vector, u32 pc, u32 cts, u32 mts) m_rs[15] -= 24; // load ssw from trap vector and set previous mode - m_ssw = (m_data->read_dword(vector + 0) & ~SSW_P) | (SSW(U) << 1); + set_ssw((m_data->read_dword(vector + 0) & ~(SSW(P))) | (SSW(U) << 1)); // clear psw m_psw = 0; diff --git a/src/devices/cpu/clipper/clipper.h b/src/devices/cpu/clipper/clipper.h index a00b8d5ce1c..4a0492f91d4 100644 --- a/src/devices/cpu/clipper/clipper.h +++ b/src/devices/cpu/clipper/clipper.h @@ -8,8 +8,13 @@ #include <limits.h> +// convenience macros for dealing with the psw and ssw +#define PSW(mask) (m_psw & PSW_##mask) +#define SSW(mask) (m_ssw & SSW_##mask) + class clipper_device : public cpu_device { +protected: enum registers { CLIPPER_R0, CLIPPER_R1, CLIPPER_R2, CLIPPER_R3, CLIPPER_R4, CLIPPER_R5, CLIPPER_R6, CLIPPER_R7, @@ -101,6 +106,15 @@ class clipper_device : public cpu_device SSW_P = 0x80000000, // previous mode }; + enum clipper_ssw_id + { + SSW_ID_C400R0 = 0x00000, + SSW_ID_C400R1 = 0x04000, + SSW_ID_C400R2 = 0x08000, + SSW_ID_C400R3 = 0x0c000, + SSW_ID_C400R4 = 0x10000 + }; + enum exception_vectors { // data memory trap group @@ -167,7 +181,7 @@ public: DECLARE_READ32_MEMBER(ssw) { return m_ssw; } protected: - clipper_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock); + clipper_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, const u32 cpuid); // device-level overrides virtual void device_start() override; @@ -195,6 +209,8 @@ protected: virtual uint32_t disasm_max_opcode_bytes() const override { return 8; } // largest instruction virtual offs_t disasm_disassemble(std::ostream &stream, offs_t pc, const u8 *oprom, const u8 *opram, u32 options) override; + void set_ssw(u32 data) { m_ssw = (m_ssw & SSW(ID)) | (data & ~SSW(ID)); } + // core registers u32 m_pc; u32 m_psw; diff --git a/src/devices/machine/ncr5390.cpp b/src/devices/machine/ncr5390.cpp index c140c2bd8b9..f4ad2ca4cf3 100644 --- a/src/devices/machine/ncr5390.cpp +++ b/src/devices/machine/ncr5390.cpp @@ -577,7 +577,7 @@ void ncr5390_device::delay_cycles(int cycles) READ8_MEMBER(ncr5390_device::tcount_lo_r) { - logerror("%s: tcount_lo_r %02x (%08x)\n", tag(), tcount & 0xff, space.device().safe_pc()); + logerror("%s: tcount_lo_r %02x (%s)\n", tag(), tcount & 0xff, machine().describe_context()); return tcount; } @@ -585,12 +585,12 @@ WRITE8_MEMBER(ncr5390_device::tcount_lo_w) { tcount = (tcount & 0xff00) | data; status &= ~S_TC0; - logerror("%s: tcount_lo_w %02x (%08x)\n", tag(), data, space.device().safe_pc()); + logerror("%s: tcount_lo_w %02x (%s)\n", tag(), data, machine().describe_context()); } READ8_MEMBER(ncr5390_device::tcount_hi_r) { - logerror("%s: tcount_hi_r %02x (%08x)\n", tag(), tcount >> 8, space.device().safe_pc()); + logerror("%s: tcount_hi_r %02x (%s)\n", tag(), tcount >> 8, machine().describe_context()); return tcount >> 8; } @@ -598,7 +598,7 @@ WRITE8_MEMBER(ncr5390_device::tcount_hi_w) { tcount = (tcount & 0x00ff) | (data << 8); status &= ~S_TC0; - logerror("%s: tcount_hi_w %02x (%08x)\n", tag(), data, space.device().safe_pc()); + logerror("%s: tcount_hi_w %02x (%s)\n", tag(), data, machine().describe_context()); } uint8_t ncr5390_device::fifo_pop() @@ -638,13 +638,13 @@ WRITE8_MEMBER(ncr5390_device::fifo_w) READ8_MEMBER(ncr5390_device::command_r) { - logerror("%s: command_r (%08x)\n", tag(), space.device().safe_pc()); + logerror("%s: command_r (%s)\n", tag(), machine().describe_context()); return command[0]; } WRITE8_MEMBER(ncr5390_device::command_w) { - logerror("%s: command_w %02x (%08x)\n", tag(), data, space.device().safe_pc()); + logerror("%s: command_w %02x (%s)\n", tag(), data, machine().describe_context()); if(command_pos == 2) { status |= S_GROSS_ERROR; check_irq(); @@ -787,7 +787,7 @@ READ8_MEMBER(ncr5390_device::status_r) { uint32_t ctrl = scsi_bus->ctrl_r(); uint8_t res = status | (ctrl & S_MSG ? 4 : 0) | (ctrl & S_CTL ? 2 : 0) | (ctrl & S_INP ? 1 : 0); - logerror("%s: status_r %02x (%08x)\n", tag(), res, space.device().safe_pc()); + logerror("%s: status_r %02x (%s)\n", tag(), res, machine().describe_context()); if(irq) status &= ~(S_GROSS_ERROR|S_PARITY|S_TCC); return res; @@ -808,7 +808,7 @@ READ8_MEMBER(ncr5390_device::istatus_r) if(res) command_pop_and_chain(); - logerror("%s: istatus_r %02x (%08x)\n", tag(), res, space.device().safe_pc()); + logerror("%s: istatus_r %02x (%s)\n", tag(), res, machine().describe_context()); return res; } @@ -819,7 +819,7 @@ WRITE8_MEMBER(ncr5390_device::timeout_w) READ8_MEMBER(ncr5390_device::seq_step_r) { - logerror("%s: seq_step_r %d (%08x)\n", tag(), seq, space.device().safe_pc()); + logerror("%s: seq_step_r %d (%s)\n", tag(), seq, machine().describe_context()); return seq; } @@ -932,5 +932,5 @@ WRITE8_MEMBER(ncr53c94_device::conf_w) WRITE8_MEMBER(ncr53c94_device::test_w) { if (test_mode) - logerror("%s: test_w %d (%08x) - test mode not implemented\n", tag(), data, space.device().safe_pc()); + logerror("%s: test_w %d (%s) - test mode not implemented\n", tag(), data, machine().describe_context()); } diff --git a/src/devices/machine/ncr539x.cpp b/src/devices/machine/ncr539x.cpp index eedc81e2d05..3e9853a784f 100644 --- a/src/devices/machine/ncr539x.cpp +++ b/src/devices/machine/ncr539x.cpp @@ -284,7 +284,7 @@ READ8_MEMBER( ncr539x_device::read ) { uint8_t rv = 0; - LOGREADS("539x: Read @ %s (%02x) (PC=%x) (status %02x irq_status %02x)\n", rdregs[offset], offset, space.device().safe_pc(), m_status, m_irq_status); + LOGREADS("539x: Read @ %s (%02x) (%s) (status %02x irq_status %02x)\n", rdregs[offset], offset, machine().describe_context(), m_status, m_irq_status); switch (offset) { @@ -313,7 +313,7 @@ READ8_MEMBER( ncr539x_device::read ) m_xfer_count--; update_fifo_internal_state(fifo_bytes); - LOG("Read %02x from FIFO[%d], FIFO now contains %d bytes (PC=%x, m_buffer_remaining %x)\n", rv, m_fifo_read_ptr-1, fifo_bytes, space.device().safe_pc(), m_buffer_remaining); + LOG("Read %02x from FIFO[%d], FIFO now contains %d bytes (%s) (m_buffer_remaining %x)\n", rv, m_fifo_read_ptr-1, fifo_bytes, machine().describe_context(), m_buffer_remaining); if (fifo_bytes == 0) { @@ -415,7 +415,7 @@ READ8_MEMBER( ncr539x_device::read ) WRITE8_MEMBER( ncr539x_device::write ) { //if (offset != 2) - LOG("539x: Write %02x @ %s (%02x) (PC=%x)\n", data, wrregs[offset], offset, space.device().safe_pc()); + LOG("539x: Write %02x @ %s (%02x) (%s)\n", data, wrregs[offset], offset, machine().describe_context()); switch (offset) { diff --git a/src/mame/drivers/interpro.cpp b/src/mame/drivers/interpro.cpp index 5df7ad56ba5..dc3ea441252 100644 --- a/src/mame/drivers/interpro.cpp +++ b/src/mame/drivers/interpro.cpp @@ -3,7 +3,7 @@ #include "emu.h" -#define NEW_SCSI 0 +#define NEW_SCSI 1 #include "includes/interpro.h" #include "debugger.h" @@ -20,91 +20,81 @@ // machine start void interpro_state::machine_start() { - m_system_reg[SREG_CTRL2] = CTRL2_COLDSTART | CTRL2_PWRENA | CTRL2_PWRUP; + m_sreg_ctrl2 = CTRL2_COLDSTART | CTRL2_PWRENA | CTRL2_PWRUP; } void interpro_state::machine_reset() { // flash rom requires the following values - m_system_reg[SREG_ERROR] = 0x00; - m_system_reg[SREG_STATUS] = 0x400; - m_system_reg[SREG_CTRL1] = CTRL1_FLOPRDY; + m_sreg_error = 0x00; + m_sreg_status = 0x400; + m_sreg_ctrl1 = CTRL1_FLOPRDY; } -WRITE16_MEMBER(interpro_state::system_w) +WRITE16_MEMBER(interpro_state::sreg_ctrl1_w) { - switch (offset) - { - case SREG_LED: - LOG_SYSTEM("LED value %d at %s\n", data, machine().describe_context()); - break; - - case SREG_STATUS: // not sure if writable? - break; - - case SREG_CTRL1: - LOG_SYSTEM("system control register 1 write data 0x%x pc %s\n", data, machine().describe_context()); + LOG_SYSTEM("system control register 1 write data 0x%x (%s)\n", data, machine().describe_context()); - if ((data ^ m_system_reg[offset]) & CTRL1_LEDDP) - LOG_SYSTEM("LED decimal point %s\n", data & CTRL1_LEDDP ? "on" : "off"); + if ((data ^ m_sreg_ctrl1) & CTRL1_LEDDP) + LOG_SYSTEM("LED decimal point %s\n", data & CTRL1_LEDDP ? "on" : "off"); - m_system_reg[offset] = data; - break; + m_sreg_ctrl1 = data; +} - case SREG_CTRL2: - LOG_SYSTEM("system control register 2 write data 0x%x at %s\n", data, machine().describe_context()); - if (data & CTRL2_RESET) - { - m_system_reg[SREG_CTRL2] &= ~CTRL2_COLDSTART; +WRITE16_MEMBER(interpro_state::sreg_ctrl2_w) +{ + LOG_SYSTEM("system control register 2 write data 0x%x (%s)\n", data, machine().describe_context()); + if (data & CTRL2_RESET) + { + m_sreg_ctrl1 &= ~CTRL2_COLDSTART; - machine().schedule_soft_reset(); - } - else - m_system_reg[offset] = data & 0x0f; // top four bits are not persistent - break; + machine().schedule_soft_reset(); } + else + m_sreg_ctrl1 = data & CTRL2_WMASK; } -READ16_MEMBER(interpro_state::system_r) +READ16_MEMBER(interpro_state::sreg_error_r) { - LOG_SYSTEM("system register read offset %d at %s\n", offset, machine().describe_context()); - switch (offset) - { - case SREG_ERROR: - case SREG_STATUS: - case SREG_CTRL1: - case SREG_CTRL2: - default: - return m_system_reg[offset]; - break; - } + u16 result = m_sreg_error; + + // clear error register on read + m_sreg_error = 0; + + return result; } -READ32_MEMBER(interpro_state::idprom_r) +READ8_MEMBER(interpro_state::idprom_r) { LOG_IDPROM("idprom read offset 0x%x mask 0x%08x at %s\n", offset, mem_mask, machine().describe_context()); - // abitrary fake number for now, not working properly - u32 speed = 20000000; - u32 speed1 = speed >> 24; - u32 speed2 = speed >> 16; - u32 speed3 = speed >> 8; + // compute femtoseconds per cycle from main cpu clock + u32 speed = 1'000'000'000'000'000 / m_maincpu->clock(); - static uint8_t idprom[] = { + static u8 idprom[] = { // module type id - 'M', 'P', 'C', 'B', - '0', '1', '4', '5', + 0x00, 0x00, 0x00, 0x00, // board type MSMT/MPCB - detected by feature[3] + '1', '2', '3', // board number + 'A', // board revision // ECO bytes 0x87, 0x65, 0x43, 0x21, 0xbb, 0xcc, 0xdd, 0xee, // the following 8 bytes are "feature bytes" - // the feature bytes contain a 32 bit word which is divided by 40000 - // if they're empty, a default value of 50 000 000 is used - // perhaps this is a system speed (50MHz)? - 0x2, 0x34, 0x56, 0x78, - (u8)speed, (u8)speed3, (u8)speed2, (u8)speed1, + + // for a 2700/2800/2500 system board, the first feature byte selects the variant + // model = (feature[0] & 0x2) ? (feature[0] & 0x8 ? 2700 : 2800) : 2500 + + // 0x0a, // 2700 series + 0x02, // 2800 series + // 0x00, // 2500 series + + 0x00, 0x00, + 0x80, // board type, 0x80 = MPCB, 0x00 = MSMT + + // for the system boards, these bytes contain cpu clock speed (as femtoseconds per cycle, big-endian) + (u8)(speed >> 24), (u8)(speed >> 16), (u8)(speed >> 8), (u8)(speed >> 0), // reserved bytes 0xff, 0xff, @@ -113,8 +103,14 @@ READ32_MEMBER(interpro_state::idprom_r) // boot rom tests for family == 0x41 or 0x42 // if so, speed read from feature bytes 2 & 3 // if not, read speed from feature bytes 4-7 - 0x41, 0x00, // 2800-series CPU - //0x24, 0x00, // 2000-series system board + + //0x24, 0x00, // 2000 + + // 0x31, 0x00, // 2400 + 0x39, 0x00, // 2700/2800/2500 depending on first feature byte (0xa, 0x2, 0x0) + // 0x40, 0x00, // 6700 + // 0x41, 0x00, // idprom reports as 2800 series cpu? + //0x42, 0x00, // 6800 series // footprint and checksum 0x55, 0xaa, 0x55, 0x00 @@ -124,13 +120,13 @@ READ32_MEMBER(interpro_state::idprom_r) { case 0x1f: { - uint8_t sum = 0; + u8 sum = 0; // compute the checksum (sum of all bytes must be == 0x00) for (int i = 0; i < 0x20; i++) sum += idprom[i]; - return 0x100 - (sum & 0xff); + return 0x100 - sum; } default: @@ -138,19 +134,74 @@ READ32_MEMBER(interpro_state::idprom_r) } } -READ32_MEMBER(interpro_state::slot0_r) +READ8_MEMBER(interpro_state::slot0_r) { +#if 0 // a known graphics board idprom - static uint8_t slot0[] = { + static u8 slot0[] = { 0x00, 0x00, 0x00, 0x00, '9', '6', '3', 'A', // board 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // eco 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // features 0xff, 0xff, // reserved 0x22, 0x00, // family - 0x55, 0xaa, 0x55, 0x00 + 0x55, 0xaa, 0x55, // footprint + 0x00 // checksum + }; +#else + static u8 slot0[] = { + 0x00, 0x00, 0x00, 0x00, '1', '1', '1', 'A', // board + 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // eco + 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, // features + 0xff, 0xff, // reserved + 0x05, 0x00, // family + 0x55, 0xaa, 0x55, // footprint + 0x00 // checksum }; +#endif + switch (offset) + { + case 0x1f: + { + u8 sum = 0; + + // compute the checksum (sum of all bytes must be == 0x00) + for (int i = 0; i < 0x20; i++) + sum += slot0[i]; - return ((uint8_t *)&slot0)[offset % 32]; + return 0x100 - sum; + } + + default: + return slot0[offset]; + } +} + +READ32_MEMBER(interpro_state::unmapped_r) +{ + // check if non-existent memory errors are enabled + if (m_srarb->tmctrl_r(space, offset, mem_mask) & interpro_srarb_device::TMCTRL_ENNEM) + { + // flag non-existent memory error in system error register + m_sreg_error |= (ERROR_SRXNEM | ERROR_SRXVALID); + + // tell ioga to raise a bus error + m_ioga->bus_error(space, interpro_ioga_device::BINFO_BERR | interpro_ioga_device::BINFO_SNAPOK, offset << 2); + } + + return space.unmap(); +} + +WRITE32_MEMBER(interpro_state::unmapped_w) +{ + // check if non-existent memory errors are enabled + if (m_srarb->tmctrl_r(space, offset, mem_mask) & interpro_srarb_device::TMCTRL_ENNEM) + { + // flag non-existent memory error in system error register + m_sreg_error |= (ERROR_SRXNEM | ERROR_SRXVALID); + + // tell ioga to raise a bus error + m_ioga->bus_error(space, interpro_ioga_device::BINFO_BERR | interpro_ioga_device::BINFO_SNAPOK, offset << 2); + } } WRITE8_MEMBER(interpro_state::rtc_w) @@ -271,6 +322,19 @@ WRITE8_MEMBER(interpro_state::scsi_dma_w) DRIVER_INIT_MEMBER(interpro_state, ip2800) { + // FIXME: not all memory sizes are reported properly using fdm "5 inqhw" and "optimum_memory" commands + + // 16 = reports 16M, banks empty? + // 32 = reports 16M, banks empty? + // 64 = reports 128M, 16x8 + // 128 = reports 128M, 16x8 + // 256 = reports 256M, 32x8 + + // grab the main memory space from the mmu + address_space &space = m_mmu->space(AS_0); + + // map the configured ram + space.install_ram(0, m_ram->mask(), m_ram->pointer()); } #if NEW_SCSI @@ -280,7 +344,7 @@ static SLOT_INTERFACE_START(interpro_scsi_devices) SLOT_INTERFACE_INTERNAL(INTERPRO_SCSI_ADAPTER_TAG, NCR53C94) SLOT_INTERFACE_END -static MACHINE_CONFIG_FRAGMENT(interpro_scsi_adapter) +static MACHINE_CONFIG_START(interpro_scsi_adapter) MCFG_DEVICE_CLOCK(XTAL_12_5MHz) MCFG_NCR5390_IRQ_HANDLER(DEVWRITELINE(":" INTERPRO_IOGA_TAG, interpro_ioga_device, ir0_w)) MCFG_NCR5390_DRQ_HANDLER(DEVWRITELINE(":" INTERPRO_IOGA_TAG, interpro_ioga_device, drq_scsi)) @@ -296,50 +360,49 @@ static ADDRESS_MAP_START(clipper_data_map, AS_DATA, 32, interpro_state) AM_RANGE(0x00000000, 0xffffffff) AM_DEVREADWRITE32(INTERPRO_MMU_TAG, cammu_device, data_r, data_w, 0xffffffff) ADDRESS_MAP_END -// these maps represent the real main, i/o and boot spaces of the system -static ADDRESS_MAP_START(interpro_main_map, AS_0, 32, interpro_state) - AM_RANGE(0x00000000, 0x00ffffff) AM_RAM // 16M RAM - - AM_RANGE(0x40000000, 0x4000003f) AM_DEVICE(INTERPRO_MCGA_TAG, interpro_fmcc_device, map) +static ADDRESS_MAP_START(interpro_common_map, AS_0, 32, interpro_state) + AM_RANGE(0x40000000, 0x4000004f) AM_DEVICE(INTERPRO_MCGA_TAG, interpro_fmcc_device, map) AM_RANGE(0x4f007e00, 0x4f007eff) AM_DEVICE(INTERPRO_SGA_TAG, interpro_sga_device, map) AM_RANGE(0x7f000100, 0x7f00011f) AM_DEVICE8(INTERPRO_FDC_TAG, n82077aa_device, map, 0xff) AM_RANGE(0x7f000200, 0x7f0002ff) AM_DEVICE(INTERPRO_SRARB_TAG, interpro_srarb_device, map) - AM_RANGE(0x7f000300, 0x7f00030f) AM_READWRITE16(system_r, system_w, 0xffff) + + AM_RANGE(0x7f000300, 0x7f000303) AM_READ16(sreg_error_r, 0xffff) + AM_RANGE(0x7f000304, 0x7f000307) AM_READWRITE16(sreg_status_r, sreg_led_w, 0xffff) + AM_RANGE(0x7f000308, 0x7f00030b) AM_READWRITE16(sreg_ctrl1_r, sreg_ctrl1_w, 0xffff) + AM_RANGE(0x7f00030c, 0x7f00030f) AM_READWRITE16(sreg_ctrl2_r, sreg_ctrl2_w, 0xffff) + + AM_RANGE(0x7f00031c, 0x7f00031f) AM_READWRITE16(sreg_ctrl3_r, sreg_ctrl3_w, 0xffff) + AM_RANGE(0x7f000400, 0x7f00040f) AM_DEVREADWRITE8(INTERPRO_SCC1_TAG, scc85c30_device, ba_cd_inv_r, ba_cd_inv_w, 0xff) AM_RANGE(0x7f000410, 0x7f00041f) AM_DEVREADWRITE8(INTERPRO_SCC2_TAG, scc85230_device, ba_cd_inv_r, ba_cd_inv_w, 0xff) AM_RANGE(0x7f000500, 0x7f0006ff) AM_READWRITE8(rtc_r, rtc_w, 0xff) - AM_RANGE(0x7f000700, 0x7f00077f) AM_READ(idprom_r) + AM_RANGE(0x7f000700, 0x7f00077f) AM_READ8(idprom_r, 0xff) AM_RANGE(0x7f001000, 0x7f001fff) AM_READWRITE8(scsi_r, scsi_w, 0x0000ff00) AM_RANGE(0x7f0fff00, 0x7f0fffff) AM_DEVICE(INTERPRO_IOGA_TAG, interpro_ioga_device, map) + AM_RANGE(0x08000000, 0x08000fff) AM_NOP // bogus + AM_RANGE(0x87000000, 0x8700007f) AM_READ8(slot0_r, 0xff) + + // 2800 (CBUS?) slots are mapped as follows + AM_RANGE(0x87000000, 0x8700007f) AM_MIRROR(0x78000000) AM_READWRITE(unmapped_r, unmapped_w) +ADDRESS_MAP_END + +// these maps represent the real main, i/o and boot spaces of the system +static ADDRESS_MAP_START(interpro_main_map, AS_0, 32, interpro_state) + AM_RANGE(0x00000000, 0x00ffffff) AM_RAM AM_SHARE(RAM_TAG) + AM_RANGE(0x7f100000, 0x7f11ffff) AM_ROM AM_REGION(INTERPRO_EPROM_TAG, 0) AM_RANGE(0x7f180000, 0x7f1bffff) AM_ROM AM_REGION(INTERPRO_FLASH_TAG, 0) - AM_RANGE(0x08000000, 0x08000fff) AM_NOP // bogus - AM_RANGE(0x8f000000, 0x8f0fffff) AM_NOP // AM_READ(slot0_r) + AM_IMPORT_FROM(interpro_common_map) ADDRESS_MAP_END static ADDRESS_MAP_START(interpro_io_map, AS_1, 32, interpro_state) AM_RANGE(0x00000000, 0x00001fff) AM_DEVICE(INTERPRO_MMU_TAG, cammu_device, map) - AM_RANGE(0x40000000, 0x4000004f) AM_DEVICE(INTERPRO_MCGA_TAG, interpro_fmcc_device, map) - AM_RANGE(0x4f007e00, 0x4f007eff) AM_DEVICE(INTERPRO_SGA_TAG, interpro_sga_device, map) - - AM_RANGE(0x7f000100, 0x7f00011f) AM_DEVICE8(INTERPRO_FDC_TAG, n82077aa_device, map, 0xff) - AM_RANGE(0x7f000200, 0x7f0002ff) AM_DEVICE(INTERPRO_SRARB_TAG, interpro_srarb_device, map) - AM_RANGE(0x7f000300, 0x7f00030f) AM_READWRITE16(system_r, system_w, 0xffff) - AM_RANGE(0x7f000400, 0x7f00040f) AM_DEVREADWRITE8(INTERPRO_SCC1_TAG, scc85c30_device, ba_cd_inv_r, ba_cd_inv_w, 0xff) - AM_RANGE(0x7f000410, 0x7f00041f) AM_DEVREADWRITE8(INTERPRO_SCC2_TAG, scc85230_device, ba_cd_inv_r, ba_cd_inv_w, 0xff) - AM_RANGE(0x7f000500, 0x7f0006ff) AM_READWRITE8(rtc_r, rtc_w, 0xff) - AM_RANGE(0x7f000700, 0x7f00077f) AM_READ(idprom_r) - AM_RANGE(0x7f001000, 0x7f001fff) AM_READWRITE8(scsi_r, scsi_w, 0x0000ff00) - - AM_RANGE(0x7f0fff00, 0x7f0fffff) AM_DEVICE(INTERPRO_IOGA_TAG, interpro_ioga_device, map) - - AM_RANGE(0x08000000, 0x08000fff) AM_NOP // bogus - AM_RANGE(0x8f000000, 0x8f0fffff) AM_NOP // AM_READ(slot0_r) + AM_IMPORT_FROM(interpro_common_map) ADDRESS_MAP_END static ADDRESS_MAP_START(interpro_boot_map, AS_2, 32, interpro_state) @@ -360,7 +423,7 @@ static INPUT_PORTS_START(ip2800) INPUT_PORTS_END static MACHINE_CONFIG_START(ip2800) - MCFG_CPU_ADD(INTERPRO_CPU_TAG, CLIPPER_C400, XTAL_10MHz) + MCFG_CPU_ADD(INTERPRO_CPU_TAG, CLIPPER_C400, XTAL_12_5MHz) MCFG_CPU_PROGRAM_MAP(clipper_insn_map) MCFG_CPU_DATA_MAP(clipper_data_map) MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE(INTERPRO_IOGA_TAG, interpro_ioga_device, inta_cb) @@ -371,26 +434,47 @@ static MACHINE_CONFIG_START(ip2800) MCFG_DEVICE_ADDRESS_MAP(AS_2, interpro_boot_map) MCFG_CAMMU_SSW_CB(DEVREAD32(INTERPRO_CPU_TAG, clipper_device, ssw)) - // serial controllers and rs232 bus + MCFG_RAM_ADD(RAM_TAG) + MCFG_RAM_DEFAULT_SIZE("16M") + MCFG_RAM_EXTRA_OPTIONS("32M,64M,128M,256M") + + // TODO: work out serial port assignments for mouse, console, keyboard and ? + // first serial controller and devices MCFG_SCC85C30_ADD(INTERPRO_SCC1_TAG, XTAL_4_9152MHz, 0, 0, 0, 0) - MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE("rs232a", rs232_port_device, write_txd)) - MCFG_Z80SCC_OUT_TXDB_CB(DEVWRITELINE("rs232b", rs232_port_device, write_txd)) + MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(INTERPRO_SERIAL1_TAG, rs232_port_device, write_txd)) + MCFG_Z80SCC_OUT_TXDB_CB(DEVWRITELINE(INTERPRO_SERIAL2_TAG, rs232_port_device, write_txd)) MCFG_Z80SCC_OUT_INT_CB(DEVWRITELINE(INTERPRO_IOGA_TAG, interpro_ioga_device, ir11_w)) - MCFG_RS232_PORT_ADD("rs232a", default_rs232_devices, nullptr) + // is this the keyboard port? + MCFG_RS232_PORT_ADD(INTERPRO_SERIAL1_TAG, default_rs232_devices, nullptr) // "keyboard" MCFG_RS232_RXD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, rxa_w)) MCFG_RS232_DCD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, dcda_w)) MCFG_RS232_CTS_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, ctsa_w)) - // the following port is known as "port 2" - MCFG_RS232_PORT_ADD("rs232b", default_rs232_devices, "terminal") + // eprom uses this serial port for console (show_config calls it "port 2") + MCFG_RS232_PORT_ADD(INTERPRO_SERIAL2_TAG, default_rs232_devices, "terminal") MCFG_RS232_RXD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, rxb_w)) MCFG_RS232_DCD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, dcdb_w)) MCFG_RS232_CTS_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, ctsb_w)) + // second serial controller and devices MCFG_SCC85230_ADD(INTERPRO_SCC2_TAG, XTAL_4_9152MHz, 0, 0, 0, 0) + MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(INTERPRO_SERIAL3_TAG, rs232_port_device, write_txd)) + MCFG_Z80SCC_OUT_TXDB_CB(DEVWRITELINE(INTERPRO_SERIAL4_TAG, rs232_port_device, write_txd)) + MCFG_Z80SCC_OUT_INT_CB(DEVWRITELINE(INTERPRO_IOGA_TAG, interpro_ioga_device, ir11_w)) + + MCFG_RS232_PORT_ADD(INTERPRO_SERIAL3_TAG, default_rs232_devices, nullptr) + MCFG_RS232_RXD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, rxa_w)) + MCFG_RS232_DCD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, dcda_w)) + MCFG_RS232_CTS_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, ctsa_w)) + + MCFG_RS232_PORT_ADD(INTERPRO_SERIAL4_TAG, default_rs232_devices, nullptr) //"terminal") + MCFG_RS232_RXD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, rxb_w)) + MCFG_RS232_DCD_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, dcdb_w)) + MCFG_RS232_CTS_HANDLER(DEVWRITELINE(INTERPRO_SCC1_TAG, z80scc_device, ctsb_w)) + // real-time clock/non-volatile memory MCFG_MC146818_ADD(INTERPRO_RTC_TAG, XTAL_32_768kHz) MCFG_MC146818_UTC(true) @@ -408,9 +492,9 @@ static MACHINE_CONFIG_START(ip2800) #if NEW_SCSI MCFG_NSCSI_BUS_ADD(INTERPRO_SCSI_TAG) MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":0", interpro_scsi_devices, "harddisk", false) - MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":1", interpro_scsi_devices, "cdrom", false) + MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":1", interpro_scsi_devices, nullptr, false) MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":2", interpro_scsi_devices, nullptr, false) - MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":3", interpro_scsi_devices, nullptr, false) + MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":3", interpro_scsi_devices, "cdrom", false) MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":4", interpro_scsi_devices, nullptr, false) MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":5", interpro_scsi_devices, nullptr, false) MCFG_NSCSI_ADD(INTERPRO_SCSI_TAG ":6", interpro_scsi_devices, nullptr, false) @@ -419,7 +503,7 @@ static MACHINE_CONFIG_START(ip2800) #else MCFG_DEVICE_ADD(INTERPRO_SCSI_TAG, SCSI_PORT, 0) MCFG_SCSIDEV_ADD(INTERPRO_SCSI_TAG ":" SCSI_PORT_DEVICE1, "harddisk", SCSIHD, SCSI_ID_0) - MCFG_SCSIDEV_ADD(INTERPRO_SCSI_TAG ":" SCSI_PORT_DEVICE2, "cdrom", SCSICD, SCSI_ID_3) + MCFG_SCSIDEV_ADD(INTERPRO_SCSI_TAG ":" SCSI_PORT_DEVICE3, "cdrom", SCSICD, SCSI_ID_3) MCFG_DEVICE_ADD(INTERPRO_SCSI_ADAPTER_TAG, NCR539X, XTAL_12_5MHz) MCFG_LEGACY_SCSI_PORT(INTERPRO_SCSI_TAG) diff --git a/src/mame/includes/interpro.h b/src/mame/includes/interpro.h index d2a45e24225..e4163ae1278 100644 --- a/src/mame/includes/interpro.h +++ b/src/mame/includes/interpro.h @@ -9,6 +9,8 @@ #include "cpu/clipper/clipper.h" #include "machine/cammu.h" +#include "machine/ram.h" + #include "machine/interpro_ioga.h" #include "machine/interpro_mcga.h" #include "machine/interpro_sga.h" @@ -39,7 +41,11 @@ #define INTERPRO_RTC_TAG "rtc" #define INTERPRO_SCC1_TAG "scc1" +#define INTERPRO_SERIAL1_TAG "serial1" +#define INTERPRO_SERIAL2_TAG "serial2" #define INTERPRO_SCC2_TAG "scc2" +#define INTERPRO_SERIAL3_TAG "serial3" +#define INTERPRO_SERIAL4_TAG "serial4" #define INTERPRO_EPROM_TAG "eprom" #define INTERPRO_FLASH_TAG "flash" #define INTERPRO_TERMINAL_TAG "terminal" @@ -52,36 +58,6 @@ #define INTERPRO_SGA_TAG "sga" #define INTERPRO_SRARB_TAG "srarb" -// system board register offsets -#define SREG_LED 0 -#define SREG_ERROR 0 -#define SREG_STATUS 1 -#define SREG_CTRL1 2 -#define SREG_CTRL2 3 - -// control register 1 -#define CTRL1_FLOPLOW 0x0001 -#define CTRL1_FLOPRDY 0x0002 -#define CTRL1_LEDENA 0x0004 -#define CTRL1_LEDDP 0x0008 -#define CTRL1_ETHLOOP 0x0010 -#define CTRL1_ETHDTR 0x0020 -#define CTRL1_ETHRMOD 0x0040 -#define CTRL1_CLIPRESET 0x0040 -#define CTRL1_FIFOACTIVE 0x0080 - -// control register 2 -#define CTRL2_PWRUP 0x0001 -#define CTRL2_PWRENA 0x0002 -#define CTRL2_HOLDOFF 0x0004 -#define CTRL2_EXTNMIENA 0x0008 -#define CTRL2_COLDSTART 0x0010 -#define CTRL2_RESET 0x0020 -#define CTRL2_BUSENA 0x0040 -#define CTRL2_FRCPARITY 0x0080 -#define CTRL2_FLASHEN 0x0080 -#define CTRL2_WMASK 0x000f - class interpro_state : public driver_device { public: @@ -89,6 +65,7 @@ public: : driver_device(mconfig, type, tag), m_maincpu(*this, INTERPRO_CPU_TAG), m_mmu(*this, INTERPRO_MMU_TAG), + m_ram(*this, RAM_TAG), m_scc1(*this, INTERPRO_SCC1_TAG), m_scc2(*this, INTERPRO_SCC2_TAG), m_rtc(*this, INTERPRO_RTC_TAG), @@ -108,6 +85,8 @@ public: required_device<clipper_device> m_maincpu; required_device<cammu_device> m_mmu; + required_device<ram_device> m_ram; + // FIXME: not sure which one is the escc required_device<z80scc_device> m_scc1; required_device<z80scc_device> m_scc2; @@ -127,14 +106,73 @@ public: DECLARE_DRIVER_INIT(ip2800); - DECLARE_WRITE16_MEMBER(system_w); - DECLARE_READ16_MEMBER(system_r); + enum sreg_error_mask + { + ERROR_BPID4 = 0x0001, + ERROR_SRXMMBE = 0x0002, + ERROR_SRXHOG = 0x0004, + ERROR_SRXNEM = 0x0008, + ERROR_SRXVALID = 0x0010, + ERROR_CBUSNMI = 0x0020, + ERROR_CBUSBG = 0x00c0, + ERROR_BG = 0x0070, + ERROR_BUSHOG = 0x0080 + }; + DECLARE_READ16_MEMBER(sreg_error_r); + DECLARE_WRITE16_MEMBER(sreg_led_w) { m_sreg_led = data; } + + enum sreg_status_mask + { + STATUS_YELLOW_ZONE = 0x0001, + STATUS_SRNMI = 0x0002, + STATUS_PWRLOSS = 0x0004, + STATUS_RED_ZONE = 0x0008, + STATUS_BP = 0x00f0 + }; + DECLARE_READ16_MEMBER(sreg_status_r) { return m_sreg_status; } + + enum sreg_ctrl1_mask + { + CTRL1_FLOPLOW = 0x0001, + CTRL1_FLOPRDY = 0x0002, + CTRL1_LEDENA = 0x0004, + CTRL1_LEDDP = 0x0008, + CTRL1_ETHLOOP = 0x0010, + CTRL1_ETHDTR = 0x0020, + CTRL1_ETHRMOD = 0x0040, + CTRL1_CLIPRESET = 0x0040, + CTRL1_FIFOACTIVE = 0x0080 + }; + DECLARE_READ16_MEMBER(sreg_ctrl1_r) { return m_sreg_ctrl1; } + DECLARE_WRITE16_MEMBER(sreg_ctrl1_w); + + enum sreg_ctrl2_mask + { + CTRL2_PWRUP = 0x0001, + CTRL2_PWRENA = 0x0002, + CTRL2_HOLDOFF = 0x0004, + CTRL2_EXTNMIENA = 0x0008, + CTRL2_COLDSTART = 0x0010, + CTRL2_RESET = 0x0020, + CTRL2_BUSENA = 0x0040, + CTRL2_FRCPARITY = 0x0080, + CTRL2_FLASHEN = 0x0080, + + CTRL2_WMASK = 0x000f + }; + DECLARE_READ16_MEMBER(sreg_ctrl2_r) { return m_sreg_ctrl2; } + DECLARE_WRITE16_MEMBER(sreg_ctrl2_w); + DECLARE_READ16_MEMBER(sreg_ctrl3_r) { return m_sreg_ctrl3; } + DECLARE_WRITE16_MEMBER(sreg_ctrl3_w) { m_sreg_ctrl3 = data; } DECLARE_WRITE8_MEMBER(rtc_w); DECLARE_READ8_MEMBER(rtc_r); - DECLARE_READ32_MEMBER(idprom_r); - DECLARE_READ32_MEMBER(slot0_r); + DECLARE_READ8_MEMBER(idprom_r); + DECLARE_READ8_MEMBER(slot0_r); + + DECLARE_READ32_MEMBER(unmapped_r); + DECLARE_WRITE32_MEMBER(unmapped_w); DECLARE_READ8_MEMBER(scsi_r); DECLARE_WRITE8_MEMBER(scsi_w); @@ -148,7 +186,13 @@ protected: virtual void machine_reset() override; private: - u16 m_system_reg[4]; + u16 m_sreg_error; + u16 m_sreg_led; + u16 m_sreg_status; + u16 m_sreg_ctrl1; + u16 m_sreg_ctrl2; + + u16 m_sreg_ctrl3; }; #endif // MAME_INCLUDES_INTERPRO_H diff --git a/src/mame/machine/interpro_ioga.cpp b/src/mame/machine/interpro_ioga.cpp index e31c8e7c633..937072f346f 100644 --- a/src/mame/machine/interpro_ioga.cpp +++ b/src/mame/machine/interpro_ioga.cpp @@ -45,6 +45,7 @@ DEVICE_ADDRESS_MAP_START(map, 32, interpro_ioga_device) AM_RANGE(0x1c, 0x1f) AM_READWRITE(dma_plotter_eosl_r, dma_plotter_eosl_w) AM_RANGE(0x20, 0x2f) AM_READWRITE(dma_scsi_r, dma_scsi_w) AM_RANGE(0x30, 0x3f) AM_READWRITE(dma_floppy_r, dma_floppy_w) + AM_RANGE(0x40, 0x57) AM_READWRITE(dma_serial_r, dma_serial_w) AM_RANGE(0x5c, 0x7f) AM_READWRITE16(icr_r, icr_w, 0xffffffff) AM_RANGE(0x80, 0x83) AM_READWRITE16(icr18_r, icr18_w, 0x0000ffff) @@ -59,6 +60,7 @@ DEVICE_ADDRESS_MAP_START(map, 32, interpro_ioga_device) AM_RANGE(0x9c, 0x9f) AM_READWRITE16(arbctl_r, arbctl_w, 0x0000ffff) AM_RANGE(0xa8, 0xab) AM_READWRITE(timer3_r, timer3_w) + AM_RANGE(0xac, 0xaf) AM_READWRITE(bus_timeout_r, bus_timeout_w) // boot code writes 0x64 AM_RANGE(0xb0, 0xbf) AM_READWRITE16(softint_vector_r, softint_vector_w, 0xffffffff) ADDRESS_MAP_END @@ -133,8 +135,8 @@ void interpro_ioga_device::device_start() m_timer[2] = timer_alloc(IOGA_TIMER_2); m_timer[3] = timer_alloc(IOGA_TIMER_3); - for (auto & elem : m_timer) - elem->enable(false); + for (auto & timer : m_timer) + timer->enable(false); // allocate timer for DMA controller m_dma_timer = timer_alloc(IOGA_TIMER_DMA); @@ -243,7 +245,7 @@ void interpro_ioga_device::device_timer(emu_timer &timer, device_timer_id id, in { case IOGA_TIMER_0: m_timer_reg[0]++; - set_irq_line(IOGA_TIMER0_IRQ, ASSERT_LINE); + m_hwicr[IOGA_TIMER0_IRQ] |= IOGA_INTERRUPT_PENDING; break; case IOGA_TIMER_1: @@ -260,7 +262,7 @@ void interpro_ioga_device::device_timer(emu_timer &timer, device_timer_id id, in timer.set_param(true); // throw an interrupt - set_irq_line(IOGA_TIMER1_IRQ, ASSERT_LINE); + m_hwicr[IOGA_TIMER1_IRQ] |= IOGA_INTERRUPT_PENDING; } break; @@ -278,7 +280,7 @@ void interpro_ioga_device::device_timer(emu_timer &timer, device_timer_id id, in timer.set_param(true); // throw an interrupt - set_irq_line(IOGA_TIMER3_IRQ, ASSERT_LINE); + m_hwicr[IOGA_TIMER3_IRQ] |= IOGA_INTERRUPT_PENDING; } break; @@ -361,11 +363,11 @@ void interpro_ioga_device::set_nmi_line(int state) m_nmictrl &= ~IOGA_NMI_ENABLE_IN; } #endif - m_nmictrl |= IOGA_NMI_PENDING; + m_nmictrl |= NMI_PENDING; break; case CLEAR_LINE: - m_nmictrl &= ~IOGA_NMI_PENDING; + m_nmictrl &= ~NMI_PENDING; break; } } @@ -462,7 +464,7 @@ IRQ_CALLBACK_MEMBER(interpro_ioga_device::inta_cb) case INPUT_LINE_NMI: // clear pending flag - m_nmictrl &= ~IOGA_NMI_PENDING; + m_nmictrl &= ~NMI_PENDING; m_active_interrupt_type = IOGA_INTERRUPT_NONE; break; } @@ -488,25 +490,33 @@ void interpro_ioga_device::interrupt_clock() return; // check for pending nmi - if (m_nmictrl & IOGA_NMI_PENDING) + if (m_nmictrl & NMI_PENDING) { m_active_interrupt_type = IOGA_INTERRUPT_NMI; nmi(ASSERT_LINE); return; } - // check for any pending and enabled hardware interrupts + // scan all hardware interrupts for (int i = 0; i < IOGA_INTERRUPT_COUNT; i++) { - if ((m_hwicr[i] & irq_enable_mask[i]) && (m_hwicr[i] & IOGA_INTERRUPT_PENDING)) + // check if there is a pending interrupt + if (m_hwicr[i] & IOGA_INTERRUPT_PENDING) { - LOG_HWINT(i, "accepting interrupt %d - %s (%s)\n", i, interrupt_source[i], m_int_line & (1 << i) ? "real" : "forced"); + // check if from an external device or internal to ioga + bool external = m_int_line & (1 << i); - m_active_interrupt_type = IOGA_INTERRUPT_EXTERNAL; // TODO: flag internal/external - m_active_interrupt_number = i; + // check if masked + if (m_hwicr[i] & irq_enable_mask[i]) //(external ? IRQ_ENABLE_EXTERNAL : IRQ_ENABLE_INTERNAL)) + { + LOG_HWINT(i, "accepting interrupt %d - %s (%s)\n", i, interrupt_source[i], external ? "external" : "internal"); - irq(ASSERT_LINE); - return; + m_active_interrupt_type = external ? IOGA_INTERRUPT_EXTERNAL : IOGA_INTERRUPT_INTERNAL; + m_active_interrupt_number = i; + + irq(ASSERT_LINE); + return; + } } } @@ -598,6 +608,8 @@ WRITE8_MEMBER(interpro_ioga_device::softint_w) WRITE8_MEMBER(interpro_ioga_device::nmictrl_w) { + LOG_INTERRUPT("nmictrl = 0x%02x (%s)\n", data, machine().describe_context()); + #if 0 // save the existing value uint8_t previous = m_nmictrl; @@ -606,24 +618,25 @@ WRITE8_MEMBER(interpro_ioga_device::nmictrl_w) m_nmictrl = data; // force an nmi when pending bit is written low - if (previous & IOGA_NMI_PENDING && !(data & IOGA_NMI_PENDING)) + if (previous & NMI_PENDING && !(data & NMI_PENDING)) set_nmi_line(ASSERT_LINE); #else - if (data & IOGA_NMI_PENDING) +#if 0 + if (data & NMI_PENDING) { m_nmi_forced = true; - m_nmictrl = (m_nmictrl & IOGA_NMI_PENDING) | (data & ~IOGA_NMI_PENDING); + m_nmictrl = (m_nmictrl & NMI_PENDING) | (data & ~NMI_PENDING); } else if (m_nmi_forced) { m_nmi_forced = false; - m_nmictrl = data | IOGA_NMI_PENDING; + m_nmictrl = data | NMI_PENDING; } else m_nmictrl = data; - - //m_nmictrl = data & ~IOGA_NMI_PENDING; +#endif + m_nmictrl = data & ~NMI_PENDING; #endif } @@ -647,47 +660,118 @@ void interpro_ioga_device::dma_clock(int channel) { // transfer data between device and main memory - // TODO: figure out what indicates dma write (memory -> device) - // TODO: implement multiple dma channels // TODO: virtual memory? - if (!m_dma_channel[channel].dma_active) + // handle device to memory dma + if (m_dma_channel[channel].drq_state) { - LOG_DMA(channel, "dma: transfer started, channel = %d, control 0x%08x, real address 0x%08x count 0x%08x\n", - channel, m_dma_channel[channel].control, m_dma_channel[channel].real_address, m_dma_channel[channel].transfer_count); - m_dma_channel[channel].dma_active = true; - } + if (!m_dma_channel[channel].dma_active) + { + LOG_DMA(channel, "dma: transfer from device started, channel = %d, control 0x%08x, real address 0x%08x count 0x%08x\n", + channel, m_dma_channel[channel].control, m_dma_channel[channel].real_address, m_dma_channel[channel].transfer_count); + m_dma_channel[channel].dma_active = true; + } - // while the device is requesting a data transfer and the transfer count is not zero - while (m_dma_channel[channel].drq_state && m_dma_channel[channel].transfer_count) - { - // transfer a byte between device and memory - if (true) + // while the device is requesting a data transfer and the transfer count is not zero + while (m_dma_channel[channel].drq_state && m_dma_channel[channel].transfer_count) + { + // transfer from the device to memory m_memory_space->write_byte(m_dma_channel[channel].real_address, m_dma_channel[channel].device_r()); - else - m_dma_channel[channel].device_w(m_memory_space->read_byte(m_dma_channel[channel].real_address)); - // increment addresses and decrement count - m_dma_channel[channel].real_address++; - m_dma_channel[channel].virtual_address++; - m_dma_channel[channel].transfer_count--; - } + // increment addresses and decrement count + m_dma_channel[channel].real_address++; + m_dma_channel[channel].virtual_address++; + m_dma_channel[channel].transfer_count--; + } - // if there are no more bytes remaining, terminate the transfer - if (m_dma_channel[channel].transfer_count == 0) + // if there are no more bytes remaining, terminate the transfer + if (m_dma_channel[channel].transfer_count == 0) + { + LOG_DMA(channel, "dma: transfer from device completed, control 0x%08x, real address 0x%08x count 0x%08x\n", + m_dma_channel[channel].control, m_dma_channel[channel].real_address, m_dma_channel[channel].transfer_count); + + if (channel == IOGA_DMA_FLOPPY) + { + LOG_DMA(channel, "dma: asserting fdc terminal count line\n"); + + m_fdc_tc_func(ASSERT_LINE); + m_fdc_tc_func(CLEAR_LINE); + } + + m_dma_channel[channel].dma_active = false; + } + } + else // memory to device dma { - LOG_DMA(channel, "dma: transfer completed, control 0x%08x, real address 0x%08x count 0x%08x\n", - m_dma_channel[channel].control, m_dma_channel[channel].real_address, m_dma_channel[channel].transfer_count); + // get access to the bus + { + // iogadiag test 7.0265 + u32 mask = 0; + + switch (channel) + { + case IOGA_DMA_PLOTTER: + mask = ARBCTL_BGR_PLOT; + break; + + case IOGA_DMA_SCSI: + mask = ARBCTL_BGR_SCSI; + break; + + case IOGA_DMA_FLOPPY: + mask = ARBCTL_BGR_FDC; + break; + } - if (channel == IOGA_DMA_FLOPPY) + // if bus grant is not enabled, set the busy flag + if (!(m_arbctl & mask)) + { + LOG_DMA(channel, "dma: delay for bus grant channel %d\n", channel); + + m_dma_channel[channel].control |= IOGA_DMA_CTRL_BUSY; + m_dma_timer->adjust(attotime::from_hz(clock()), channel); + + return; + } + else + m_dma_channel[channel].control &= ~IOGA_DMA_CTRL_BUSY; + } + + if (!m_dma_channel[channel].dma_active) + { + LOG_DMA(channel, "dma: transfer to device begun, channel %d, control 0x%08x, real address 0x%08x, count 0x%08x\n", + channel, m_dma_channel[channel].control, m_dma_channel[channel].real_address, m_dma_channel[channel].transfer_count); + m_dma_channel[channel].dma_active = true; + } + + while (m_dma_channel[channel].transfer_count) { - LOG_DMA(channel, "dma: asserting fdc terminal count line\n"); + // transfer from memory to the device + m_dma_channel[channel].device_w(m_memory_space->read_byte(m_dma_channel[channel].real_address)); - m_fdc_tc_func(ASSERT_LINE); - m_fdc_tc_func(CLEAR_LINE); + // increment addresses and decrement count + m_dma_channel[channel].real_address++; + m_dma_channel[channel].virtual_address++; + m_dma_channel[channel].transfer_count--; } + // TODO: do we need the floppy terminal count line here? + + m_dma_channel[channel].control |= IOGA_DMA_CTRL_TCZERO; m_dma_channel[channel].dma_active = false; + + // TODO: do we need to throw an interrupt? + LOG_DMA(channel, "dma: transfer to device ended, channel %d, control 0x%08x, real address 0x%08x, count 0x%08x\n", + channel, m_dma_channel[channel].control, m_dma_channel[channel].real_address, m_dma_channel[channel].transfer_count); + + // dma ctrl = 0xbf000600 + // = 0xff000600 + // = 0x63xxxxxx + // 600 = scsi channel? + // b = 1011 + // f = 1111 + // 6 = 0101 + // -> bit 0x4 = read/write? } } @@ -739,68 +823,57 @@ void interpro_ioga_device::dma_w(address_space &space, offs_t offset, u32 data, switch (offset) { case 0: + LOG_DMA(channel, "channel %d real address = 0x%08x (%s)\n", channel, data, machine().describe_context()); m_dma_channel[channel].real_address = data; break; case 1: + LOG_DMA(channel, "channel %d virtual address = 0x%08x (%s)\n", channel, data, machine().describe_context()); m_dma_channel[channel].virtual_address = data & ~0x3; break; case 2: + LOG_DMA(channel, "channel %d transfer count = 0x%08x (%s)\n", channel, data, machine().describe_context()); m_dma_channel[channel].transfer_count = data; break; case 3: + LOG_DMA(channel, "channel %d control = 0x%08x (%s)\n", channel, data, machine().describe_context()); m_dma_channel[channel].control = data & IOGA_DMA_CTRL_WMASK; - logerror("dma: channel = %d, control = 0x%08x, ra = 0x%08x, va = 0x%08x, tc = 0x%08x at %s\n", - channel, data, m_dma_channel[channel].real_address, m_dma_channel[channel].virtual_address, m_dma_channel[channel].transfer_count, machine().describe_context()); - - // scsidiag - // dma ctrl = 0xbf000600 - // = 0xff000600 - // = 0x63xxxxxx - // 600 = scsi channel? - // b = 1011 - // f = 1111 - // 6 = 0101 - // -> bit 0x4 = read/write? + // start dma transfer if necessary + if (data & IOGA_DMA_CTRL_START) + m_dma_timer->adjust(attotime::from_hz(clock()), channel); + break; + } +} +u32 interpro_ioga_device::dma_serial_r(address_space &space, offs_t offset, u32 mem_mask) +{ + int channel = offset >> 1; - // mask + if (offset & 1) + return m_dma_serial[channel].control; + else + return m_dma_serial[channel].address; +} - // iogadiag test 7.0265 - if (data & IOGA_DMA_CTRL_START) - { - uint32_t mask = 0; +void interpro_ioga_device::dma_serial_w(address_space &space, offs_t offset, u32 data, u32 mem_mask) +{ + int channel = offset >> 1; - switch (channel) - { - case IOGA_DMA_PLOTTER: - mask = IOGA_ARBCTL_BGR_PLOT; - break; + if (offset & 1) + m_dma_serial[channel].control = (m_dma_serial[channel].control & ~mem_mask) | data; + else + m_dma_serial[channel].address = (m_dma_serial[channel].address & ~mem_mask) | data; +} - case IOGA_DMA_SCSI: - mask = IOGA_ARBCTL_BGR_SCSI; - break; +READ32_MEMBER(interpro_ioga_device::error_businfo_r) +{ + u32 result = m_error_businfo; - case IOGA_DMA_FLOPPY: - mask = IOGA_ARBCTL_BGR_FDC; - break; - } + // clear register after reading + m_error_businfo = 0; - // if bus grant is not enabled, set the busy flag - if (!(m_arbctl & mask)) - m_dma_channel[channel].control |= IOGA_DMA_CTRL_BUSY; -#if 0 - // flip transfer count zero on immediately if needed - if (m_dma_channel[channel].transfer_count == 0) - { - m_dma_channel[channel].control |= IOGA_DMA_CTRL_TCZERO; - set_irq_line(2, ASSERT_LINE); - } -#endif - } - break; - } -} + return result; +}
\ No newline at end of file diff --git a/src/mame/machine/interpro_ioga.h b/src/mame/machine/interpro_ioga.h index 399dabf8089..fd0f91acee0 100644 --- a/src/mame/machine/interpro_ioga.h +++ b/src/mame/machine/interpro_ioga.h @@ -47,11 +47,6 @@ #define IOGA_INTERRUPT_NEGPOL 0x0800 #define IOGA_INTERRUPT_ENABLE_INTERNAL 0x1000 -#define IOGA_NMI_EDGE 0x02 -#define IOGA_NMI_PENDING 0x08 -#define IOGA_NMI_ENABLE_IN 0x10 -#define IOGA_NMI_ENABLE (IOGA_NMI_EDGE | IOGA_NMI_ENABLE_IN) - #define IOGA_INTERRUPT_NONE 0 #define IOGA_INTERRUPT_NMI 1 #define IOGA_INTERRUPT_INTERNAL 2 @@ -85,22 +80,10 @@ #define IOGA_DMA_CTRL_UNK2 0x67000600 // forced berr with nmi and interrupts disabled #define IOGA_DMA_CTRL_UNK3 0xbf000600 // set by scsidiag before executing scsi "transfer information" command - // read values // iogadiag expects 0x64400800 after forced berr with nmi/interrupts disabled -// bus arbitration bus grant bits -#define IOGA_ARBCTL_BGR_ETHC 0x0001 -#define IOGA_ARBCTL_BGR_SCSI 0x0002 -#define IOGA_ARBCTL_BGR_PLOT 0x0004 -#define IOGA_ARBCTL_BGR_FDC 0x0008 -#define IOGA_ARBCTL_BGR_SER0 0x0010 -#define IOGA_ARBCTL_BGR_SER1 0x0020 -#define IOGA_ARBCTL_BGR_SER2 0x0040 -#define IOGA_ARBCTL_BGR_ETHB 0x0080 -#define IOGA_ARBCTL_BGR_ETHA 0x0100 - class interpro_ioga_device : public device_t { public: @@ -141,6 +124,19 @@ public: DECLARE_READ32_MEMBER(timer_prescaler_r) { return m_prescaler; } DECLARE_READ32_MEMBER(timer0_r) { return m_timer_reg[0]; } DECLARE_READ32_MEMBER(timer1_r); + + enum arbctl_mask + { + ARBCTL_BGR_ETHC = 0x0001, + ARBCTL_BGR_SCSI = 0x0002, + ARBCTL_BGR_PLOT = 0x0004, + ARBCTL_BGR_FDC = 0x0008, + ARBCTL_BGR_SER0 = 0x0010, + ARBCTL_BGR_SER1 = 0x0020, + ARBCTL_BGR_SER2 = 0x0040, + ARBCTL_BGR_ETHB = 0x0080, + ARBCTL_BGR_ETHA = 0x0100 + }; DECLARE_READ16_MEMBER(arbctl_r) { return m_arbctl; } DECLARE_WRITE16_MEMBER(arbctl_w) { m_arbctl = data; } DECLARE_READ32_MEMBER(timer2_r) { return m_timer_reg[2]; } @@ -160,6 +156,14 @@ public: DECLARE_WRITE32_MEMBER(timer2_w) { write_timer(2, data, IOGA_TIMER_2); } DECLARE_WRITE32_MEMBER(timer3_w) { write_timer(3, data, IOGA_TIMER_3); } + enum hwicr_mask + { + IRQ_PENDING = 0x0100, + IRQ_ENABLE_EXTERNAL = 0x0200, + IRQ_EDGE = 0x0400, + IRQ_NEGPOL = 0x0800, + IRQ_ENABLE_INTERNAL = 0x1000 + }; DECLARE_READ16_MEMBER(icr_r) { return m_hwicr[offset]; } DECLARE_WRITE16_MEMBER(icr_w); DECLARE_READ16_MEMBER(icr18_r) { return icr_r(space, 18, mem_mask); } @@ -167,6 +171,15 @@ public: DECLARE_READ8_MEMBER(softint_r) { return m_softint; } DECLARE_WRITE8_MEMBER(softint_w); + + enum nmictrl_mask + { + NMI_EDGE = 0x02, + NMI_PENDING = 0x08, + NMI_ENABLE_IN = 0x10, + + NMI_ENABLE = NMI_ENABLE_IN | NMI_EDGE + }; DECLARE_READ8_MEMBER(nmictrl_r) { return m_nmictrl; } DECLARE_WRITE8_MEMBER(nmictrl_w); @@ -180,14 +193,36 @@ public: DECLARE_READ32_MEMBER(dma_floppy_r) { return dma_r(space, offset, mem_mask, IOGA_DMA_FLOPPY); } DECLARE_WRITE32_MEMBER(dma_floppy_w) { dma_w(space, offset, data, mem_mask, IOGA_DMA_FLOPPY); } + DECLARE_READ32_MEMBER(dma_serial_r); + DECLARE_WRITE32_MEMBER(dma_serial_w); + DECLARE_READ32_MEMBER(dma_plotter_eosl_r) { return m_dma_plotter_eosl; } DECLARE_WRITE32_MEMBER(dma_plotter_eosl_w) { m_dma_plotter_eosl = data; } DECLARE_READ32_MEMBER(error_address_r) { return m_error_address; } - DECLARE_READ32_MEMBER(error_businfo_r) { return m_error_businfo; } + + enum error_businfo_mask + { + BINFO_CT = 0x003f, + BINFO_TAG = 0x01c0, + BINFO_BG = 0x0e00, + BINFO_BERR = 0x1000, + BINFO_MMBE = 0x2000, + BINFO_SNAPOK = 0x4000, + BINFO_MSBE = 0x8000 + }; + enum error_businfo_bg + { + BINFO_BG_IOD = 0x0200, + BINFO_BG_ICAMMU = 0x0400, + BINFO_BG_DCAMMU = 0x0800, + BINFO_BG_SRMASTER = 0x0c00 + }; + DECLARE_READ32_MEMBER(error_businfo_r); + DECLARE_READ32_MEMBER(bus_timeout_r) { return m_bus_timeout; } + DECLARE_WRITE32_MEMBER(bus_timeout_w) { m_bus_timeout = data; } DECLARE_WRITE32_MEMBER(bus_error) { m_error_address = data; m_error_businfo = offset; } - //void bus_error(uint32_t address, uint32_t cycle_type) { m_error_address = address; m_error_businfo = cycle_type; } protected: // device-level overrides @@ -231,6 +266,12 @@ private: } m_dma_channel[IOGA_DMA_CHANNELS]; u32 m_dma_plotter_eosl; + struct serial_dma + { + u32 address; + u32 control; + } m_dma_serial[3]; + devcb_write_line m_fdc_tc_func; u32 m_active_interrupt_type; @@ -260,6 +301,7 @@ private: u32 m_error_address; u32 m_error_businfo; + u32 m_bus_timeout; emu_timer *m_ioga_clock; int m_nmi_state; diff --git a/src/mame/machine/interpro_mcga.cpp b/src/mame/machine/interpro_mcga.cpp index 810d73f0087..66ef3f30411 100644 --- a/src/mame/machine/interpro_mcga.cpp +++ b/src/mame/machine/interpro_mcga.cpp @@ -41,6 +41,7 @@ DEVICE_ADDRESS_MAP_START(map, 32, interpro_fmcc_device) AM_RANGE(0x28, 0x2b) AM_READWRITE16(reg28_r, reg28_w, 0xffff) AM_RANGE(0x30, 0x33) AM_READWRITE16(reg30_r, reg30_w, 0xffff) AM_RANGE(0x38, 0x3b) AM_READWRITE16(memsize_r, memsize_w, 0xffff) + AM_RANGE(0x40, 0x43) AM_NOP // unknown AM_RANGE(0x48, 0x4b) AM_READWRITE16(error_control_r, error_control_w, 0xffff) ADDRESS_MAP_END @@ -69,29 +70,29 @@ void interpro_mcga_device::device_start() void interpro_mcga_device::device_reset() { m_reg[0] = 0x00ff; - m_control = MCGA_CTRL_ENREFRESH | MCGA_CTRL_CBITFRCSUB | MCGA_CTRL_CBITFRCRD; + m_control = CONTROL_ENREFRESH | CONTROL_CBITFRCSUB | CONTROL_CBITFRCRD; m_reg[1] = 0x00ff; m_memsize = 0x0340; } WRITE16_MEMBER(interpro_mcga_device::control_w) { - m_control = data & MCGA_CTRL_MASK; + m_control = data & CONTROL_MASK; // HACK: set or clear error status depending on ENMMBE bit - if (data & MCGA_CTRL_ENMMBE) - m_error |= MCGA_ERROR_VALID; - // else - // error &= ~MCGA_ERROR_VALID; + if (data & CONTROL_ENMMBE) + m_error |= ERROR_VALID; + //else + // m_error &= ~ERROR_VALID; } WRITE16_MEMBER(interpro_fmcc_device::control_w) { - m_control = data & FMCC_CTRL_MASK; + m_control = data & CONTROL_MASK; // HACK: set or clear error status depending on ENMMBE bit - if (data & MCGA_CTRL_ENMMBE) - m_error |= MCGA_ERROR_VALID; - // else - // error &= ~MCGA_ERROR_VALID; + if (data & CONTROL_ENMMBE) + m_error |= ERROR_VALID; + //else + // m_error &= ~ERROR_VALID; } diff --git a/src/mame/machine/interpro_mcga.h b/src/mame/machine/interpro_mcga.h index 22535746ddc..780ea8c8233 100644 --- a/src/mame/machine/interpro_mcga.h +++ b/src/mame/machine/interpro_mcga.h @@ -6,23 +6,6 @@ #pragma once -// mcga control register -#define MCGA_CTRL_OPTMASK 0x0003 -#define MCGA_CTRL_CBITFRCRD 0x0004 -#define MCGA_CTRL_CBITFRCSUB 0x0008 -#define MCGA_CTRL_ENREFRESH 0x0010 -#define MCGA_CTRL_ENMSBE 0x0100 -#define MCGA_CTRL_ENMMBE 0x0200 -#define MCGA_CTRL_ENECC 0x0400 -#define MCGA_CTRL_WRPROT 0x8000 - -// rom writes bit 0x80 to test if fmcc or mcga -#define MCGA_CTRL_MASK 0x871f -#define FMCC_CTRL_MASK 0x8fff - -// mcga error register -#define MCGA_ERROR_VALID 0x00008000 - class interpro_mcga_device : public device_t { public: @@ -32,8 +15,31 @@ public: DECLARE_READ16_MEMBER(reg00_r) { return m_reg[0]; } DECLARE_WRITE16_MEMBER(reg00_w) { m_reg[0] = data; } + + enum control_mask + { + CONTROL_OPTMASK = 0x0003, + CONTROL_CBITFRCRD = 0x0004, + CONTROL_CBITFRCSUB = 0x0008, + CONTROL_ENREFRESH = 0x0010, + CONTROL_ENMSBE = 0x0100, + CONTROL_ENMMBE = 0x0200, + CONTROL_ENECC = 0x0400, + CONTROL_WRPROT = 0x8000, + + CONTROL_MASK = 0x871f + }; DECLARE_READ16_MEMBER(control_r) { return m_control; } virtual DECLARE_WRITE16_MEMBER(control_w); + + enum error_mask + { + ERROR_SYND = 0x00ff, + ERROR_MMBE = 0x0100, + ERROR_MSBE = 0x0200, + ERROR_ADDR = 0x1c00, + ERROR_VALID = 0x8000 + }; DECLARE_READ16_MEMBER(error_r) { return m_error; } DECLARE_WRITE16_MEMBER(error_w) { m_error = data; } DECLARE_READ8_MEMBER(frcrd_r) { return m_frcrd; } @@ -44,6 +50,11 @@ public: DECLARE_WRITE16_MEMBER(reg28_w) { m_reg[1] = data; } DECLARE_READ16_MEMBER(reg30_r) { return m_reg[2]; } DECLARE_WRITE16_MEMBER(reg30_w) { m_reg[2] = data; } + + enum memsize_mask + { + MEMSIZE_ADDR = 0x007f + }; DECLARE_READ16_MEMBER(memsize_r) { return m_memsize; } DECLARE_WRITE16_MEMBER(memsize_w) { m_memsize = data; } @@ -69,8 +80,38 @@ public: virtual DECLARE_ADDRESS_MAP(map, 32) override; + enum control_mask + { + CONTROL_CBITFRCRD = 0x0004, + CONTROL_CBITFRCSUB = 0x0008, + CONTROL_ENREFRESH = 0x0010, + CONTROL_ENMSBENMI = 0x0020, + CONTROL_ENMMBENMI = 0x0040, + CONTROL_ENSTICKY = 0x0080, + CONTROL_ENMERR = 0x0100, + CONTROL_ENMMBE = 0x0200, + CONTROL_ENECC = 0x0400, + CONTROL_ENRMWCOR = 0x0800, + CONTROL_WRPROT = 0x8000, + + CONTROL_MASK = 0x8fff + }; DECLARE_WRITE16_MEMBER(control_w) override; + enum error_mask + { + ERROR_SYND = 0x00ff, + ERROR_MMBE = 0x0100, + ERROR_MSBE = 0x0200, + ERROR_MTYPE = 0x0400, + ERROR_VALID = 0x8000 + }; + + enum error_control_mask + { + ERROR_CONTROL_CYCLE = 0x003f, + ERROR_CONTROL_TAG = 0x01c0 + }; DECLARE_READ16_MEMBER(error_control_r) { return m_error_control; } DECLARE_WRITE16_MEMBER(error_control_w) { m_error_control = data; } diff --git a/src/mame/machine/interpro_sga.cpp b/src/mame/machine/interpro_sga.cpp index 8cc35fd82b3..b33dfcce297 100644 --- a/src/mame/machine/interpro_sga.cpp +++ b/src/mame/machine/interpro_sga.cpp @@ -93,13 +93,14 @@ WRITE32_MEMBER(interpro_sga_device::ddtc1_w) // when complete, we indicate by setting DMAEND(2) - 2 is probably the channel // we also turn off the INTBERR and INTMMBE flags - m_ipoll &= ~(0x20000 | 0x10000); + m_ipoll &= ~(IPOLL_INTBERR | IPOLL_INTMMBE); m_ipoll |= 0x200; +#if 0 // if the address is invalid, fake a bus error if ((m_dspad1 & 0xfffff000) == 0x40000000 || (m_ddpad1 & 0xfffff) == 0x40000000) { - m_ipoll |= 0x10000; + m_ipoll |= IPOLL_INTBERR; // error cycle - bit 0x10 indicates source address error (dspad1) // now expecting 0x5463? @@ -112,4 +113,5 @@ WRITE32_MEMBER(interpro_sga_device::ddtc1_w) // 0x5433 = BERR|SNAPOK | BG(ICAMMU)? | CT(33) // 0x5463 = BERR|SNAPOK | BG(ICAMMU)? | TAG(1) | CT(23) } +#endif } diff --git a/src/mame/machine/interpro_sga.h b/src/mame/machine/interpro_sga.h index 4232a436fa1..eb6d3a63fdf 100644 --- a/src/mame/machine/interpro_sga.h +++ b/src/mame/machine/interpro_sga.h @@ -20,21 +20,60 @@ public: DECLARE_READ32_MEMBER(gcsr_r) { return m_gcsr; } DECLARE_WRITE32_MEMBER(gcsr_w) { m_gcsr = data; } + enum ipoll_mask + { + IPOLL_ATTN = 0x000000ff, + IPOLL_DMAEND = 0x00000700, + IPOLL_NOGRANT = 0x00001000, + IPOLL_SRMMBE = 0x00002000, + IPOLL_SRBERR = 0x00004000, + IPOLL_RETRYABORT = 0x00008000, + IPOLL_INTBERR = 0x00010000, + IPOLL_INTMMBE = 0x00020000 + }; DECLARE_READ32_MEMBER(ipoll_r) { return m_ipoll; } DECLARE_WRITE32_MEMBER(ipoll_w) { m_ipoll = data; } + + enum imask_mask + { + IMASK_DMAENDCH1 = 0x00000200, + IMASK_NOGRANT = 0x00001000, + IMASK_SRMMBE = 0x00002000, + IMASK_SRBERR = 0x00004000, + IMASK_RETRYABORT = 0x00008000, + IMASK_INTBERR = 0x00010000, + IMASK_INTMMBE = 0x00020000 + }; DECLARE_READ32_MEMBER(imask_r) { return m_imask; } DECLARE_WRITE32_MEMBER(imask_w) { m_imask = data; } DECLARE_READ32_MEMBER(range_base_r) { return m_range_base; } DECLARE_WRITE32_MEMBER(range_base_w) { m_range_base = data; } DECLARE_READ32_MEMBER(range_end_r) { return m_range_end; } DECLARE_WRITE32_MEMBER(range_end_w) { m_range_end = data; } + + enum cttag_mask + { + CTTAG_TAG = 0x00000007, + CTTAG_CYCLE = 0x000001f8, + CTTAG_MAXBCLK = 0x0003fe00, + CTTAG_MAXRETRY = 0x3ffc0000 + }; DECLARE_READ32_MEMBER(cttag_r) { return m_cttag; } DECLARE_WRITE32_MEMBER(cttag_w) { m_cttag = data; } DECLARE_READ32_MEMBER(address_r) { return m_address; } DECLARE_WRITE32_MEMBER(address_w) { m_address = data; } + + enum dmacsr_mask + { + DMACSR_CH1ENABLE = 0x00000080 + }; DECLARE_READ32_MEMBER(dmacsr_r) { return m_dmacsr; } DECLARE_WRITE32_MEMBER(dmacsr_w) { m_dmacsr = data; } + enum edmacsr_mask + { + EDMACSR_CH1RDONLY = 0x00000010 + }; DECLARE_READ32_MEMBER(edmacsr_r) { return m_edmacsr; } DECLARE_WRITE32_MEMBER(edmacsr_w) { m_edmacsr = data; } DECLARE_READ32_MEMBER(reg6_range_r) { return m_reg6_range; } diff --git a/src/mame/machine/interpro_srarb.cpp b/src/mame/machine/interpro_srarb.cpp index a389a272317..d3074ea2847 100644 --- a/src/mame/machine/interpro_srarb.cpp +++ b/src/mame/machine/interpro_srarb.cpp @@ -25,6 +25,9 @@ DEVICE_ADDRESS_MAP_START(map, 32, interpro_srarb_device) AM_RANGE(0x14, 0x17) AM_READWRITE(errdomhi_r, errdomhi_w) AM_RANGE(0x18, 0x1b) AM_READWRITE(tmctrl_r, tmctrl_w) + AM_RANGE(0x1c, 0x1f) AM_READWRITE8(unknown0_r, unknown0_w, 0x0000ff00) // boot code writes 0x10 + AM_RANGE(0x20, 0x23) AM_READWRITE8(unknown1_r, unknown1_w, 0x0000ff00) // boot code writes 0x07 + AM_RANGE(0x24, 0x27) AM_READWRITE(tmsrnem_r, tmsrnem_w) AM_RANGE(0x28, 0x2b) AM_READWRITE(tmsrhog_r, tmsrhog_w) AM_RANGE(0x2c, 0x2f) AM_READWRITE(tmscale_r, tmscale_w) diff --git a/src/mame/machine/interpro_srarb.h b/src/mame/machine/interpro_srarb.h index f1b5c9a34d5..d9adccddf20 100644 --- a/src/mame/machine/interpro_srarb.h +++ b/src/mame/machine/interpro_srarb.h @@ -15,6 +15,12 @@ public: DECLARE_READ32_MEMBER(sdepid_r) { return sdepid; } DECLARE_WRITE32_MEMBER(sdepid_w) { sdepid = data; } + + enum snapid_mask + { + SNAPID_GRANT = 0x0000000f, + SNAPID_HOGLOCK = 0x000000f0 + }; DECLARE_READ32_MEMBER(snapid_r) { return snapid; } DECLARE_WRITE32_MEMBER(snapid_w) { snapid = data; } DECLARE_READ32_MEMBER(prilo_r) { return prilo; } @@ -27,8 +33,20 @@ public: DECLARE_READ32_MEMBER(errdomhi_r) { return errdomhi; } DECLARE_WRITE32_MEMBER(errdomhi_w) { errdomhi = data; } + enum tmctrl_mask + { + TMCTRL_UNUSED = 0x00000007, + TMCTRL_ENNEM = 0x00000008, + TMCTRL_ENHOG = 0x00000010 + }; DECLARE_READ32_MEMBER(tmctrl_r) { return tmctrl; } DECLARE_WRITE32_MEMBER(tmctrl_w) { tmctrl = data; } + + DECLARE_READ8_MEMBER(unknown0_r) { return unknown0; } + DECLARE_WRITE8_MEMBER(unknown0_w) { unknown0 = data; } + DECLARE_READ8_MEMBER(unknown1_r) { return unknown1; } + DECLARE_WRITE8_MEMBER(unknown1_w) { unknown1 = data; } + DECLARE_READ32_MEMBER(tmsrnem_r) { return tmsrnem; } DECLARE_WRITE32_MEMBER(tmsrnem_w) { tmsrnem = data; } DECLARE_READ32_MEMBER(tmsrhog_r) { return tmsrhog; } @@ -44,6 +62,8 @@ private: u32 sdepid, snapid, prilo, prihi; u32 errdomlo, errdomhi; u32 tmctrl, tmsrnem, tmsrhog, tmscale; + + u8 unknown0, unknown1; }; // device type definition |