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author Roberto Fresca <robbie@robertofresca.com>2025-09-17 10:29:03 +0200
committer Roberto Fresca <robbie@robertofresca.com>2025-09-17 10:29:03 +0200
commit7259f7600ec735da3f6b0073e8e8b9781ad8ac94 (patch)
tree39800945ad7f047a68514e84285aece9c45ce70c
parent972f9c66d204a5ab9229617f9aeed4b3169bc821 (diff)
Lucky Line III improvements: [Roberto Fresca, Grull Osgo]
- Added workaround to defeat initial protection. - Bypassed the port 10h protection (disabling video). - Created new memory map. - Created new machine config. - Created new inputs from the scratch. Systems promoted to working --------------------------- Lucky Line III (ver 2.00, Wang QL-1 v3.03) [Roberto Fresca, Grull Osgo]
-rw-r--r--src/mame/igs/goldstar.cpp132
1 files changed, 125 insertions, 7 deletions
diff --git a/src/mame/igs/goldstar.cpp b/src/mame/igs/goldstar.cpp
index 26a168a30ea..91490898a32 100644
--- a/src/mame/igs/goldstar.cpp
+++ b/src/mame/igs/goldstar.cpp
@@ -1,5 +1,5 @@
// license:BSD-3-Clause
-// copyright-holders: David Haywood, Roberto Fresca, Vas Crabb
+// copyright-holders: David Haywood, Roberto Fresca, Grull Osgo, Vas Crabb
/***************************************************************************
@@ -444,8 +444,9 @@ public:
void eldoradd(machine_config &config) ATTR_COLD;
void eldoraddoa(machine_config &config) ATTR_COLD;
void jkrmast(machine_config &config) ATTR_COLD;
- void pkrmast(machine_config &config) ATTR_COLD;
+ void ll3(machine_config &config) ATTR_COLD;
void nfm(machine_config &config) ATTR_COLD;
+ void pkrmast(machine_config &config) ATTR_COLD;
void reelmg(machine_config &config) ATTR_COLD;
void super7(machine_config &config) ATTR_COLD;
@@ -492,8 +493,8 @@ public:
void init_tonypok() ATTR_COLD;
void init_reelmag() ATTR_COLD;
void init_rm7b() ATTR_COLD;
- template <uint8_t Xor_value> void init_tsk() ATTR_COLD;
void init_wcat3a() ATTR_COLD;
+ template <uint8_t Xor_value> void init_tsk() ATTR_COLD;
protected:
virtual void video_start() override ATTR_COLD;
@@ -534,6 +535,7 @@ private:
void eldoraddoa_portmap(address_map &map) ATTR_COLD;
void jkrmast_map(address_map &map) ATTR_COLD;
void jkrmast_portmap(address_map &map) ATTR_COLD;
+ void ll3_map(address_map &map) ATTR_COLD;
void nfm_map(address_map &map) ATTR_COLD;
void nfm_portmap(address_map &map) ATTR_COLD;
void pkrmast_portmap(address_map &map) ATTR_COLD;
@@ -542,7 +544,6 @@ private:
void super7_portmap(address_map &map) ATTR_COLD;
void ramdac_map(address_map &map) ATTR_COLD;
-
// installed by various driver init handlers to get stuff to work
template <uint8_t V> uint8_t fixedval_r() { return V; }
};
@@ -1151,7 +1152,7 @@ void cmaster_state::outport0_w(uint8_t data)
xxxx ---- unused?
*/
- //popmessage("outport %02x",data);
+ // popmessage("outport %02x",data);
m_enable_reg = data;
}
@@ -2333,6 +2334,31 @@ void cmaster_state::cm_map(address_map &map)
map(0xfc80, 0xffff).ram();
}
+
+void cmaster_state::ll3_map(address_map &map)
+{
+ map(0x0000, 0xbfff).rom().nopw();
+
+ map(0xc000, 0xc7ff).ram();
+ map(0xc800, 0xcfff).ram().share("nvram");
+ map(0xd000, 0xdfff).ram();
+
+ map(0xe000, 0xe7ff).ram().w(FUNC(cmaster_state::fg_vidram_w)).share(m_fg_vidram);
+ map(0xe800, 0xefff).ram().w(FUNC(cmaster_state::fg_atrram_w)).share(m_fg_atrram);
+
+ map(0xf000, 0xf1ff).ram().w(FUNC(cmaster_state::reel_ram_w<0>)).share(m_reel_ram[0]);
+ map(0xf200, 0xf3ff).ram().w(FUNC(cmaster_state::reel_ram_w<1>)).share(m_reel_ram[1]);
+ map(0xf400, 0xf5ff).ram().w(FUNC(cmaster_state::reel_ram_w<2>)).share(m_reel_ram[2]);
+ map(0xf600, 0xf7ff).ram();
+
+ map(0xf800, 0xf87f).ram().share(m_reel_scroll[0]);
+ map(0xf880, 0xf9ff).ram();
+ map(0xfa00, 0xfa7f).ram().share(m_reel_scroll[1]);
+ map(0xfa80, 0xfbff).ram();
+ map(0xfc00, 0xfc7f).ram().share(m_reel_scroll[2]);
+ map(0xfc80, 0xffff).ram();
+}
+
void cmaster_state::super7_map(address_map &map)
{
map(0x0000, 0xcfff).rom().nopw();
@@ -3984,6 +4010,82 @@ static INPUT_PORTS_START( cm_nodsw )
INPUT_PORTS_END
+static INPUT_PORTS_START( ll3 )
+
+ PORT_START("IN0")
+ PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_GAMBLE_HIGH ) PORT_CODE(KEYCODE_B) PORT_NAME("Big")
+ PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_GAMBLE_TAKE ) PORT_CODE(KEYCODE_X) PORT_NAME("Take")
+ PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_BET ) PORT_CODE(KEYCODE_Z) PORT_CODE(KEYCODE_C) PORT_NAME("Bet / D-UP")
+ PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_LOW ) PORT_CODE(KEYCODE_V) PORT_NAME("Small / Info")
+ PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START1 ) PORT_CODE(KEYCODE_N) PORT_NAME("Start")
+
+ PORT_START("IN1")
+ PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SLOT_STOP2 ) PORT_CODE(KEYCODE_K) PORT_CODE(KEYCODE_2_PAD) // Stop B
+ PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SLOT_STOP1 ) PORT_CODE(KEYCODE_J) PORT_CODE(KEYCODE_1_PAD) // Stop A
+ PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2) PORT_NAME("Coin B")
+ PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SLOT_STOP3 ) PORT_CODE(KEYCODE_L) PORT_CODE(KEYCODE_3_PAD) // Stop C
+ PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN4 ) PORT_IMPULSE(2) PORT_NAME("Coin D")
+ PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_IMPULSE(2) PORT_NAME("Coin C")
+ PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_KEYIN )
+ PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2) PORT_NAME("Coin A")
+
+ PORT_INCLUDE( cmv4_service )
+
+ PORT_START("DSW1")
+ PORT_DIPUNKNOWN_DIPLOC(0x01, 0x01, "DSW1:1")
+ PORT_DIPUNKNOWN_DIPLOC(0x02, 0x02, "DSW1:2")
+ PORT_DIPUNKNOWN_DIPLOC(0x04, 0x04, "DSW1:3")
+ PORT_DIPUNKNOWN_DIPLOC(0x08, 0x08, "DSW1:4")
+ PORT_DIPUNKNOWN_DIPLOC(0x10, 0x10, "DSW1:5")
+ PORT_DIPUNKNOWN_DIPLOC(0x20, 0x20, "DSW1:6")
+ PORT_DIPUNKNOWN_DIPLOC(0x40, 0x40, "DSW1:7")
+ PORT_DIPUNKNOWN_DIPLOC(0x80, 0x80, "DSW1:8")
+
+ PORT_START("DSW2")
+ PORT_DIPUNKNOWN_DIPLOC(0x01, 0x01, "DSW2:1")
+ PORT_DIPUNKNOWN_DIPLOC(0x02, 0x02, "DSW2:2")
+ PORT_DIPUNKNOWN_DIPLOC(0x04, 0x04, "DSW2:3")
+ PORT_DIPUNKNOWN_DIPLOC(0x08, 0x08, "DSW2:4")
+ PORT_DIPUNKNOWN_DIPLOC(0x10, 0x10, "DSW2:5")
+ PORT_DIPUNKNOWN_DIPLOC(0x20, 0x20, "DSW2:6")
+ PORT_DIPUNKNOWN_DIPLOC(0x40, 0x40, "DSW2:7")
+ PORT_DIPUNKNOWN_DIPLOC(0x80, 0x80, "DSW2:8")
+
+ PORT_START("DSW3")
+ PORT_DIPUNKNOWN_DIPLOC(0x01, 0x01, "DSW3:1")
+ PORT_DIPUNKNOWN_DIPLOC(0x02, 0x02, "DSW3:2")
+ PORT_DIPUNKNOWN_DIPLOC(0x04, 0x04, "DSW3:3")
+ PORT_DIPUNKNOWN_DIPLOC(0x08, 0x08, "DSW3:4")
+ PORT_DIPUNKNOWN_DIPLOC(0x10, 0x10, "DSW3:5")
+ PORT_DIPUNKNOWN_DIPLOC(0x20, 0x20, "DSW3:6")
+ PORT_DIPUNKNOWN_DIPLOC(0x40, 0x40, "DSW3:7")
+ PORT_DIPUNKNOWN_DIPLOC(0x80, 0x80, "DSW3:8")
+
+ PORT_START("DSW4")
+ PORT_DIPUNKNOWN_DIPLOC(0x01, 0x01, "DSW4:1")
+ PORT_DIPUNKNOWN_DIPLOC(0x02, 0x02, "DSW4:2")
+ PORT_DIPUNKNOWN_DIPLOC(0x04, 0x04, "DSW4:3")
+ PORT_DIPUNKNOWN_DIPLOC(0x08, 0x08, "DSW4:4")
+ PORT_DIPUNKNOWN_DIPLOC(0x10, 0x10, "DSW4:5")
+ PORT_DIPUNKNOWN_DIPLOC(0x20, 0x20, "DSW4:6")
+ PORT_DIPUNKNOWN_DIPLOC(0x40, 0x40, "DSW4:7")
+ PORT_DIPUNKNOWN_DIPLOC(0x80, 0x80, "DSW4:8")
+
+ PORT_START("DSW5")
+ PORT_DIPUNKNOWN_DIPLOC(0x01, 0x01, "DSW5:1")
+ PORT_DIPUNKNOWN_DIPLOC(0x02, 0x02, "DSW5:2")
+ PORT_DIPUNKNOWN_DIPLOC(0x04, 0x04, "DSW5:3")
+ PORT_DIPUNKNOWN_DIPLOC(0x08, 0x08, "DSW5:4")
+ PORT_DIPUNKNOWN_DIPLOC(0x10, 0x10, "DSW5:5")
+ PORT_DIPUNKNOWN_DIPLOC(0x20, 0x20, "DSW5:6")
+ PORT_DIPUNKNOWN_DIPLOC(0x40, 0x40, "DSW5:7")
+ PORT_DIPUNKNOWN_DIPLOC(0x80, 0x80, "DSW5:8")
+INPUT_PORTS_END
+
+
static INPUT_PORTS_START( cmezspin )
PORT_START("IN0")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -12158,6 +12260,12 @@ void cmaster_state::eldoradd(machine_config &config)
m_gfxdecode->set_info(gfx_cmast97); // TODO: wrong, needs correct decode
}
+void cmaster_state::ll3(machine_config &config)
+{
+ cm(config);
+
+ m_maincpu->set_addrmap(AS_PROGRAM, &cmaster_state::ll3_map);
+}
void wingco_state::masked_irq(int state)
@@ -25154,6 +25262,16 @@ void cmaster_state::init_ll3() // verified with ICE dump
std::swap_ranges(&rom[0x1800], &rom[0x2000], &rom[0x4800]);
std::swap_ranges(&rom[0x2800], &rom[0x3000], &rom[0xa800]);
std::swap_ranges(&rom[0x6800], &rom[0x7000], &rom[0x9800]);
+
+ rom[0x8a] = 0;
+ rom[0x8b] = 0;
+ rom[0x8c] = 0;
+
+ // NOP'ing the writes to port 10h (video register)
+ // all the writes have masked the bit1 ON, getting
+ // the video totally disabled. Surely for protection.
+ rom[0x0b2c] = 0x00;
+ rom[0x0b2d] = 0x00;
}
void goldstar_state::init_palnibbles()
@@ -26545,11 +26663,11 @@ GAMEL( 1991, skdelux2k, cmaster, cm, cmasterb, cmaster_state, init_cmv4
GAMEL( 1991, skdelux99, cmaster, cm, cmasterb, cmaster_state, init_cmv4, ROT0, "bootleg", "Florida Skill Deluxe 99 (FBV2 ver.T)", 0, layout_cmasterb )
GAMEL( 199?, super7, cmaster, super7, super7, cmaster_state, init_super7, ROT0, "bootleg", "Super Seven (ver. 2.3)", MACHINE_NOT_WORKING, layout_cmasterb ) // inputs / outputs needs verifying
GAME ( 199?, wcat3a, wcat3, chryangl, cmaster, cmaster_state, init_wcat3a, ROT0, "E.A.I.", "Wild Cat 3 (CMV4 hardware)", MACHINE_NOT_WORKING ) // does not boot. Wrong decryption, wrong machine or wrong what?
-GAMEL( 199?, ll3, cmaster, cm, cmasterb, cmaster_state, init_ll3, ROT0, "bootleg", "Lucky Line III", MACHINE_NOT_WORKING, layout_cmasterb ) // not looked at yet
+GAME ( 199?, ll3, cmaster, ll3, ll3, cmaster_state, init_ll3, ROT0, "bootleg", "Lucky Line III (ver 2.00, Wang QL-1 v3.03)", 0 ) // needs layout
GAMEL( 199?, cmfb55, cmaster, cmfb55, cmaster, cmaster_state, init_palnibbles,ROT0, "bootleg", "Cherry Master (bootleg, Game FB55 Ver.2)", MACHINE_NOT_WORKING, layout_cmv4 ) // inputs not done
GAMEL( 199?, hamhouse, cmaster, cm, cmaster, cmaster_state, init_hamhouse, ROT0, "bootleg", "Hamburger House", 0, layout_cmaster )
GAMEL( 199?, hamhouse9, cmaster, cm, cmaster, cmaster_state, init_hamhouse9, ROT0, "bootleg", "Hamburger House 9", 0, layout_cmaster )
-GAMEL( 199?, alienatt, cmaster, cm, cmv4, cmaster_state, init_alienatt, ROT0, "bootleg", "Allien Attack", 0, layout_cmv4 )
+GAMEL( 199?, alienatt, cmaster, cm, cmv4, cmaster_state, init_alienatt, ROT0, "bootleg", "Allien Attack (Game FBV2, ver.T)", 0, layout_cmv4 )
// sets with internal settings and no use of DSW banks
GAMEL( 1991, cmv4zg, cmv4, cmv4zg, cm_nodsw, cmaster_state, empty_init, ROT0, "hack", "Cherry Bonus III (Ziogas V4.1 hack, set 1)", 0, layout_cmv4 ) // uses default NVRAM