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author Nigel Barnes <Pernod70@users.noreply.github.com>2022-05-20 01:59:02 +0100
committer Nigel Barnes <Pernod70@users.noreply.github.com>2022-05-20 02:02:36 +0100
commit6e80edf3be0f788af0ab140c0e7e76dde8e28434 (patch)
tree25c792cc32962a93b2fa8582f20507ec72661b32
parentb6c0392fa9d162f98445ae48735e8e18b2e424e9 (diff)
bus/mtx/cfx: Do nothing when both CS0/CS1 are asserted.
-rw-r--r--src/devices/bus/mtx/cfx.cpp18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/devices/bus/mtx/cfx.cpp b/src/devices/bus/mtx/cfx.cpp
index 2bf6e5d23b0..0692abb3686 100644
--- a/src/devices/bus/mtx/cfx.cpp
+++ b/src/devices/bus/mtx/cfx.cpp
@@ -123,19 +123,19 @@ void mtx_cfx_device::portc_w(uint8_t data)
if (BIT(data, 7))
m_ide->reset();
- switch (BIT(data, 5, 2))
+ switch (BIT(data, 3, 2))
{
- case 0x01: // WRITE
- if (BIT(data, 3)) // CS0
+ case 0x01: // CS0
+ if (BIT(data, 5)) // WRITE
m_ide->cs0_w(data & 0x07, m_ide_data);
- else if (BIT(data, 4)) // CS1
- m_ide->cs1_w(data & 0x07, m_ide_data);
+ if (BIT(data, 6)) // READ
+ m_ide_data = m_ide->cs0_r(data & 0x07);
break;
- case 0x02: // READ
- if (BIT(data, 3)) // CS0
- m_ide_data = m_ide->cs0_r(data & 0x07);
- else if (BIT(data, 4)) // CS1
+ case 0x02: // CS1
+ if (BIT(data, 5)) // WRITE
+ m_ide->cs1_w(data & 0x07, m_ide_data);
+ if (BIT(data, 6)) // READ
m_ide_data = m_ide->cs1_r(data & 0x07);
break;
}