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authorGravatarGravatar AJR <ajrhacker@users.noreply.github.com>2018-08-09 12:16:17 -0400
committerGravatarGravatar AJR <ajrhacker@users.noreply.github.com>2018-08-09 12:16:17 -0400
commit6cfd636c604fc012eac8b19a4ff56b5e35e77693 (patch) (github)
tree1c7f3bdf3cd1bb9ad7811a651c19de5b890b5e6c
parent2123d4bc641822ff602fa15ab4fe45bcd89fd3c6 (diff)
downloadmame-6cfd636c604fc012eac8b19a4ff56b5e35e77693.tar.bz2
mame-6cfd636c604fc012eac8b19a4ff56b5e35e77693.zip
F8 documentation correction and improvement (nw)
-rw-r--r--src/devices/cpu/f8/f8.cpp21
-rw-r--r--src/devices/machine/f3853.cpp5
2 files changed, 21 insertions, 5 deletions
diff --git a/src/devices/cpu/f8/f8.cpp b/src/devices/cpu/f8/f8.cpp
index 136f6cec2a7..79ed7b9644e 100644
--- a/src/devices/cpu/f8/f8.cpp
+++ b/src/devices/cpu/f8/f8.cpp
@@ -7,6 +7,27 @@
* This work is based on Frank Palazzolo's F8 emulation in a standalone
* Fairchild Channel F emulator and the 'Fairchild F3850 CPU' data sheets.
*
+ * The 3850 CPU itself does not include the address bus, pointer registers
+ * or an interrupt controller. Those functions are provided by at least one
+ * of the following devices:
+ *
+ * - 3851 Program Storage Unit (PSU)
+ * - 3852 Dynamic Memory Interface (DMI)
+ * - 3853 Static Memory Interface (SMI)
+ * - 3856 Program Storage Unit (PSU)
+ * - 3861 Peripheral Input/Output (PIO)
+ * - 3871 Peripheral Input/Output (PIO)
+ *
+ * Of these support devices, the 3851 PSU includes 1024 bytes of mask ROM,
+ * and the 3856 PSU includes 2048 bytes of mask ROM; addressing for the PSU
+ * is also determined by mask option. The 3853 SMI may be used with external
+ * program ROMs.
+ *
+ * The PSU does not have DC0 and DC1, only DC0; as a result, it does not
+ * respond to the main CPU's DC0/DC1 swap instruction. This may lead to two
+ * devices responding to the same DC0 address and attempting to place their
+ * bytes on the data bus simultaneously!
+ *
*****************************************************************************/
#include "emu.h"
diff --git a/src/devices/machine/f3853.cpp b/src/devices/machine/f3853.cpp
index c3ba50dc39e..19e5a1b388a 100644
--- a/src/devices/machine/f3853.cpp
+++ b/src/devices/machine/f3853.cpp
@@ -10,11 +10,6 @@
Based on a datasheet obtained from www.freetradezone.com
- The SMI does not have DC0 and DC1, only DC0; as a result, it does
- not respond to the main CPU's DC0/DC1 swap instruction. This may
- lead to two devices responding to the same DC0 address and
- attempting to place their bytes on the data bus simultaneously!
-
8-bit shift register:
Feedback in0 = !((out3 ^ out4) ^ (out5 ^ out7))
Interrupts are at 0xfe