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author | Sandro Ronco <sandro.ronco@gmx.com> | 2021-01-03 00:04:42 +0100 |
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committer | Sandro Ronco <sandro.ronco@gmx.com> | 2021-01-03 00:04:42 +0100 |
commit | 6bceee5c4beb626f1e1259aa1b1f7fc2a166f8a0 (patch) | |
tree | d3f6b63d6f6fe65a99a1c9708887157485409de2 | |
parent | 11c30f91accb22f091a84bf1ca4a974de0aa3ed1 (diff) |
ARM: fix carry flag in ADC instruction. [Sandro Ronco]
-rw-r--r-- | src/devices/cpu/arm/arm.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/devices/cpu/arm/arm.cpp b/src/devices/cpu/arm/arm.cpp index 13a6cf7c64b..ac80af28531 100644 --- a/src/devices/cpu/arm/arm.cpp +++ b/src/devices/cpu/arm/arm.cpp @@ -765,7 +765,7 @@ void arm_cpu_device::HandleMemSingle( uint32_t insn ) ((R15 &~ (N_MASK | Z_MASK | V_MASK | C_MASK)) \ | (((!SIGN_BITS_DIFFER(rn, op2)) && SIGN_BITS_DIFFER(rn, rd)) \ << V_BIT) \ - | (((~(rn)) < (op2)) << C_BIT) \ + | (((IsNeg(rn) & IsNeg(op2)) | (IsNeg(rn) & IsPos(rd)) | (IsNeg(op2) & IsPos(rd))) ? C_MASK : 0) \ | HandleALUNZFlags(rd)) \ + 4; \ else R15 += 4; |