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author yz70s <yz70s@users.noreply.github.com>2020-02-11 09:35:48 +0100
committer yz70s <yz70s@users.noreply.github.com>2020-02-12 00:13:29 +0100
commit6b3a689ce15e5536034a7b288dce31bc6b20073f (patch)
tree6bccf98da4f551d750e8e911fd10396236ec06b8
parenta0a658a11148f3dac497d24a3eb16460df9b69c0 (diff)
naomi: converted 315-6154 device into a real pci host [Samuele Zannoli]
And updated dimm board accordingly.
-rw-r--r--src/mame/machine/315-6154.cpp49
-rw-r--r--src/mame/machine/315-6154.h13
-rw-r--r--src/mame/machine/naomigd.cpp195
-rw-r--r--src/mame/machine/naomigd.h49
4 files changed, 218 insertions, 88 deletions
diff --git a/src/mame/machine/315-6154.cpp b/src/mame/machine/315-6154.cpp
index 940c1b8c144..a3a6ec87162 100644
--- a/src/mame/machine/315-6154.cpp
+++ b/src/mame/machine/315-6154.cpp
@@ -7,10 +7,9 @@
DEFINE_DEVICE_TYPE(SEGA315_6154, sega_315_6154_device, "sega315_6154", "Sega 315-6154 Northbridge")
sega_315_6154_device::sega_315_6154_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : device_t(mconfig, SEGA315_6154, tag, owner, clock),
- device_memory_interface(mconfig, *this),
- m_memory_config("memory", ENDIANNESS_LITTLE, 32, 32),
- m_configuration_config("configuration", ENDIANNESS_LITTLE, 32, 32)
+ : pci_host_device(mconfig, SEGA315_6154, tag, owner, clock),
+ m_configuration_config("configuration_space", ENDIANNESS_LITTLE, 32, 20),
+ m_memory_config("memory_space", ENDIANNESS_LITTLE, 32, 32)
{
memset(m_registers, 0, sizeof(m_registers));
memset(m_bases, 0, sizeof(m_bases));
@@ -20,8 +19,19 @@ sega_315_6154_device::sega_315_6154_device(const machine_config &mconfig, const
void sega_315_6154_device::device_start()
{
- m_memory = &space(AS_PCI_MEMORY);
- m_configuration = &space(AS_PCI_CONFIGURATION);
+ pci_host_device::device_start();
+ memory_space = &space(AS_PCI_MEMORY);
+ // never unmap addresses lower than start
+ memory_window_start = 0x80000000;
+ memory_window_end = 0xffffffff;
+ memory_offset = 0;
+
+ m_configuration = &space(AS_PCI_CONFIG);
+
+ io_space = memory_space;
+ io_window_start = 0xc0000000;
+ io_window_end = 0xc000ffff;
+ io_offset = 0xc0000000;
save_item(NAME(m_registers));
save_item(NAME(m_bases));
@@ -31,17 +41,34 @@ void sega_315_6154_device::device_start()
void sega_315_6154_device::device_reset()
{
+ pci_host_device::device_reset();
memset(m_registers, 0, sizeof(m_registers));
}
device_memory_interface::space_config_vector sega_315_6154_device::memory_space_config() const
{
return space_config_vector{
- std::make_pair(AS_PCI_MEMORY, &m_memory_config),
- std::make_pair(AS_PCI_CONFIGURATION, &m_configuration_config)
+ std::make_pair(AS_PCI_CONFIG, &m_configuration_config),
+ std::make_pair(AS_PCI_MEMORY, &m_memory_config)
};
}
+void sega_315_6154_device::regenerate_config_mapping()
+{
+ // like pci_bridge_device::regenerate_config_mapping() in pci.cpp
+ // but each device n is assigned bit n+11 in the configuration space
+ // devices in different buses must have different numbers
+ address_space *config_space = &space(AS_PCI_CONFIG);
+ config_space->unmap_readwrite(0x00000, 0xfffff);
+ for (int i = 0; i < 9; i++)
+ if (sub_devices[i])
+ {
+ const int s = i >> 3;
+ const int o = (i & 7) << 8;
+ config_space->install_device((0x800 << s) + o, ((0x800 << s) + o) | 0xff, *sub_devices[i], &pci_device::config_map);
+ }
+}
+
READ32_MEMBER(sega_315_6154_device::registers_r)
{
return m_registers[offset];
@@ -85,7 +112,7 @@ WRITE32_MEMBER(sega_315_6154_device::registers_w)
logerror("got dma transfer request from 0x%08x to 0x%08x size 0x%08x bytes\n", s, d, l << 2);
while (l != 0)
{
- m_memory->write_dword(d, m_memory->read_dword(s));
+ memory_space->write_dword(d, memory_space->read_dword(s));
s += 4;
d += 4;
l--;
@@ -106,7 +133,7 @@ u32 sega_315_6154_device::aperture_r(address_space &space, offs_t offset, u32 me
return m_configuration->read_dword(destination_offset << 2, mem_mask);
if ((Aperture == 1) && (destination == 0) && (m_useconfig_18x == true))
return m_configuration->read_dword(destination_offset << 2, mem_mask);
- return m_memory->read_dword(m_bases[index] + (destination_offset << 2), mem_mask);
+ return memory_space->read_dword(m_bases[index] + (destination_offset << 2), mem_mask);
}
template u32 sega_315_6154_device::aperture_r<0>(address_space &space, offs_t offset, u32 mem_mask);
@@ -130,7 +157,7 @@ void sega_315_6154_device::aperture_w(address_space &space, offs_t offset, u32 d
m_configuration->write_dword(destination_offset << 2, data, mem_mask);
return;
}
- m_memory->write_dword(m_bases[index] + (destination_offset << 2), data, mem_mask);
+ memory_space->write_dword(m_bases[index] + (destination_offset << 2), data, mem_mask);
}
template void sega_315_6154_device::aperture_w<0>(address_space &space, offs_t offset, u32 data, u32 mem_mask);
diff --git a/src/mame/machine/315-6154.h b/src/mame/machine/315-6154.h
index 815fb767b72..a80397fac14 100644
--- a/src/mame/machine/315-6154.h
+++ b/src/mame/machine/315-6154.h
@@ -5,14 +5,16 @@
#pragma once
+#include "machine/pci.h"
+
DECLARE_DEVICE_TYPE(SEGA315_6154, sega_315_6154_device)
-class sega_315_6154_device : public device_t, public device_memory_interface
+class sega_315_6154_device : public pci_host_device
{
public:
// construction/destruction
sega_315_6154_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- address_space *memory() { return m_memory; }
+ address_space *memory() { return memory_space; }
DECLARE_READ32_MEMBER(registers_r);
DECLARE_WRITE32_MEMBER(registers_w);
@@ -22,8 +24,7 @@ public:
void aperture_w(address_space &space, offs_t offset, u32 data, u32 mem_mask = 0xffffffff);
enum {
- AS_PCI_MEMORY = 0,
- AS_PCI_CONFIGURATION = 1
+ AS_PCI_MEMORY = 1
};
protected:
@@ -32,11 +33,11 @@ protected:
// device_memory_interface overrides
virtual space_config_vector memory_space_config() const override;
+ virtual void regenerate_config_mapping() override;
private:
- address_space_config m_memory_config;
address_space_config m_configuration_config;
- address_space *m_memory;
+ address_space_config m_memory_config;
address_space *m_configuration;
u32 m_registers[0x100 / 4];
diff --git a/src/mame/machine/naomigd.cpp b/src/mame/machine/naomigd.cpp
index e4bbea9962e..a249a8240cf 100644
--- a/src/mame/machine/naomigd.cpp
+++ b/src/mame/machine/naomigd.cpp
@@ -401,6 +401,117 @@ void naomi_gdrom_board::write_from_qword(uint8_t *region, uint64_t qword)
region[i] = qword >> (56-(i*8));
}
+// For ide gdrom controller
+
+DEFINE_DEVICE_TYPE(IDE_GDROM, idegdrom_device, "ide_gdrom", "ide gdrom controller")
+
+idegdrom_device::idegdrom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, const char *image_tag, const char *space_tag, int space_id)
+ : idegdrom_device(mconfig, tag, owner, clock)
+{
+ space_owner_tag = space_tag;
+ space_owner_id = space_id;
+}
+
+idegdrom_device::idegdrom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : pci_device(mconfig, IDE_GDROM, tag, owner, clock),
+ m_ide(*this, "ide"),
+ irq_cb(*this)
+{
+ set_ids(0x11db189d, 0, 0, 0); // 0x10221000 or 0x00011172 possible too
+}
+
+void idegdrom_device::device_start()
+{
+ pci_device::device_start();
+ irq_cb.resolve_safe();
+ add_map(0x00000020, M_IO, FUNC(idegdrom_device::map_command));
+ bank_infos[0].adr = 0x01c0;
+ // pci system does not support base addresses not multiples of size
+ add_map(0x00000020, M_IO | M_DISABLED, FUNC(idegdrom_device::map_control));
+ bank_infos[1].adr = 0x03b0;
+ add_map(0x00000010, M_IO, FUNC(idegdrom_device::map_dma));
+ bank_infos[2].adr = 0xcc00;
+ command = 0x0083;
+}
+
+void idegdrom_device::device_reset()
+{
+ pci_device::device_reset();
+}
+
+void idegdrom_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
+ uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space)
+{
+ io_space->install_device(io_offset + 0x03b0, io_offset + 0x03cf, *static_cast<idegdrom_device*>(this), &idegdrom_device::map_control);
+}
+
+static void gdrom_devices(device_slot_interface &device)
+{
+ device.option_add(":gdrom", GDROM);
+}
+
+
+WRITE_LINE_MEMBER(idegdrom_device::ide_irq)
+{
+ irq_cb(state);
+}
+
+void idegdrom_device::device_add_mconfig(machine_config &config)
+{
+ BUS_MASTER_IDE_CONTROLLER(config, m_ide).options(gdrom_devices, ":gdrom", nullptr, true);
+ m_ide->irq_handler().set(*this, FUNC(idegdrom_device::ide_irq));
+ m_ide->set_bus_master_space(space_owner_tag, space_owner_id);
+}
+
+void idegdrom_device::map_command(address_map &map)
+{
+ map(0x0000, 0x001f).rw(FUNC(idegdrom_device::ide_cs0_r), FUNC(idegdrom_device::ide_cs0_w));
+}
+
+void idegdrom_device::map_control(address_map &map)
+{
+ map(0x0000, 0x001f).rw(FUNC(idegdrom_device::ide_cs1_r), FUNC(idegdrom_device::ide_cs1_w));
+}
+
+void idegdrom_device::map_dma(address_map &map)
+{
+ map(0x0000, 0x000f).rw("ide", FUNC(bus_master_ide_controller_device::bmdma_r), FUNC(bus_master_ide_controller_device::bmdma_w));
+}
+
+READ32_MEMBER(idegdrom_device::ide_cs0_r)
+{
+ const int o = offset >> 2;
+ const int r = (offset & 3) << 3;
+
+ return m_ide->cs0_r(space, o, mem_mask << r) >> r;
+}
+
+READ32_MEMBER(idegdrom_device::ide_cs1_r)
+{
+ const int o = offset >> 2;
+ const int r = (offset & 3) << 3;
+
+ return m_ide->cs1_r(space, o, mem_mask << r) >> r;
+}
+
+WRITE32_MEMBER(idegdrom_device::ide_cs0_w)
+{
+ const int o = offset >> 2;
+ const int r = (offset & 3) << 3;
+
+ m_ide->cs0_w(space, o, data << r, mem_mask << r);
+}
+
+WRITE32_MEMBER(idegdrom_device::ide_cs1_w)
+{
+ const int o = offset >> 2;
+ const int r = (offset & 3) << 3;
+
+ m_ide->cs1_w(space, o, data << r, mem_mask << r);
+}
+
+// The board
+
naomi_gdrom_board::naomi_gdrom_board(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: naomi_board(mconfig, NAOMI_GDROM_BOARD, tag, owner, clock),
m_maincpu(*this, "dimmcpu"),
@@ -408,8 +519,8 @@ naomi_gdrom_board::naomi_gdrom_board(const machine_config &mconfig, const char *
m_i2c0(*this, "i2c_0"),
m_i2c1(*this, "i2c_1"),
m_eeprom(*this, "eeprom"),
- m_315_6154(*this, "northbridge"),
- m_ide(*this, "ide"),
+ m_315_6154(*this, "pci:00.0"),
+ m_idegdrom(*this, "pci:01.0"),
picdata(*this, finder_base::DUMMY_TAG),
dimm_command(0xffff),
dimm_offsetl(0xffff),
@@ -442,8 +553,8 @@ void naomi_gdrom_board::sh4_map(address_map &map)
{
map(0x00000000, 0x001fffff).mirror(0xa0000000).rom().region("bios", 0);
map(0x04000000, 0x040000ff).rw(m_315_6154, FUNC(sega_315_6154_device::registers_r), FUNC(sega_315_6154_device::registers_w));
- map(0x0c000000, 0x0cffffff).ram().share("sh4sdram");
- map(0x10000000, 0x103fffff).ram().share("6154sdram");
+ map(0x0c000000, 0x0cffffff).ram().share("pci:sh4sdram");
+ map(0x10000000, 0x103fffff).ram().share("pci:6154sdram");
map(0x14000000, 0x17ffffff).rw(m_315_6154, FUNC(sega_315_6154_device::aperture_r<0>), FUNC(sega_315_6154_device::aperture_w<0>));
map(0x18000000, 0x1bffffff).rw(m_315_6154, FUNC(sega_315_6154_device::aperture_r<1>), FUNC(sega_315_6154_device::aperture_w<1>));
map.unmap_value_high();
@@ -454,28 +565,22 @@ void naomi_gdrom_board::sh4_io_map(address_map &map)
map(0x00, 0x0f).rw(FUNC(naomi_gdrom_board::i2cmem_dimm_r), FUNC(naomi_gdrom_board::i2cmem_dimm_w));
}
-void naomi_gdrom_board::pci_map(address_map& map)
+void naomi_gdrom_board::pci_map(address_map &map)
{
- map(0x00000000, 0x00000003).rw(FUNC(naomi_gdrom_board::sh4_unknown_r), FUNC(naomi_gdrom_board::sh4_unknown_w));
- map(0x00000014, 0x00000017).rw(FUNC(naomi_gdrom_board::sh4_command_r), FUNC(naomi_gdrom_board::sh4_command_w));
- map(0x00000018, 0x0000001b).rw(FUNC(naomi_gdrom_board::sh4_offsetl_r), FUNC(naomi_gdrom_board::sh4_offsetl_w));
- map(0x0000001c, 0x0000001f).rw(FUNC(naomi_gdrom_board::sh4_parameterl_r), FUNC(naomi_gdrom_board::sh4_parameterl_w));
- map(0x00000020, 0x00000023).rw(FUNC(naomi_gdrom_board::sh4_parameterh_r), FUNC(naomi_gdrom_board::sh4_parameterh_w));
- map(0x00000024, 0x00000027).rw(FUNC(naomi_gdrom_board::sh4_status_r), FUNC(naomi_gdrom_board::sh4_status_w));
- map(0x00000028, 0x0000002b).rw(FUNC(naomi_gdrom_board::sh4_control_r), FUNC(naomi_gdrom_board::sh4_control_w));
+ const char *t = tag();
+
+ map(0x00000000, 0x00000003).rw(t, FUNC(naomi_gdrom_board::sh4_unknown_r), FUNC(naomi_gdrom_board::sh4_unknown_w));
+ map(0x00000014, 0x00000017).rw(t, FUNC(naomi_gdrom_board::sh4_command_r), FUNC(naomi_gdrom_board::sh4_command_w));
+ map(0x00000018, 0x0000001b).rw(t, FUNC(naomi_gdrom_board::sh4_offsetl_r), FUNC(naomi_gdrom_board::sh4_offsetl_w));
+ map(0x0000001c, 0x0000001f).rw(t, FUNC(naomi_gdrom_board::sh4_parameterl_r), FUNC(naomi_gdrom_board::sh4_parameterl_w));
+ map(0x00000020, 0x00000023).rw(t, FUNC(naomi_gdrom_board::sh4_parameterh_r), FUNC(naomi_gdrom_board::sh4_parameterh_w));
+ map(0x00000024, 0x00000027).rw(t, FUNC(naomi_gdrom_board::sh4_status_r), FUNC(naomi_gdrom_board::sh4_status_w));
+ map(0x00000028, 0x0000002b).rw(t, FUNC(naomi_gdrom_board::sh4_control_r), FUNC(naomi_gdrom_board::sh4_control_w));
map(0x0000002c, 0x0000002f).lr32([]() { return 0x0c; }, "Constant 0x0c"); // 0x0a or 0x0e possible too
- map(0x00000030, 0x00000033).rw(FUNC(naomi_gdrom_board::sh4_des_keyl_r), FUNC(naomi_gdrom_board::sh4_des_keyl_w));
- map(0x00000034, 0x00000037).rw(FUNC(naomi_gdrom_board::sh4_des_keyh_r), FUNC(naomi_gdrom_board::sh4_des_keyh_w));
+ map(0x00000030, 0x00000033).rw(t, FUNC(naomi_gdrom_board::sh4_des_keyl_r), FUNC(naomi_gdrom_board::sh4_des_keyl_w));
+ map(0x00000034, 0x00000037).rw(t, FUNC(naomi_gdrom_board::sh4_des_keyh_r), FUNC(naomi_gdrom_board::sh4_des_keyh_w));
map(0x70000000, 0x70ffffff).ram().share("sh4sdram");
map(0x78000000, 0x783fffff).ram().share("6154sdram");
- map(0xc00001c0, 0xc00001df).rw(FUNC(naomi_gdrom_board::ide_cs0_r), FUNC(naomi_gdrom_board::ide_cs0_w));
- map(0xc00003b0, 0xc00003cf).rw(FUNC(naomi_gdrom_board::ide_cs1_r), FUNC(naomi_gdrom_board::ide_cs1_w));
- map(0xc000cc00, 0xc000cc0f).rw(m_ide, FUNC(bus_master_ide_controller_device::bmdma_r), FUNC(bus_master_ide_controller_device::bmdma_w));
-}
-
-void naomi_gdrom_board::pci_config_map(address_map& map)
-{
- map(0x1000, 0x1003).lr32([]() { return 0x189d11db; }, "Constant 0x189d11db"); // 0x10001022 or 0x11720001 possible too
}
WRITE16_MEMBER(naomi_gdrom_board::dimm_command_w)
@@ -683,38 +788,6 @@ WRITE64_MEMBER(naomi_gdrom_board::i2cmem_dimm_w)
}
}
-READ32_MEMBER(naomi_gdrom_board::ide_cs0_r)
-{
- const int o = offset >> 2;
- const int r = (offset & 3) << 3;
-
- return m_ide->cs0_r(space, o, mem_mask << r) >> r;
-}
-
-READ32_MEMBER(naomi_gdrom_board::ide_cs1_r)
-{
- const int o = offset >> 2;
- const int r = (offset & 3) << 3;
-
- return m_ide->cs1_r(space, o, mem_mask << r) >> r;
-}
-
-WRITE32_MEMBER(naomi_gdrom_board::ide_cs0_w)
-{
- const int o = offset >> 2;
- const int r = (offset & 3) << 3;
-
- m_ide->cs0_w(space, o, data << r, mem_mask << r);
-}
-
-WRITE32_MEMBER(naomi_gdrom_board::ide_cs1_w)
-{
- const int o = offset >> 2;
- const int r = (offset & 3) << 3;
-
- m_ide->cs1_w(space, o, data << r, mem_mask << r);
-}
-
void naomi_gdrom_board::pic_map(address_map &map)
{
map(0x00, 0x1f).rw(FUNC(naomi_gdrom_board::pic_dimm_r), FUNC(naomi_gdrom_board::pic_dimm_w));
@@ -972,11 +1045,6 @@ void naomi_gdrom_board::board_advance(uint32_t size)
dimm_cur_address %= dimm_data_size;
}
-static void gdrom_devices(device_slot_interface& device)
-{
- device.option_add(":gdrom", GDROM);
-}
-
#define CPU_CLOCK 200000000 // need to set the correct value here
#define PIC_CLOCK 20000000 // and here
@@ -995,12 +1063,13 @@ void naomi_gdrom_board::device_add_mconfig(machine_config &config)
m_maincpu->set_sh4_clock(CPU_CLOCK);
m_maincpu->set_addrmap(AS_PROGRAM, &naomi_gdrom_board::sh4_map);
m_maincpu->set_addrmap(AS_IO, &naomi_gdrom_board::sh4_io_map);
+
+
+ PCI_ROOT(config, "pci", 0);
SEGA315_6154(config, m_315_6154, 0);
m_315_6154->set_addrmap(sega_315_6154_device::AS_PCI_MEMORY, &naomi_gdrom_board::pci_map);
- m_315_6154->set_addrmap(sega_315_6154_device::AS_PCI_CONFIGURATION, &naomi_gdrom_board::pci_config_map);
- BUS_MASTER_IDE_CONTROLLER(config, m_ide).options(gdrom_devices, ":gdrom", nullptr, true);
- m_ide->irq_handler().set_inputline(m_maincpu, SH4_IRL2);
- m_ide->set_bus_master_space(m_315_6154, sega_315_6154_device::AS_PCI_MEMORY);
+ IDE_GDROM(config, m_idegdrom, 0, image_tag, m_315_6154->tag(), sega_315_6154_device::AS_PCI_MEMORY);
+ m_idegdrom->irq_callback().set_inputline(m_maincpu, SH4_IRL2);
PIC16C622(config, m_securitycpu, PIC_CLOCK);
m_securitycpu->set_addrmap(AS_IO, &naomi_gdrom_board::pic_map);
m_securitycpu->set_config(0x3fff - 0x04);
diff --git a/src/mame/machine/naomigd.h b/src/mame/machine/naomigd.h
index 5756fe4585c..583528a556e 100644
--- a/src/mame/machine/naomigd.h
+++ b/src/mame/machine/naomigd.h
@@ -13,6 +13,43 @@
#include "machine/idectrl.h"
#include "machine/gdrom.h"
+// For ide gdrom controller
+
+class idegdrom_device : public pci_device {
+public:
+ idegdrom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, const char *image_tag, const char *space_tag, int space_id);
+ idegdrom_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+ auto irq_callback() { return irq_cb.bind(); }
+
+ virtual void device_add_mconfig(machine_config &config) override;
+
+ void map_command(address_map &map);
+ void map_control(address_map &map);
+ void map_dma(address_map &map);
+
+ DECLARE_READ32_MEMBER(ide_cs0_r);
+ DECLARE_READ32_MEMBER(ide_cs1_r);
+ DECLARE_WRITE32_MEMBER(ide_cs0_w);
+ DECLARE_WRITE32_MEMBER(ide_cs1_w);
+ DECLARE_WRITE_LINE_MEMBER(ide_irq);
+
+protected:
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
+ uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
+
+private:
+ required_device<bus_master_ide_controller_device> m_ide;
+ devcb_write_line irq_cb;
+ const char *space_owner_tag;
+ int space_owner_id;
+};
+
+DECLARE_DEVICE_TYPE(IDE_GDROM, idegdrom_device)
+
class naomi_gdrom_board : public naomi_board
{
public:
@@ -36,7 +73,7 @@ public:
naomi_gdrom_board(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual void device_add_mconfig(machine_config &config) override;
- virtual void submap(address_map& map) override;
+ virtual void submap(address_map &map) override;
void sh4_map(address_map &map);
void sh4_io_map(address_map &map);
void pic_map(address_map &map);
@@ -87,11 +124,6 @@ public:
DECLARE_READ8_MEMBER(pic_dimm_r);
DECLARE_WRITE8_MEMBER(pic_dimm_w);
- DECLARE_READ32_MEMBER(ide_cs0_r);
- DECLARE_READ32_MEMBER(ide_cs1_r);
- DECLARE_WRITE32_MEMBER(ide_cs0_w);
- DECLARE_WRITE32_MEMBER(ide_cs1_w);
-
protected:
virtual void device_start() override;
virtual void device_reset() override;
@@ -102,7 +134,7 @@ protected:
private:
enum { FILENAME_LENGTH=24 };
- const int work_mode = 0; // set to 1 and rebuild to enable the cpus
+ const int work_mode = 0; // set to 1 and rebuild to enable the cpus and full dimm board emulation
required_device<sh4_device> m_maincpu;
required_device<pic16c622_device> m_securitycpu;
@@ -110,7 +142,7 @@ private:
required_device<i2cmem_device> m_i2c1;
required_device<eeprom_serial_93cxx_device> m_eeprom;
required_device<sega_315_6154_device> m_315_6154;
- required_device<bus_master_ide_controller_device> m_ide;
+ required_device<idegdrom_device> m_idegdrom;
const char *image_tag;
optional_region_ptr<uint8_t> picdata;
@@ -159,4 +191,5 @@ private:
DECLARE_DEVICE_TYPE(NAOMI_GDROM_BOARD, naomi_gdrom_board)
+
#endif // MAME_MACHINE_NAOMIGD_H